Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.

The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas

Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)

Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi

Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names

have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.

Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been

made to the contents of the document, and these changes do not constitute any alteration to the

contents of the document itself.

Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices

and power devices.

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

To all our customers

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Description

Description

The M30220 group of single-chip microcomputers are built using the high-performance silicon gate CMOS

process using a M16C/60 Series CPU core. The M30220 group has LCD controller/driver. M30220 group is

packaged in a 144-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated

instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are ca-

pable of executing instructions at high speed.

Features

· Basic machine instructions .................. Compatible with the M16C/60 series

· Memory capacity .................................. See figure memory expansion

· Shortest instruction execution time ...... 100ns (f(X

)=10MHz)

· Supply voltage ..................................... 4.0V to 5.5V (f(X

)=10MHz)

2.7V to 5.5V (f(X

)=7MHz with software one-wait)

· Interrupts .............................................. 26 internal and 8 external interrupt sources, 4 software, 7 levels

(including key input interrupt)

· Multifunction 16-bit timer ...................... Timer A (output) x 8, timer B (input) x 6

· Real time port outputs .......................... 8 bits X 4 lines

· Serial I/O .............................................. 3 channel for UART or clock synchronous

· DMAC .................................................. 2 channels (trigger: 26 sources)

· A-D converter ....................................... 10 bits X 8 channels

· D-A converter ....................................... 8 bits X 3 channels

· Watchdog timer .................................... 1 line

· Programmable I/O ............................... 104 lines (32 lines are shared with LCD outputs)

· Output port ........................................... 16 lines (shared with LCD outputs)

· Input port ..............................................

_______

1 line (P7

, shared with NMI pin)

· LCD drive control circuit ....................... 1/2, 1/3 bias

2, 3 and 4 time sharing

4 common outputs

48 segment outputs

built-in Charge-pump

· Key input interrupt ................................ 20 lines

· Clock generating circuit ....................... 2 built-in clock generation circuits

(built-in feedback resistor, and external ceramic or quartz oscillator)

Applications

Camera, Home appliances, Portable equipment, Drop meter, Audio, Office equipment, etc.

------Table of Contents------

Real time Port ............................................... 85

Serial I/O ....................................................... 87

LCD Drive Control Circuit ............................ 123

A-D Converter ............................................. 130

D-A Converter ............................................. 140

Programmable I/O Port ............................... 142

Electric Characteristics ............................... 155

Flash Memory Version ................................ 171

Central Processing Unit (CPU) ....................... 9

Reset ............................................................. 12

Clock Generating Circuit ............................... 20

Protection ...................................................... 29

Interrupt ......................................................... 30

Watchdog Timer ............................................ 53

DMAC ........................................................... 55

Timer ............................................................. 65

Description

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Pin Configuration

Figure 1.1.1 shows the pin configurations (top view).

PIN CONFIGURATION (top view)

Package: 144P6Q-A, 144PFB-A

Figure 1.1.1. Pin configuration (top view)

(
N

t
e

)

/TA2

/TA1

/TA2

OUT

/
SEG

SEG

REF

Vss

SEG

CNV

COM

110

113

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

109

111
112

144

SEG

(
N

t
e

)

/TA0

/TA1

OUT

/TA0

OUT

/RxD

x
D

SEG

SEG8

/AN

/
SEG

P10

/SEG

P10

/SEG

P10

/SEG

SEG

/CLK

/TB3

/TB0

/TB1

/TB2

/TB5

/TB4

/CK

OUT

P13

/DA

P13

/DA

108

107

106

105

104

103

102

100

101

/IN

P13

/AD

TRG

/DA

/CTS

/RTS

/TA3

/INT4

/TA3

OUT

/INT4

/KI

/IN

/INT3

N o te : P 7

a n d P 7

a re N ch a n n e l o p e n -d ra in o u tp u t p in .

M30220MX-XXXGP/RP

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Description

Block Diagram

Figure 1.1.2 is a block diagram of the M30220 group.

Figure 1.1.2. Block diagram of M30220 group

Timer

Internal peripheral functions

Watchdog timer

(15 bits)

Memory

ROM

(Note 1)

RAM

(Note 2)

A-D converter

(10 bits

8 channels

UART/clock synchronous SI/O

(8 bits

3 channels)

System clock generator

-X

OUT

CIN

-X

COUT

M16C/60 series 16-bit CPU core

I/O ports

Port P4

Port P5

Port P6

Port P7

Port P8

R0L

R0H

R1H

R1
L

R
2

R
3

A
0

A
1

R0L

R0H

R1H

R1L

A1
FB

Registers

ISP

USP

Stack pointer

Multiplier

Vector table

INTB

Port P9

Flag register

FLG

Program counter

Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.

DMAC

(2 channels)

D-A converter

(8 bits X 3 channels)

LCD drive control circuit

(4COM X 48SEG)

Port P10

Port P12

Port P13

Port P3

Port P2

Port P1

Port P0

Port P11

Timer TA0 (16 bits)

Timer TA1 (16 bits)
Timer TA2 (16 bits)
Timer TA3 (16 bits)
Timer TA4 (16 bits)
Timer TA5 (16 bits)
Timer TA6 (16 bits)

Timer TA7 (16 bits)

Timer TB0 (16 bits)
Timer TB1 (16 bits)

Timer TB2 (16 bits)

Timer TB3 (16 bits)
Timer TB4 (16 bits)
Timer TB5 (16 bits)

Description

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Item

Performance

Number of basic instructions

91 instructions

Shortest instruction execution time

100ns (f(X

)=10MHz

Memory

ROM

96 Kbytes

capacity

RAM

6 Kbytes

I/O port

P0 to P13 (except P7

)

8 bits x 11, 3 bits x 1, 6 bits x 1, 7 bits x 1

Input port

1 bit x 1

Output port

SEG

to SEG

2 bits x 8

Multifunction

TA0 to TA7

16 bits x 8

timer

TB0 to TB5

16 bits x 6

Real time port outputs

8 bits x 4 lines

Serial I/O

UART0 to UART2

(UART or clock synchronous) x 3

A-D converter

10 bits x 8 channels

D-A converter

8 bits x 3 channels

DMAC

2 channel(trigger:26 sources)

LCD

COM

to COM

4 lines

SEG

to SEG

48 lines (32 lines are shared with I/O ports)

Watchdog timer

15 bits x 1 (with prescaler)

Interrupt

26 internal and 8 external sources, 4 software sources

Clock generating circuit

2 built-in clock generation circuits

(built-in feedback resistor, and external ceramic or

quartz oscillator)

Supply voltage

4.0V to 5.5V (f(X

)=10MHz)

2.7V to 5.5V (f(X

)=7MHz with software one-wait)

Power consumption

18mW (V

=3V, f(X

)=7MHz with software one-wait)

I/O withstand voltage (P0 to P13)

5 V

Output current P1 to P9,P13

5 mA

P0, P10 to P12

0.1mA("H" output), 2.5mA("L" output)

Device configuration

CMOS high-performance silicon gate

Package

144-pin plastic mold QFP

Table 1.1.1. Performance outline of M30220 group

Performance Outline

Table 1.1.1 is performance outline of M30220 group.

I/O char-
acteristics

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Description

Mitsubishi plans to release the following products in the M30220 group:

(1) Support for mask ROM version, flash memory version

(2) ROM capacity

(3) Package

144P6Q-A

: Plastic molded QFP (mask ROM and flash memory versions)

144PFB-A

: Plastic molded QFP(mask ROM and flash memory versions)

Figure 1.1.3 shows the ROM expansion and figure 1.1.4 shows the Type No., memory size, and package.

Figure 1.1.3. Memory expansion

RAM

(Byte)

96K

ROM

(Byte)

M30220MA-XXXGP/RP

128K

10K

M30220FCGP/RP

Under development

Dec. 2001

Figure 1.1.4. Type No., memory size, and package

Type No. M30 22 0 M A - XXX GP

Package type:
GP:

Package144P6Q-A

RP:

144PFB-A

ROM capacity:
8 : 64K bytes C : 128K bytes
A : 96K bytes

ROM No.
Omitted for flash memory version

Memory type:
M : Mask ROM version
F : Flash memory version

Shows RAM capacity, pin count, etc.
(The value itself has no specific meaning)

M16C/22 Group(built-in LCDC)

M16C Family

Shows characteristic, use
None: General

Pin Description

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Pin Description

, V

CNV

CIN

COUT

REF

to P0

to P1

to P3

to P4

Signal name

Power supply
input

CNV

Reset input

Clock input

Clock output

Analog power
supply input

Reference
voltage input

I/O port P0

I/O port P1

I/O port P3

I/O port P4

Supply 2.7 to 5.5 V to the V

pin. Supply 0 V to the V

pin.

Function

Connect it to the V

pin via resistor.

A "L" on this input resets the microcomputer.

This pin is a power supply input for the A-D converter. Connect
it to V

This pin is a reference voltage input for the A-D converter.

This is an 8-bit CMOS I/O port. It has an input/output port
direction register that allows the user to set each pin for input or
output individually. When set for input, the user can specify in
units of four bits via software whether or not they are tied to a
pull-up resistor. Pins in this port also use as LCD segment
output and real time port output.

This is an 8-bit I/O port equivalent to P0. Pins in this port also
function as input pins for the key input interrupt function and real
time port output.

This is a 6-bit I/O port equivalent to P0. P3

to P3

also function

as input pins for the key input interrupt function.

Pin name

I/O

Analog power
supply input

RESET

I/O port P5

I/O port P6

to P5

to P6

This is an 8-bit I/O port equivalent to P0. Pins in this port also
function as UART0 and UART1 I/O pins as selected by
software.

to P2

I/O port P2

This is an 8-bit I/O port equivalent to P0. Pins in this port also
function as input pins for the key input interrupt function and real
time port output.

I/O

This is a 8-bit I/O port equivalent to P0. Pins in this port also
function as timer B0 to B5 and INT

input pins, CK

OUT

output

pin as selected by software.

This is a 8-bit I/O port equivalent to P0. Pins in this port also
function as timer A0 to A3 I/O pins, INT

input pin as selected

by software.

These pins are provided for the sub clock generating circuit.
Connect a ceramic resonator or crystal between the X

CIN

and the

COUT

pins. To use an externally derived clock, input it to the

CIN

pin and leave the X

COUT

pin open.

OUT

Clock input

Clock output

These pins are provided for the main clock generating circuit.
Connect a ceramic resonator or crystal between the X

and the

OUT

pins. To use an externally derived clock, input it to the X

pin and leave the X

OUT

pin open.

Pin Description

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Pin Description

Signal name

Function

Pin name

I/O

I/O port P7

I/O port P8

I/O port P9

I/O port P10

to P7

to P8

to P9

P10

to P10

This is an 8-bit I/O port equivalent to P0. Pins in this port also
function as A-D converter analog input pins as selected by
software.

This is an 8-bit I/O port equivalent to P0. Pins in this port also
function as SEG output for LCD as selected by software.

This is an 3-bit I/O port equivalent to P0. Pins in this port also
function as D-A converter analog output pins or start trigger for
A-D input pins.

I/O

I/O port P11

P11

to P11

This is an 8-bit I/O port equivalent to P0. Pins in this port also
function as SEG output for LCD as selected by software.

I/O

I/O port P13

P13

to P13

Segment
output

SEG

Pins in this port function as SEG output for LCD drive circuit.

Common
output

COM

Power supply input for LCD drive circuit.

Power supply
input for LCD

to VL

Pins in this port function as common output for LCD drive circuit.

Step-up
condenser
connect port

, C

Pins in this port function as external pin for LCD step-up
condenser. Connect a condenser between C

and C

I/O

I/O port P12

P12

to P12

This is an 8-bit I/O port equivalent to P0. Pins in this port also
function as SEG output for LCD and real time port output.

This is a 8-bit I/O port equivalent to P0. Pins in this port also
function as timer A4 to A7 I/O pins, INT

input pin as selected by

software.

to P7

are I/O ports equivalent to P0 (P7

and P7

are N

channel open-drain output).
Pins in this port also function as UART2 I/O pin, INT

to INT

input pins as selected by software.
P7

is an input-only port that also functions for NMI.

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Memory

Operation of Functional Blocks

The M30220 group accommodates certain units in a single chip. These units include ROM and RAM to

store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations.

Also included are peripheral units such as timers, real time port, serial I/O, LCD drive control circuit, D-A

converter, A-D converter, DMAC and I/O ports.

The following explains each unit.

Memory

Figure 1.4.1 is a memory map of the M30220 group. The address space extends the 1M bytes from ad-

dress 00000

to FFFFF

. From FFFFF

down is ROM. For example, in the M30220MA-XXXGP, there

is 96K bytes of internal ROM from E8000

to FFFFF

. The vector table for fixed interrupts such as the

_______

reset and NMI are mapped to FFFDC

to FFFFF

. The starting address of the interrupt routine is stored

here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal

From 00400

up is RAM. For example, in the M30220MA-XXXGP, 6K bytes of internal RAM is mapped to

the space from 00400

to 01BFF

. In addition to storing data, the RAM also stores the stack used when

calling subroutines and when interrupts are generated.

The SFR area is mapped to 00000

to 003FF

. This area accommodates the control registers for periph-

eral devices such as I/O ports, A-D converter, serial I/O, timers, and LCD, etc. Figures 1.7.1 to 1.7.3 are

location of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and

cannot be used for other purposes.

The special page vector table is mapped to FFE00

to FFFDB

. If the starting addresses of subroutines

or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions

can be used as 2-byte instructions, reducing the number of program steps.

Figure 1.4.1. Memory map

SFR area

For details, see

Figures 1.7.1 to 1.7.3

Internal RAM area

Internal ROM area

Reset

Watchdog timer

Single step

Address match

BRK instruction

Overflow

Undefined instruction

Special page

vector table

00000

00400

XXXXX

YYYYY

FFFFF

FFFDC

FFE00

DBC

NMI

RAM size

Address XXXXX

4K bytes

013FF

ROM size

64K bytes

F0000

Address YYYYY

6K bytes

01BFF

10K bytes

02BFF

96K bytes

E8000

128K bytes

E0000

CPU

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Central Processing Unit (CPU)

The CPU has a total of 13 registers shown in Figure 1.5.1. Seven of these registers (R0, R1, R2, R3, A0,

A1, and FB) come in two sets; therefore, these have two register banks.

(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)

Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and

arithmetic/logic operations.

Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),

and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can

use as 32-bit data registers (R2R0/R3R1).

(2) Address registers (A0 and A1)

Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data

registers. These registers can also be used for address register indirect addressing and address register

relative addressing.

In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).

b15

(Note)

b15

(Note)

b15

(Note)

b15

(Note)

b15

(Note)

b15

(Note)

b15

Data
registers

Address
registers

Frame base
registers

b15

b19

Program counter

Interrupt table
register

User stack pointer

Interrupt stack
pointer

Static base
register

Flag register

INTB

USP

ISP

FLG

Note: These registers consist of two register banks.

IPL

Figure 1.5.1. Central processing unit register

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

CPU

(3) Frame base register (FB)

Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.

(4) Program counter (PC)

Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.

(5) Interrupt table register (INTB)

Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector

table.

(6) Stack pointer (USP/ISP)

Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-

ured with 16 bits.

Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).

This flag is located at the position of bit 7 in the flag register (FLG).

(7) Static base register (SB)

Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.

(8) Flag register (FLG)

Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.5.2 shows the flag

· Bit 0: Carry flag (C flag)

This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.

· Bit 1: Debug flag (D flag)

This flag enables a single-step interrupt.

When this flag is "1", a single-step interrupt is generated after instruction execution. This flag is

cleared to "0" when the interrupt is acknowledged.

· Bit 2: Zero flag (Z flag)

This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, cleared to "0".

· Bit 3: Sign flag (S flag)

This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, cleared to "0".

· Bit 4: Register bank select flag (B flag)

This flag chooses a register bank. Register bank 0 is selected when this flag is "0" ; register bank 1 is

selected when this flag is "1".

· Bit 5: Overflow flag (O flag)

This flag is set to "1" when an arithmetic operation resulted in overflow; otherwise, cleared to "0".

· Bit 6: Interrupt enable flag (I flag)

This flag enables a maskable interrupt.

An interrupt is disabled when this flag is "0", and is enabled when this flag is "1". This flag is cleared to

"0" when the interrupt is acknowledged.

CPU

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

· Bit 7: Stack pointer select flag (U flag)

Interrupt stack pointer (ISP) is selected when this flag is "0" ; user stack pointer (USP) is selected

when this flag is "1".

This flag is cleared to "0" when a hardware interrupt is acknowledged or an INT instruction of software

interrupt Nos. 0 to 31 is executed.

· Bits 8 to 11: Reserved area

· Bits 12 to 14: Processor interrupt priority level (IPL)

Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight

processor interrupt priority levels from level 0 to level 7.

If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt

is enabled.

· Bit 15: Reserved area

The C, Z, S, and O flags are changed when instructions are executed. See the software manual for

details.

Figure 1.5.2. Flag register (FLG)

Carry flag

Debug flag

Zero flag

Sign flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved area

Processor interrupt priority level

Reserved area

Flag register (FLG)

IPL

b15

Reset

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

____________

Table 1.6.1 shows the statuses of the other pins while the RESET pin level is "L". Figures 1.6.3 and 1.6.4

show the internal status of the microcomputer immediately after the reset is cancelled.

____________

Table 1.6.1. Pin status when RESET pin level is "L"

Status

Pin name

SEG

to SEG

P0, P10 to P12

Input port(with a pull up resistor)

Input port (floating)

"H" level is output

COM

to COM

P1 to P9, P13

Figure 1.6.2. Reset sequence

Reset

There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.

(See "Software Reset" for details of software resets.) This section explains on hardware resets.

When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the

reset pin level "L" (0.2V

max.) for at least 20 cycles. When the reset pin level is then returned to the "H"

level while main clock is stable, the reset status is cancelled and program execution resumes from the

address in the reset vector table.

Figure 1.6.1 shows the example reset circuit. Figure 1.6.2 shows the reset sequence.

Figure 1.6.1. Example reset circuit

Address

(Internal Address signal)

FFFFE

FFFFC

More than 20 cycles are needed

BCLK

BCLK 24 cycles

RESET

Content of reset vector

RESET

0.8V

RESET

4.0V

Example when f(X

)=10MH

, V

=5V.

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Reset

Figure 1.6.3. Device's internal status after a reset is cleared

The content of other registers and RAM is undefined when the microcomputer is
reset. The initial values must therefore be set.

0 1 0 0 1 0 0 0

0 0

0 0 0 ? ? ? ? ?

0 0

0 0 0

0 0 ?

0 0

0 0 0

0 0

? 0 0

0 0

? 0 0

0 0

0 0 0

0 0

0 0 0

0 0

0 0 0

0 0

0 0 0

? 0 0 0

0 0 0 0

0 0 0

? 0 0 0

0 0 0

0 0

0 0 0

0 0

0 0 0

0 0

0 0 0

0 0

0 0 0

(26)UART0 receive interrupt control register

(0052

)···

(1)Processor mode register 0

(0004

)···

(2)Processor mode register 1

(0005

)···

(3)System clock control register 0

(0006

)···

(4)System clock control register 1

(0007

)···

(5)Address match interrupt enable register

(0009

)···

(6)Protect register

(000A

)···

(7)Watchdog timer control register

(000F

)···

(8)Address match interrupt register 0

(0010

)···

(0011

)···

(0012

)···

(9)Address match interrupt register 1

(0014

)···

(0015

)···

(0016

)···

(10)DMA0 control register

(002C

)···

(11)DMA1 control register

(003C

)···

(12)INT3 interrupt control register

(0044

)···

(13)Timer B5 interrupt control register

(0045

)···

(14)Timer B4 interrupt control register

(0046

)···

(15)Timer B3 interrupt control register

(0047

)···

(16)Timer A7 interrupt control register

(0048

)···

(17)Timer A6 interrupt control register

(0049

)···

(18)Timer A5 interrupt control register

(004A

)···

(19)DMA0 interrupt control register

(004B

)···

(20)DMA1 interrupt control register

(004C

)···

(21)Key input interrupt control register

(004D

)···

(22)A-D conversion interrupt control register

(004E

)···

(23)UART2 transmit interrupt control register

(004F

)···

(24)UART2 receive interrupt control register

(0050

)···

(25)UART0 transmit interrupt control register

(0051

)···

(58)UART2 transmit/receive mode register

(0378

)···

(27)UART1 transmit interrupt control register

(0053

)···

(28)UART1 receive interrupt control register

(0054

)···

(29)Timer A0 interrupt control register

(0055

)···

(30)Timer A1 interrupt control register

(0056

)···

(31)Timer A2 interrupt control register

(0057

)···

(32)Timer A3 / INT4 interrupt control register

(0058

)···

(33)Timer A4 / INT5 interrupt control register

(0059

)···

(34)Timer B0 interrupt control register

(005A

)···

(35)Timer B1 interrupt control register

(005B

)···

(36)Timer B2 interrupt control register

(005C

)···

(37)INT0 interrupt control register

(005D

)···

(38)INT1 interrupt control register

(005E

)···

(39)INT2 interrupt control register

(005F

)···

(40)LCD mode register

(0120

)···

(41)Segment output enable register

(0122

)···

(42)Key input mode register

(0126

)···

(43)Count start flag 1

(0340

)···

(44)One-shot start flag 1

(0342

)···

(45)Trigger select flag 1

(0343

)···

(46)Up-down flag 1

(0344

)···

(47)Timer A5 mode register

(0356

)···

(48)Timer A6 mode register

(0357

)···

(49)Timer A7 mode register

(0358

)···

(50)Timer B3 mode register

(035B

)···

(51)Timer B4 mode register

(035C

)···

(52)Timer B5 mode register

(035D

)···

(53)Interrupt cause select register 0

(035E

)···

(54)Interrupt cause select register 1

(035F

)···

(57)UART2 special mode register

(0377

)···

0 1 1

0 0 0

0 0

(55)Clock division counter control register

(0360

)···

(56)UART2 special mode register 2

(0376

)···

x : Nothing is mapped to this bit
? : Undefined

Reset

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Figure 1.6.4. Device's internal status after a reset is cleared

0 0 0 ? ? ?

(85)A-D control register 0

(86)A-D control register 1

(87)D-A control register

(88)Port P0 direction register

(89)Port P1 direction register

(90)Port P2 direction register

(91)Port P3 direction register

(92)Port P4 direction register

(93)Port P5 direction register

(94)Port P6 direction register

(95)Port P7 direction register

(96)Port P8 direction register

(97)Port P9 direction register

(98)Port P10 direction register

(99)Port P11 direction register

0000

00000

0000

(113)Flag register (FLG)

(100)Port P12 direction register

(101)Port P13 direction register

(102)Pull-up control register 0

(103)Pull-up control register 1

(104)Pull-up control register 2

(105)Real time port control register

(106)Data registers (R0/R1/R2/R3)

(107)Address registers (A0/A1)

(108)Frame base register (FB)

(109)Interrupt table register (INTB)

(110)User stack pointer (USP)

(111)Interrupt stack pointer (ISP)

(112)Static base register (SB)

0 0 0 0 0

1 1 1 1 0

(03D6

)· · ·

(03D7

)· · ·

(03DC

)· · ·

(03E2

)· · ·

(03E3

)· · ·

(03E6

)· · ·

(03E7

)· · ·

(03EA

)· · ·

(03EB

)· · ·

(03EE

)· · ·

(03EF

)· · ·

(03F2

)· · ·

(03F3

)· · ·

(03F6

)· · ·

(03F7

)· · ·

(03FA

)· · ·

(03FB

)· · ·

(03FC

)· · ·

(03FD

)· · ·

(03FE

)· · ·

(03FF

)· · ·

· · ·

(59)

UART2 transmit/receive control register 0

(60)

UART2 transmit/receive control register 1

(61)Count start flag 0

(62) Clock prescaler reset flag

(63)One-shot start flag 0

(64)Trigger select flag 0

(65)Up-down flag 0

(66)Timer A0 mode register

(67)Timer A1 mode register

(68)Timer A2 mode register

(84) A-D control register 2

(69)Timer A3 mode register

(70)Timer A4 mode register

(71)Timer B0 mode register

(72)Timer B1 mode register

(73)Timer B2 mode register

(74)

UART0 transmit/receive mode register

(75)

UART0 transmit/receive control register 0

(76)

UART0 transmit/receive control register 1

(77)

UART1 transmit/receive mode register

(78)

UART1 transmit/receive control register 0

(79)

UART1 transmit/receive control register 1

(80)

UART transmit/receive control register 2

(82)DMA0 cause select register

(83)DMA1 cause select register

(81)Flash memory control register

(Note)

(037C

)· · ·

(037D

)· · ·

(0380

)· · ·

(0381

)· · ·

(0382

)· · ·

(0383

)· · ·

(0384

)· · ·

(0396

)· · ·

(0397

)· · ·

(0398

)· · ·

(0399

)· · ·

(039A

)· · ·

(039B

)· · ·

(039C

)· · ·

(039D

)· · ·

(03A0

)· · ·

(03A4

)· · ·

(03A5

)· · ·

(03A8

)· · ·

(03AC

)· · ·

(03AD

)· · ·

(03B0

)· · ·

(03B4

)· · ·

(03B8

)· · ·

(03BA

)· · ·

(03D4

)· · ·

0 0 0 0 1

0 0 0 0 0

x : Nothing is mapped to this bit
? : Undefined

0 0

0 0 0 0 0

0 0 0 0

0 0

0 1 0 0 0

0 0

0 0 0 1 0

0 0

0 1 0 0 0

0 0

0 0 0 1 0

0 0 0 0 0

0 0 0 0

0 0 0

The content of other registers and RAM is undefined when the microcomputer is reset. The initial values
must therefore be set.

Note : This register is only exist in flash memory version.

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

SFR

Figure 1.7.1. Location of peripheral unit control registers (1)

0000

0001

0002

0003

0004

0005

0006

0007

0008

0009

000A

000B

000C

000D

000E

000F

0010

0011

0012

0013

0014

0015

0016

0017

0018

0019

001A

001B

001C

001D

001E

001F

0020

0021

0022

0023

0024

0025

0026

0027

0028

0029

002A

002B

002C

002D

002E

002F

0030

0031

0032

0033

0034

0035

0036

0037

0038

0039

003A

003B

003C

003D

003E

003F

0040

0041

0042

0043

0044

0045

0046

0047

0048

0049

004A

004B

004C

004D

004E

004F

0050

0051

0052

0053

0054

0055

0056

0057

0058

0059

005A

005B

005C

005D

005E

005F

0100

0101

0102

0103

0104

0105

0106

0107

0108

0109

010A

010B

010C

010D

010E

010F

0110

0111

0112

0113

0114

0115

0116

0117

0120

0121

0122

0123

0124

0125

0126

INT1 interrupt control register (INT1IC)

Timer B0 interrupt control register (TB0IC)

Timer B2 interrupt control register (TB2IC)

Timer A1 interrupt control register (TA1IC)

Timer A3 interrupt control register (TA3IC)

UART0 transmit interrupt control register (S0TIC)

INT2 interrupt control register (INT2IC)

INT0 interrupt control register (INT0IC)

Timer B1 interrupt control register (TB1IC)

Timer A0 interrupt control register (TA0IC)

Timer A2 interrupt control register (TA2IC)

Timer A4 interrupt control register (TA4IC)

UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control register (S1TIC)
UART1 receive interrupt control register (S1RIC)

Key input interrupt control register (KUPIC)

A-D conversion interrupt control register (ADIC)

Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)

Processor mode register 0 (PM0)

Address match interrupt register 0 (RMAD0)

Address match interrupt register 1 (RMAD1)

System clock control register 0 (CM0)
System clock control register 1 (CM1)

Address match interrupt enable register (AIER)

Protect register (PRCR)

Processor mode register 1(PM1)

INT3 interrupt control register (INT3IC)

INT4 interrupt control register (INT4IC)

INT5 interrupt control register (INT5IC)

Timer B5 interrupt control register (TB5IC)
Timer B4 interrupt control register (TB4IC)
Timer B3 interrupt control register (TB3IC)

UART2 transmit interrupt control register (S2TIC)

UART2 receive interrupt control register (S2RIC)

Timer A7 interrupt control register (TA7IC)
Timer A6 interrupt control register (TA6IC)

Timer A5 interrupt control register (TA5IC)

DMA0 source pointer (SAR0)

DMA0 destination pointer (DAR0)

DMA0 transfer counter (TCR0)

DMA0 control register (DM0CON)

DMA1 source pointer (SAR1)

DMA1 destination pointer (DAR1)

DMA1 transfer counter (TCR1)

DMA1 control register (DM1CON)

LCD RAM0(LRAM0)

LCD RAM1(LRAM1)
LCD RAM2(LRAM2)
LCD RAM3(LRAM3)
LCD RAM4(LRAM4)
LCD RAM5(LRAM5)
LCD RAM6(LRAM6)
LCD RAM7(LRAM7)
LCD RAM8(LRAM8)
LCD RAM9(LRAM9)
LCD RAM10(LRAM10)
LCD RAM11(LRAM11)
LCD RAM12(LRAM12)
LCD RAM13(LRAM13)

LCD RAM14(LRAM14)
LCD RAM15(LRAM15)
LCD RAM16(LRAM16)

LCD RAM17(LRAM17)

LCD RAM18(LRAM18)
LCD RAM19(LRAM19)
LCD RAM20(LRAM20)

LCD RAM21(LRAM21)

LCD RAM22(LRAM22)

LCD RAM23(LRAM23)

DMA0 interrupt control register (DM0IC)
DMA1 interrupt control register (DM1IC)

LCD mode register (LCDM)

Segment output enable register (SEG)

Key input mode register (KUPM)

LCD frame frequency counter (LCDTIM)

Bus collision detection interrupt control register

(BCNIC)

Note : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.

SFR

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Figure 1.7.2. Location of peripheral unit control registers (2)

0340

0341

0342

0343

0344

0345

0346

0347

0348

0349

034A

034B

034C

034D

034E

034F

0350

0351

0352

0353

0354

0355

0356

0357

0358

0359

035A

035B

035C

035D

035E

035F

0360

0361

0362

0363

0364

0365

0366

0367

0368

0369

036A

036B

036C

036D

036E

036F

0370

0371

0372

0373

0374

0375

0376

0377

0378

0379

037A

037B

037C

037D

037E

037F

0380

0381

0382

0383

0384

0385

0386

0387

0388

0389

038A

038B

038C

038D

038E

038F

0390

0391

0392

0393

0394

0395

0396

0397

0398

0399

039A

039B

039C

039D

039E

039F

03A0

03A1

03A2

03A3

03A4

03A5

03A6

03A7

03A8

03A9

03AA

03AB

03AC

03AD

03AE

03AF

03B0

03B1

03B2

03B3

03B4

03B5

03B6

03B7

03B8

03B9

03BA

03BB

03BC

03BD

03BE

03BF

UART0 transmit/receive mode register (U0MR)

UART0 transmit buffer register (U0TB)

UART0 receive buffer register (U0RB)

UART1 transmit/receive mode register (U1MR)

UART1 transmit buffer register (U1TB)

UART1 receive buffer register (U1RB)

Timer A0 register (TA0)

Timer A1 register (TA1)

Timer A2 register (TA2)

Timer B0 register (TB0)

Timer B1 register (TB1)

Timer B2 register (TB2)

Count start flag 0 (TABSR0)

One-shot start flag 0 (ONSF0)

Timer A0 mode register (TA0MR)
Timer A1 mode register (TA1MR)
Timer A2 mode register (TA2MR)

Timer B0 mode register (TB0MR)
Timer B1 mode register (TB1MR)
Timer B2 mode register (TB2MR)

Up-down flag 0 (UDF0)

Timer A3 register (TA3)

Timer A4 register (TA4)

Timer A3 mode register (TA3MR)
Timer A4 mode register (TA4MR)

Trigger select register 0 (TRGSR0)

UART0 bit rate generator (U0BRG)

UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)

UART1 bit rate generator (U1BRG)

UART1 transmit/receive control register 0 (U1C0)
UART1 transmit/receive control register 1 (U1C1)

UART transmit/receive control register 2 (UCON)

Clock prescaler reset flag (CPSRF)

Count start flag 1 (TABSR1)

Timer B3 register (TB3)

Timer B4 register (TB4)

Timer B5 register (TB5)

Timer B3 mode register (TB3MR)
Timer B4 mode register (TB4MR)
Timer B5 mode register(TB5MR)

Timer A5 register (TA5)

Timer A6 register (TA6)

Timer A7 register (TA7)

One-shot start flag 1 (ONSF1)
Trigger select register 1 (TRGSR1)
Up-down flag 1(UDF1)

Timer A5 mode register (TA5MR)
Timer A6 mode register (TA6MR)
Timer A7 mode register (TA7MR)

UART2 special mode register (U2SMR)

UART2 transmit/receive mode register (U2MR)
UART2 bit rate generator (U2BRG)

UART2 transmit buffer register (U2TB)

UART2 transmit/receive control register 0 (U2C0)
UART2 transmit/receive control register 1 (U2C1)

UART2 receive buffer register (U2RB)

Interrupt cause select register 1 (IFSR1)

DMA0 request cause select register (DM0SL)

DMA1 request cause select register (DM1SL)

Clock division counter (CDC)

Interrupt cause select register 0 (IFSR0)

Clock division counter control register (CDCC)

UART2 special mode register 2(U2SMR2)

Flash memory control register (FMCR)(Note 1)

Note 1: This register is only exist in flash memory version.
Note 2: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

SFR

Figure 1.7.3. Location of peripheral unit control registers (3)

03C0

03C1

03C2

03C3

03C4

03C5

03C6

03C7

03C8

03C9

03CA

03CB

03CC

03CD

03CE

03CF

03D0

03D1

03D2

03D3

03D4

03D5

03D6

03D7

03D8

03D9

03DA

03DB

03DC

03DD

03DE

03DF

03E0

03E1

03E2

03E3

03E4

03E5

03E6

03E7

03E8

03E9

03EA

03EB

03EC

03ED

03EE

03EF

03F0

03F1

03F2

03F3

03F4

03F5

03F6

03F7

03F8

03F9

03FA

03FB

03FC

03FD

03FE

03FF

Port P0 register (P0)

Port P0 direction register (PD0)

Port P1 register (P1)

Port P1 direction register (PD1)
Port P2 register (P2)

Port P2 direction register (PD2)

Port P3 register (P3)

Port P3 direction register (PD3)
Port P4 register (P4)

Port P4 direction register (PD4)

Port P5 register (P5)

Port P5 direction register (PD5)
Port P6 register (P6)

Port P6 direction register (PD6)

Port P7 register (P7)

Port P7 direction register (PD7)
Port P8 register (P8)

Port P8 direction register (PD8)

Port P9 register (P9)

Port P9 direction register (PD9)
Port P10 register (P10)

Port P10 direction register (PD10)

Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
Pull-up control register 2 (PUR2)

A-D register 7 (AD7)

A-D register 0 (AD0)

A-D register 1 (AD1)

A-D register 2 (AD2)

A-D register 3 (AD3)

A-D register 4 (AD4)

A-D register 5 (AD5)

A-D register 6 (AD6)

A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)

D-A register 0 (DA0)

D-A register 1 (DA1)

D-A control register (DACON)

A-D control register 2 (ADCON2)

D-A register 2 (DA2)

Port P11 register (P11)

Port P11 direction register (PD11)
Port P12 register (P12)

Port P12 direction register (PD12)

Real time port control register (RTP)

Port P13 register (P13)

Port P13 direction register (PD13)

Note : Locations in the SFR area where nothing is allocated are reserved areas.
Do not access these areas for read or write.

Software Reset

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Figure 1.8.1. Processor mode register 0 and 1

Software Reset

Writing "1" to bit 3 of the processor mode register 0 (address 0004

) applies a (software) reset to the

microcomputer. A software reset has the same effect as a hardware reset. The contents of internal RAM

are preserved.

Figure 1.8.1 shows the processor mode register 0 and 1.

Processor mode register 0 (Note)

Symbol

Address

When reset

PM0

0004

XXXX0000

Bit name

Function

Bit symbol

b7 b6

b1 b0

PM03

Reserved bit

Software reset bit

The device is reset when this bit
is set to "1". The value of this bit
is "0" when read.

Note: Set bit 1 of the protect register (address 000A

) to "1" when writing new

values to this register.

Must always be set to "0"

Nothing is assigned.

In an attempt to write to these bits, write "0". The value, if read, turns
out to be

indeterminate.

Processor mode register 1 (Note)

Symbol

Address

When reset

PM1

0005

0XXXXX00

Bit name

Function

Bit symbol

b6 b5

Nothing is assigned.

In an attempt to write to these bits, write "0". The value, if read, turns
out to be

indeterminate.

Reserved bit

Must always be set to "0"

Note: Set bit 1 of the protect register (address 000A

) to "1" when writing new values

to this register.

PM17

Wait bit

0 : No wait state
1 : Wait state inserted

0 0: Single-chip mode
0 1: Must not be set
1 0: Must not be set
1 1: Must not be set

b1 b0

PM01

PM00

Processor mode bit

Software Wait

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Software wait

A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address

0005

). (Note)

A software wait is inserted in the internal ROM/RAM area. When set to "0", each bus cycle is executed in

one BCLK cycle. When set to "1", each bus cycle is executed in two BCLK cycles. After the microcomputer

has been reset, this bit defaults to "0". Set this bit after referring to the recommended operating conditions

(main clock input oscillation frequency) of the electric characteristics.

The SFR area is always accessed in two BCLK cycles regardless of the setting of this control bit.

Table 1.8.1 shows the software waits and bus cycles.

Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect

) to "1".

Table 1.8.1. Software waits and bus cycles

Area

Wait bit

Bus cycle

2 BCLK cycles

SFR

Internal

ROM/RAM

1 BCLK cycle

Invalid

2 BCLK cycles

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Clock Generating Circuit

Figure 1.9.2. Examples of sub-clock

Table 1.9.1. Main clock and sub-clock generating circuits

Clock Generating Circuit

The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the

CPU and internal peripheral units.

Example of oscillator circuit

Figure 1.9.1 shows some examples of the main clock circuit, one using an oscillator connected to the

circuit, and the other one using an externally derived clock for input. Figure 1.9.2 shows some examples of

sub-clock circuits, one using an oscillator connected to the circuit, and the other one using an externally

derived clock for input. Circuit constants in Figures 1.9.1 and 1.9.2 vary with each oscillator used. Use the

values recommended by the manufacturer of your oscillator.

Figure 1.9.1. Examples of main clock

Main clock generating circuit

Sub-clock generating circuit

Use of clock

· CPU's operating clock source

· Internal peripheral units'

· Timer A/B's count clock

operating clock source

source

· Intermittent pullup operation

clock source of key input

· LCD operation clock source

Usable oscillator

Ceramic or crystal oscillator

Crystal oscillator

Pins to connect oscillator

, X

OUT

CIN

, X

COUT

Oscillation stop/restart function

Available

Oscillator status immediately after reset

Oscillating

Stopped

Other

Externally derived clock can be input

M30220

(Built-in feedback resistor)

OUT

Externally derived clock

Open

Vcc

Vss

M30220

(Built-in feedback resistor)

OUT

(Note)

Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive

capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between X

and X

OUT

following the instruction.

M30220

(Built-in feedback resistor)

CIN

COUT

Externally derived clock

Open

Vcc

Vss

Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive

CIN

and X

COUT

following the instruction.

M30220

(Built-in feedback resistor)

CIN

COUT

(Note)

CIN

COUT

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Clock Generating Circuit

The following paragraphs describes the clocks generated by the clock generating circuit.

(1) Main clock

The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to

the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 0006

). Stopping the

clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation.

After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock

oscillation circuit can be reduced using the X

-X

OUT

drive capacity select bit (bit 5 at address 0007

Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit

changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When

shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is re-

tained.

(2) Sub-clock

The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset.

After oscillation is started using the port Xc select bit (bit 4 at address 0006

), the sub-clock can be

selected as the BCLK by using the system clock select bit (bit 7 at address 0006

). However, be sure

that the sub-clock oscillation has fully stabilized before switching.

After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock

oscillation circuit can be reduced using the X

CIN

-X

COUT

drive capacity select bit (bit 3 at address 0006

Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit

changes to "1" when shifting to stop mode and at a reset.

(3) BCLK

The BCLK is the clock that drives the CPU, and is fc or the clock is derived by dividing the main clock by

1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset.

The main clock division select bit 0(bit 6 at address 0006

) changes to "1" when shifting from high-

speed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation

mode to stop mode, the value before stop mode is retained.

(4) Peripheral function clock (f

, f

)

The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The

peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function

clock stop bit (bit 2 at 0006

) to "1" and then executing a WAIT instruction.

(5) f

C132

This clock is derived by dividing the sub-clock by 1 or 32. The clock is selected by f

C132

clock select bit

(bit4 at address 0007

). It is used for the timer A and timer B counts, intermittent pull up operation of key

input.

(6) f

This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer.

Figure 1.9.4 shows the system clock control registers 0 and 1.

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Clock Generating Circuit

Figure 1.9.4. System clock control registers 0 and 1

System clock control register 0 (Note 1)

Symbol

Address

When reset

CM0

0006

Bit name

Function

Bit symbol

0 0 : I/O port P5

0 1 : f

output

1 0 : f

output

1 1 : Clock divide counter output

b1 b0

CM07

CM05

CM04

CM03

CM01

CM02

CM00

CM06

Clock output function
select bit

WAIT peripheral function
clock stop bit

0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8)

CIN

-X

COUT

drive capacity

select bit (Note 2)

0 : LOW
1 : HIGH

Sub clock (X

CIN

-X

COUT

)

oscillation enable bit

0 : Off
1 : On

Main clock (X

-X

OUT

)

stop bit (Note 3, 4, 5)

0 : On
1 : Off

Main clock division select
bit 0 (Note 7)

0 : CM16 and CM17 valid
1 : Division by 8 mode

System clock select bit
(Note 6)

0 : X

, X

OUT

1 : X

CIN

, X

COUT

Note 1: Set bit 0 of the protect register (address 000A

) to "1" before writing to this register.

Note 2: Changes to "1" when shifting to stop mode and at a reset.
Note 3: When entering power saving mode, main clock stops using this bit. When returning from stop mode and

operating with X

, set this bit to "0". When main clock oscillation is operating by itself, set system clock select

bit (CM07) to "1" before setting this bit to "1".

Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 5: If this bit is set to "1", X

OUT

turns "H". The built-in feedback resistor remains being connected, so X

turns

pulled up to X

OUT

("H") via the feedback resistor.

Note 6: Sub clock (X

CIN

-X

COUT

) oscillation enable bit (CM04) to "1" and stabilize the sub-clock oscillating before setting

to this bit from "0" to "1". Do not write to both bits at the same time. And also, set the main clock stop bit (CM05)
to "0" and stabilize the main clock oscillating before setting this bit from "1" to "0".

Note 7: This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When

shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.

Note 8: f

C132

, f

C32

is not included. Do not set to "1" when using low-speed or low power dissipation mode.

System clock control register 1 (Note 1)

Symbol

Address

When reset

CM1

0007

Bit name

Function

Bit symbol

CM10

All clock stop control bit
(Note 4)

0 : Clock on
1 : All clocks off (stop mode)

Note 1: Set bit 0 of the protect register (address 000A

) to

"1" before writing to this register.

Note 2: This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When

shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.

Note 3: Can be selected when bit 6 of the system clock control register 0 (address 0006

) is

"0". If

"1", division mode is

fixed at 8.

Note 4: If this bit is set to "1", X

OUT

turns "H", and the built-in feedback resistor is cut off. X

CIN

and X

COUT

turn high-

impedance state.

CM15

-X

OUT

drive capacity

select bit (Note 2)

0 : LOW
1 : HIGH

CM16

CM17

Reserved bit

Must always be set to

"0"

Main clock division
select bit 1 (Note 3)

0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode

b7 b6

Reserved bit

Must always be set to

"0"

Reserved bit

Must always be set to

"0"

CM14

C132

clock select bit

0 : f

C32

1 : f

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M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Clock Output

Clock Output

The clock output function select bit allows you to choose the clock from f

, f

, or a divide-by-n clock that is

output from the P5

/CK

OUT

pin. The clock divide counter is an 8-bit counter whose count source is f

, and

its divide ratio can be set in the range of 00

to FF

. Also, the clock divided counter can be controlled for

start or stop by the clock divide counter start flag. Figure 1.9.5 shows a block diagram of clock output.

Figure 1.9.6 shows a clock divided counter related register.

Figure 1.9.5. Block diagram of clock output

Figure 1.9.6. Clock divided counter related register

Clock source
selection

Reload register (8)

Low-order 8 bits

Data bus low-order bits

1/2

Division n+1 n=00

to FF

Clock divided counter (8)

Example:
When f(X

)=10MHz, count source = f

n=07

16 :

approx. 19.5kHz

n=26

16 :

approx. 4.0kHz

n=4D

16 :

approx. 2.0kHz

n=9B

16 :

approx. 1.0kHz

/CK

OUT

Address 036E

Clock divided counter

Symbol

Address

When reset

CDC

036E

Function

Values that can be set

8-bit timer

to FF

Clock divided counter control register

Symbol

Address

When reset

CDCC

0360

0XXXXXXX

Function

Bit symbol

CDCS

Bit name

Clock divided counter
start flg

0 : Stop
1 : Start

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.

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Stop Mode, Wait Mode

Table 1.9.3. Port status during wait mode

Status

Port

Retains status before wait mode

OUT

When f

selected

Does not stop

When f

, clock devided counter output selected

Retains status before stop mode

Does not stop when the WAIT peripheral

function clock stop bit is "0".

When the WAIT peripheral function clock

stop bit is "1", the status immediately prior

to entering wait mode is main-tained.

Wait Mode

When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this

mode, oscillation continues but the BCLK and watchdog timer stop. Writing "1" to the WAIT peripheral

function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal

peripheral functions, allowing power dissipation to be reduced. However, peripheral function clock f

C132

, and f

C32

do not stop so that the peripherals using f

C132

, f

, and f

C32

do not contribute to the power

saving. When the MCU running in low-speed or low power dissipation mode, do not enter WAIT mode with

this bit set to "1". Table 1.9.3 shows the status of the ports in wait mode.

Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel wait mode,

that interrupt must first have been enabled. If an interrupt is used to cancel wait mode, the microcomputer

restarts from the interrupt routine using as BCLK, the clock that had been selected when the WAIT instruc-

tion was executed.

Status

Port

Retains status before stop mode

OUT

When f

selected

"H"

When f

, clock devided counter output selected

Retains status before stop mode

Table 1.9.2. Port status during stop mode

Stop Mode

Writing "1" to the all-clock stop control bit (bit 0 at address 0007

) stops all oscillation and the microcom-

puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that V

re-

mains above 2V.

Because the oscillation , BCLK, f

to f

, f

C132

, f

C32

and f

stops in stop mode, peripheral functions

such as the A-D converter and watchdog timer do not function. However, timer A and timer B operate

provided that the event counter mode is set to an external pulse, and UART0 to UART2 functions provided

an external clock is selected. Table 1.9.2 shows the status of the ports in stop mode.

Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode,

that interrupt must first have been enabled. If returning by an interrupt, that interrupt routine is executed.

When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division

select bit 0 (bit 6 at address 0006

) is set to "1". When shifting from low-speed/low power dissipation mode

to stop mode, the value before stop mode is retained.

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Status Transition of BCLK

Invalid

Division by 2 mode

Invalid

Division by 4 mode

Invalid

Division by 8 mode

Invalid

Division by 16 mode

Invalid

No-division mode

Invalid

Low-speed mode

Invalid

Low power dissipation mode

Status Transition Of BCLK

Power dissipation can be reduced and low-voltage operation achieved by changing the count source for

BCLK. Table 1.9.4 shows the operating modes corresponding to the settings of system clock control

registers 0 and 1.

When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address

0006

) changes to "1" when shifting from high-speed/medium-speed to stop mode and at a reset. When

shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.

The following shows the operational modes of BCLK.

(1) Division by 2 mode

The main clock is divided by 2 to obtain the BCLK.

(2) Division by 4 mode

The main clock is divided by 4 to obtain the BCLK.

(3) Division by 8 mode

The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this

mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4

mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption

mode, make sure the sub-clock is oscillating stably.

(4) Division by 16 mode

The main clock is divided by 16 to obtain the BCLK.

(5) No-division mode

The main clock is divided by 1 to obtain the BCLK.

(6) Low-speed mode

is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before

transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub-

clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately

after powering up and after stop mode is cancelled.

(7) Low power dissipation mode

is the BCLK and the main clock is stopped.

Note : Before the count source for BCLK can be changed from X

to X

CIN

or vice versa, the clock to which

the count source is going to be switched must be oscillating stably. Allow a wait time in software for

the oscillation to stabilize before switching over the clock.

CM17

CM16

CM07

CM06

CM05

CM04

Operating mode of BCLK

Table 1.9.4. Operating modes dictated by settings of system clock control registers 0 and 1

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Power control

Power control

The following is a description of the three available power control modes:

Modes

Power control is available in three modes.

(a) Normal operation mode

· High-speed mode

Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the internal

clock selected. Each peripheral function operates according to its assigned clock.

· Medium-speed mode

Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the

BCLK. The CPU operates according to the internal clock selected. Each peripheral function oper-

ates according to its assigned clock.

· Low-speed mode

becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the

secondary clock. Each peripheral function operates according to its assigned clock.

· Low power consumption mode

The main clock operating in low-speed mode is stopped. The CPU operates according to the f

clock. The fc clock is supplied by the secondary clock. The only peripheral functions that operate

are those with the sub-clock selected as the count source.

(b) Wait mode

The CPU operation is stopped. The oscillators do not stop.

(c) Stop mode

All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three

modes listed here, is the most effective in decreasing power consumption.

Figure 1.9.7 is the state transition diagram of the above modes.

Mitsubishi microcomputers

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Power control

Figure 1.9.7. State transition diagram of Power control mode

Transition of stop mode, wait mode

Transition of normal mode

Reset

Medium-speed mode

(divided-by-8 mode)

Interrupt

CM10 = "1"

All oscillators stopped

CPU operation stopped

Medium-speed mode

(divided-by-8 mode)

BCLK : f(X

)/8

CM07 = "0" CM06 = "1"

Low-speed mode

High-speed mode

Main clock is oscillating

Sub clock is stopped

Main clock is oscillating

Sub clock is stopped

Main clock is stopped

Sub clock is oscillating

Main clock is oscillating

Sub clock is oscillating

Low power dissipation mode

High-speed/medium-

speed mode

Low-speed/low power

dissipation mode

Normal mode

Stop mode

All oscillators stopped

Wait mode

CPU operation stopped

Interrupt

WAIT
instruction

Interrupt

WAIT
instruction

Interrupt

WAIT
instruction

CM10 = "1"

Interrupt

CM10 = "1"

BCLK : f(X

)/2

CM07 = "0" CM06 = "0"
CM17 = "0" CM16 = "1"

Medium-speed mode

(divided-by-2 mode)

BCLK : f(X

)/16

CM07 = "0" CM06 = "0"
CM17 = "1" CM16 = "1"

Medium-speed mode
(divided-by-16 mode)

BCLK : f(X

)/4

CM07 = "0" CM06 = "0"
CM17 = "1" CM16 = "0"

Medium-speed mode

(divided-by-4 mode)

BCLK : f(X

)

CM07 = "0" CM06 = "0"
CM17 = "0" CM16 = "0"

BCLK : f(X

)/8

Medium-speed mode

(divided-by-8 mode)

CM07 = "0"
CM06 = "1"

High-speed mode

BCLK : f(X

)/2

CM07 = "0" CM06 = "0"
CM17 = "0" CM16 = "1"

Medium-speed mode

(divided-by-2 mode)

BCLK : f(X

)/16

CM07 = "0" CM06 = "0"
CM17 = "1" CM16 = "1"

Medium-speed mode
(divided-by-16 mode)

BCLK : f(X

)/4

CM07 = "0" CM06 = "0"
CM17 = "1" CM16 = "0"

Medium-speed mode

(divided-by-4 mode)

BCLK : f(X

)

CM07 = "0" CM06 = "0"
CM17 = "0" CM16 = "0"

BCLK : f(X

CIN

)

CM07 = "1"

BCLK : f(X

CIN

)

CM07 = "1"

Main clock is oscillating

Sub clock is oscillating

CM07 = "0"
(Note 1, 3)

CM07 = "0" (Note 1)
CM06 = "1"
CM04 = "0"

CM07 = "1"
(Note 2)

CM07 = "0" (Note 1)
CM06 = "0" (Note 3)
CM04 = "1"

CM07 = "1" (Note 2)
CM05 = "1"

CM05 = "0"

CM05 = "1"

CM04 = "0"

CM04 = "1"

CM06 = "0"
(Notes 1,3)

CM06 = "1"

CM04 = "0"

CM04 = "1"
(Notes 1, 3)

Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 3: Change CM06 after changing CM17 and CM16.
Note 4: Transit in accordance with arrow.

(Refer to the following for the transition of normal mode.)

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Protection

Figure 1.9.8. Protect register

Protect register

Symbol

Address

When reset

PRCR

000A

XXXXXX00

Bit name

Bit symbol

0 : Write-inhibited
1 : Write-enabled

PRC1

PRC0

Enables writing to processor mode
registers 0 and 1 (addresses 0004

and 0005

)

Function

0 : Write-inhibited
1 : Write-enabled

Enables writing to system clock
control registers 0 and 1 (addresses
0006

and 0007

)

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.

Protection

The protection function is provided so that the values in important registers cannot be changed in the event

that the program runs out of control. Figure 1.9.8 shows the protect register. The values in the processor

mode register 0 (address 0004

), processor mode register 1 (address 0005

), system clock control reg-

ister 0 (address 0006

), system clock control register 1 (address 0007

) can only be changed when the

respective bit in the protect register is set to "1".

The system clock control registers 0 and 1 write-enable bit (bit 0 at 000A

) and processor mode register 0

and 1 write-enable bit (bit 1 at 000A

) do not automatically return to "0" after a value has been written to an

address. The program must therefore be written to return these bits to "0".

Interrupt

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

· Maskable interrupt :

An interrupt which can be enabled (disabled) by the interrupt enable flag

(I flag) or whose interrupt priority can be changed by priority level.

· Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag

(I flag) or whose interrupt priority cannot be changed by priority level.

Figure 1.10.1. Classification of interrupts

Interrupt

Software

Hardware

Special

Peripheral I/O (Note)

Undefined instruction (UND instruction)

Overflow (INTO instruction)

BRK instruction

INT instruction

Reset

_______

NMI

________

DBC

Watchdog timer

Single step

Address matched

Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.

Overview of Interrupt

Type of Interrupts

Figure 1.10.1 lists the types of interrupts.

Interrupt

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Software Interrupts

A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable

interrupts.

· Undefined instruction interrupt

An undefined instruction interrupt occurs when executing the UND instruction.

· Overflow interrupt

An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to

"1". The following are instructions whose O flag changes by arithmetic:

ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB

· BRK interrupt

A BRK interrupt occurs when executing the BRK instruction.

· INT interrupt

An INT interrupt occurs when specifying one of software interrupt numbers 0 through 63 and execut-

ing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O inter-

rupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/

O interrupt does.

The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is

involved.

So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack

pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to "0" and

select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from

the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt re-

quest. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a

shift.

Interrupt

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Hardware Interrupts

Hardware interrupts are classified into two types -- special interrupts and peripheral I/O interrupts.

(1) Special interrupts

Special interrupts are non-maskable interrupts.

· Reset

____________

Reset occurs if an "L" is input to the RESET pin.

_______

· NMI interrupt

_______

An NMI interrupt occurs if an "L" is input to the NMI pin.

________

· DBC interrupt

This interrupt is exclusively for the debugger, do not use it in other circumstances.

· Watchdog timer interrupt

Generated by the watchdog timer.

· Single-step interrupt

This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug

flag (D flag) set to "1", a single-step interrupt occurs after one instruction is executed.

· Address match interrupt

An address match interrupt occurs immediately before the instruction held in the address indicated by

the address match interrupt register is executed with the address match interrupt enable bit set to "1".

If an address other than the first address of the instruction in the address match interrupt register is set,

no address match interrupt occurs.

(2) Peripheral I/O interrupts

A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func-

tions are dependent on classes of products, so the interrupt factors too are dependent on classes of

products. The interrupt vector table is the same as the one for software interrupt numbers 0 through

31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.

· Bus collision detection interrupt

This is an interrupt that the serial I/O bus collision detection generates.

· DMA0 interrupt, DMA1 interrupt

These are interrupts that DMA generates.

· Key-input interrupt

___

A key-input interrupt occurs if either a falling edge or a both edge is input to the KI pin.

· A-D conversion interrupt

This is an interrupt that the A-D converter generates.

· UART0, UART1, UART2 transmission interrupt

These are interrupts that the serial I/O transmission generates.

· UART0, UART1, UART2 reception interrupt

These are interrupts that the serial I/O reception generates.

· Timer A0 interrupt through timer A7 interrupt

These are interrupts that timer A generates

· Timer B0 interrupt through timer B5 interrupt

These are interrupts that timer B generates.

________

· INT0 interrupt through INT5 interrupt

______

An INT interrupt occurs if either a rising edge or a falling edge or a both edge is input to the INT pin.

Interrupt

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Interrupt source

Vector table addresses

Remarks

Address (L) to address (H)

Undefined instruction

FFFDC

to FFFDF

Interrupt on UND instruction

Overflow

FFFE0

to FFFE3

Interrupt on INTO instruction

BRK instruction

FFFE4

to FFFE7

If the vector contains FF

, program execution starts from

the address shown by the vector in the variable vector table

Address match

FFFE8

to FFFEB

There is an address-matching interrupt enable bit

Single step (Note)

FFFEC

to FFFEF

Do not use

Watchdog timer

FFFF0

to FFFF3

________

DBC (Note)

FFFF4

to FFFF7

Do not use

_______

NMI

FFFF8

to FFFFB

_______

External interrupt by input to NMI pin

Reset

FFFFC

to FFFFF

Note: Interrupts used for debugging purposes only.

Figure 1.10.2. Format for specifying interrupt vector addresses

Mid address

Low address

0 0 0 0

High address

0 0 0 0

Vector address + 0

Vector address + 1

Vector address + 2

Vector address + 3

LSB

MSB

Interrupts and Interrupt Vector Tables

If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector

table. Set the first address of the interrupt routine in each vector table. Figure 1.10.2 shows the format for

specifying the address.

Two types of interrupt vector tables are available -- fixed vector table in which addresses are fixed and

variable vector table in which addresses can be varied by the setting.

· Fixed vector tables

The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area

extending from FFFDC

to FFFFF

. One vector table comprises four bytes. Set the first address of

interrupt routine in each vector table. Table 1.10.1 shows the interrupts assigned to the fixed vector

tables and addresses of vector tables.

Table 1.10.1. Interrupts assigned to the fixed vector tables and addresses of vector tables

Interrupt

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Table 1.10.2. Interrupts assigned to the variable vector tables and addresses of vector tables

Software interrupt number

Interrupt source

Vector table address

Address (L) to address (H)

Remarks

Cannot be masked I flag

+0 to +3 (Note 1)

BRK instruction

Software interrupt number 0

+44 to +47 (Note 1)

Software interrupt number 11

+48 to +51 (Note 1)

Software interrupt number 12

+52 to +55 (Note 1)

Software interrupt number 13

+56 to +59 (Note 1)

Software interrupt number 14

+68 to +71 (Note 1)

Software interrupt number 17

+72 to +75 (Note 1)

Software interrupt number 18

+76 to +79 (Note 1)

Software interrupt number 19

+80 to +83 (Note 1)

Software interrupt number 20

+84 to +87 (Note 1)

Software interrupt number 21

+88 to +91 (Note 1)

Software interrupt number 22

+92 to +95 (Note 1)

Software interrupt number 23

+96 to +99 (Note 1)

Software interrupt number 24

+100 to +103 (Note 1)

Software interrupt number 25

+104 to +107 (Note 1)

Software interrupt number 26

+108 to +111 (Note 1)

Software interrupt number 27

+112 to +115 (Note 1)

Software interrupt number 28

+116 to +119 (Note 1)

Software interrupt number 29

+120 to +123 (Note 1)

Software interrupt number 30

+124 to +127 (Note 1)

Software interrupt number 31

+128 to +131 (Note 1)

Software interrupt number 32

+252 to +255 (Note 1)

Software interrupt number 63

Note 1: Address relative to address in interrupt table register (INTB).
Note 2: It is selected by interrupt request cause select bit (bit 4 in address 035E

Note 3: When IIC mode is selected, NACK and ACK interrupts are selected.
Note 4: It is selected by interrupt request cause select bit (bit 6, 7 in address 035F

Cannot be masked I flag

+40 to +43 (Note 1)

Software interrupt number 10

+60 to +63 (Note 1)

Software interrupt number 15

+64 to +67 (Note 1)

Software interrupt number 16

+20 to +23 (Note 1)

Software interrupt number 5

+24 to +27 (Note 1)

Software interrupt number 6

+28 to +31 (Note 1)

Software interrupt number 7

+32 to +35 (Note 1)

Software interrupt number 8

+16 to +19 (Note 1)

INT3

Software interrupt number 4

+36 to +39 (Note 1)

Timer A6

Software interrupt number 9

Timer A7

Timer B3

Timer B4

Timer B5

DMA0

DMA1

Key input interrupt

A-D

UART0 transmit

UART0 receive

UART1 transmit

UART1 receive

Timer A0

Timer A1

Timer A2

Timer A3/INT4

Timer A4/INT5

Timer B0

Timer B1

Timer B2

INT0

INT1

INT2

Software interrupt

Timer A5/Bus collision detection

UART2 transmit / NACK (Note 3)

UART2 receive / ACK (Note 3)

(Note 2)

(Note 4)

· Variable vector tables

The addresses in the variable vector table can be modified, according to the user's settings. Indicate

the first address using the interrupt table register (INTB). The 256-byte area subsequent to the ad-

dress the INTB indicates becomes the area for the variable vector tables. One vector table comprises

four bytes. Set the first address of the interrupt routine in each vector table. Table 1.10.2 shows the

interrupts assigned to the variable vector tables and addresses of vector tables.

Interrupt

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M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Figure 1.10.3. Interrupt control registers

Symbol

Address

When reset

INTiIC(i=0 to 2)

005D

to 005F

XX00X000

(i=3)

0044

XX00X000

TAiIC/INTjIC(i=3, 4)

0058

, 0059

XX00X000

(j=4, 5)

0058

, 0059

XX00X000

Bit name

Function

Bit symbol

ILVL0

POL

Nothing is assigned.

In an attempt to write to these bits, write "0". The value, if read, turns
out to be indeterminate.

Interrupt priority level
select bit

Interrupt request bit

Polarity select bit

Reserved bit

0: Interrupt not requested
1: Interrupt requested

0 : Selects falling edge
1 : Selects rising edge

Must always be set to "0"

ILVL1

ILVL2

Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the

interrupt request for that register. For details, see the precautions for interrupts.

(Note 1)

Interrupt control register (Note2)

Bit name

Function

Bit symbol

Symbol

Address

When reset

TBiIC(i=3 to 5)

0045

to 0047

XXXXX000

TAiIC(i=6, 7)

0048

, 0049

XXXXX000

TA5IC/BCNIC

004A

XXXXX000

DMiIC(i=0, 1)

004B

, 004C

XXXXX000

KUPIC

004D

XXXXX000

ADIC

004E

XXXXX000

SiTIC(i=0 to 2)

0051

, 0053

, 004F

XXXXX000

SiRIC(i=0 to 2)

0052

, 0054

, 0050

XXXXX000

TAiIC(i=0 to 2)

0055

to 0057

XXXXX000

TBiIC(i=0 to 2)

005A

to 005C

XXXXX000

ILVL0

Interrupt priority level
select bit

Interrupt request bit

0 : Interrupt not requested
1 : Interrupt requested

ILVL1

ILVL2

Nothing is assigned.

In an attempt to write to these bits, write "0". The value, if read, turns
out to be indeterminate.

(Note 1)

Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the

interrupt request for that register. For details, see the precautions for interrupts.

0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7

b2 b1 b0

0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7

b2 b1 b0

Interrupt Control

Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the

priority to be accepted. What is described here does not apply to non-maskable interrupts.

Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selec-

tion bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is

indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit

are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the

IPL are located in the flag register (FLG).

Figure 1.10.3 shows the memory map of the interrupt control registers.

Interrupt

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Table 1.10.4. Interrupt levels enabled according

to the contents of the IPL

Table 1.10.3. Settings of interrupt priority

levels

Interrupt priority

level select bit

Interrupt priority

level

Priority

order

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Level 0 (interrupt disabled)

Level 1

Level 2

Level 3

Level 4

Level 5

Level 6

Level 7

Low

High

b2 b1 b0

Enabled interrupt priority levels

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Interrupt levels 1 and above are enabled

Interrupt levels 2 and above are enabled

Interrupt levels 3 and above are enabled

Interrupt levels 4 and above are enabled

Interrupt levels 5 and above are enabled

Interrupt levels 6 and above are enabled

Interrupt levels 7 and above are enabled

All maskable interrupts are disabled

IPL

Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)

Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits

of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared

with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.

Therefore, setting the interrupt priority level to "0" disables the interrupt.

Table 1.10.3 shows the settings of interrupt priority levels and Table 1.10.4 shows the interrupt levels

enabled, according to the contents of the IPL.

The following are conditions under which an interrupt is accepted:

· interrupt enable flag (I flag) = 1

· interrupt request bit = 1

· interrupt priority level > IPL

The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are

independent, and they are not affected by one another.

Interrupt

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Rewrite the interrupt control register

To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for

that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after

the interrupt is disabled. The program examples are described as follow:

When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the

interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-

ated. This will depend on the instruction. If this creates problems, use the below instructions to change

the register.

Instructions : AND, OR, BCLR, BSET

Example 1:

INT_SWITCH1:

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear TA0IC int. priority level and int. request bit.

NOP

; Four NOP instructions are required when using HOLD function.

NOP
FSET

; Enable interrupts.

Example 2:

INT_SWITCH2:

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear TA0IC int. priority level and int. request bit.

MOV.W MEM, R0

; Dummy read.

FSET

; Enable interrupts.

Example 3:

INT_SWITCH3:

PUSHC FLG

; Push Flag register onto stack

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear TA0IC int. priority level and int. request bit.

POPC

FLG

; Enable interrupts.

The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.

Interrupt

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Interrupt Sequence

An interrupt sequence -- what are performed over a period from the instant an interrupt is accepted to the

instant the interrupt routine is executed -- is described here.

If an interrupt occurs during execution of an instruction, the processor determines its priority when the

execution of the instruction is completed, and transfers control to the interrupt sequence from the next

cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,

the processor temporarily suspends the instruction being executed, and transfers control to the interrupt

sequence.

In the interrupt sequence, the processor carries out the following in sequence given:

(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading ad-

dress 00000

. After this, the corresponding interrupt request bit becomes "0".

(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence

in the temporary register (Note) within the CPU.

(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to

"0" (the U flag, however does not change if the INT instruction, in software interrupt numbers 32

through 63, is executed)

(4) Saves the content of the temporary register (Note) within the CPU in the stack area.

(5) Saves the content of the program counter (PC) in the stack area.

(6) Sets the interrupt priority level of the accepted instruction in the IPL.

After the interrupt sequence is completed, the processor resumes executing instructions from the first

address of the interrupt routine.

Note: This register cannot be utilized by the user.

Interrupt Response Time

'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first

instruction within the interrupt routine has been executed. This time comprises the period from the

occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the

time required for executing the interrupt sequence (b). Figure 1.10.4 shows the interrupt response time.

Instruction

Interrupt sequence

Instruction in

interrupt routine

Time

Interrupt response time

(a)

(b)

Interrupt request acknowledged

Interrupt request generated

(a) Time from interrupt request is generated to when the instruction then under execution is completed.
(b) Time in which the instruction sequence is executed.

Figure 1.10.4. Interrupt response time

Interrupt

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Interrupt sources without priority levels

Value set in the IPL

_______

Watchdog timer, NMI

Other

Not changed

Variation of IPL when Interrupt Request is Accepted

If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.

If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown

in Table 1.10.6 is set in the IPL.

Table 1.10.6. Relationship between interrupts without interrupt priority levels and IPL

Stack pointer (SP) value

Interrupt vector address

16-Bit bus, without wait

8-Bit bus, without wait

Even

Odd (Note 2)

Even

Odd

Even

Odd

18 cycles (Note 1)

19 cycles (Note 1)

20 cycles (Note 1)

Table 1.10.5. Time required for executing the interrupt sequence

Reset

Indeterminate

The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.

Indeterminate

SP-2

contents

SP-4

contents

vec

contents

vec+2

contents

Interrupt

information

Address

0000

Indeterminate

SP-2

SP-4

vec

vec+2

BCLK

Internal

address bus

Internal

data bus

Internal

write signal

Internal

read signal

Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the

DIVX instruction (without wait).

Time (b) is as shown in Table 1.10.5.

________

Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence

interrupt or of a single-step interrupt.

Note 2: Locate an interrupt vector address in an even address, if possible.

Figure 1.10.5. Time required for executing the interrupt sequence

Interrupt

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Saving Registers

In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter

(PC) are saved in the stack area.

First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8

lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the

program counter. Figure 1.10.6 shows the state of the stack as it was before the acceptance of the

interrupt request, and the state the stack after the acceptance of the interrupt request.

Save other necessary registers at the beginning of the interrupt routine using software. Using the

PUSHM instruction alone can save all the registers except the stack pointer (SP).

Address

Content of previous stack

Stack area

[SP]
Stack pointer
value before
interrupt occurs

m 1

m 2

m 3

m 4

Stack status before interrupt request
is acknowledged

Stack status after interrupt request
is acknowledged

Content of previous stack

m + 1

MSB

LSB

m 1

m 2

m 3

m 4

Address

Flag register (FLG

)

Content of previous stack

Stack area

Flag register

(FLG

)

Program

counter (PC

)

[SP]
New stack
pointer value

Content of previous stack

m + 1

MSB

LSB

Program counter (PC

)

Program counter (PC

)

Figure 1.10.6. State of stack before and after acceptance of interrupt request

Interrupt

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Figure 1.10.7. Operation of saving registers

(2) Stack pointer (SP) contains odd number

[SP]

(Odd)

[SP] 1 (Even)

[SP] 2(Odd)

[SP] 3 (Even)

[SP] 4(Odd)

[SP] 5 (Even)

Address

Sequence in which order
registers are saved

(2)

(1)

Finished saving registers
in four operations.

(3)

(4)

(1) Stack pointer (SP) contains even number

[SP]

(Even)

[SP] 1(Odd)

[SP] 2 (Even)

[SP] 3(Odd)

[SP] 4 (Even)

[SP] 5 (Odd)

Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.

After registers are saved, the SP content is [SP] minus 4.

Address

Program counter (PC

)

Stack area

Flag register (FLG

)

Program counter (PC

)

Sequence in which order
registers are saved

(2) Saved simultaneously,

all 16 bits

(1) Saved simultaneously,

all 16 bits

Finished saving registers
in two operations.

Program counter (PC

)

Stack area

Flag register (FLG

)

Program counter (PC

)

Saved simultaneously,
all 8 bits

Flag register

(FLG

)

Program

counter (PC

)

Flag register

(FLG

)

Program

counter (PC

)

The operation of saving registers carried out in the interrupt sequence is dependent on whether the

content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the

content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the

program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at

a time. Figure 1.10.7 shows the operation of the saving registers.

Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the stack pointer

indicated by the U flag. Otherwise, it is the interrupt stack pointer (ISP).

Interrupt

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Interrupt Priority

If there are two or more interrupt requests occurring at a point in time within a single sampling (checking

whether interrupt requests are made), the interrupt assigned a higher priority is accepted.

Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level

select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware

priority is accepted.

Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority),

watchdog timer interrupt, etc. are regulated by hardware.

Figure 1.10.8 shows the priorities of hardware interrupts.

Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches

invariably to the interrupt routine.

Returning from an Interrupt Routine

Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register

(FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter

(PC), both of which have been saved in the stack area. Then control returns to the program that was being

executed before the acceptance of the interrupt request, so that the suspended process resumes.

Return the other registers saved by software within the interrupt routine using the POPM or similar instruc-

tion before executing the REIT instruction.

Interrupt resolution circuit

When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest

priority level. Figure 1.10.9 shows the circuit that judges the interrupt priority level.

Figure 1.10.8. Hardware interrupts priorities

_______

________

Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match

______

INT Interrupt

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

______

INT Interrupt

________

INT0 to INT5 are triggered by the edges of external inputs. The edge polarity is selected using the polarity select bit.

________

Of interrupt control registers, 0058

is used both as timer A3 and external interrupt INT4 input control register, and

________

0059

is used both as timer A4 and as external interrupt INT5 input control register. Use the interrupt request cause

select bits - bits 6 and 7 of the interrupt request cause select register 1 (address 035F

) - to specify which interrupt

________

request cause to select. When INT4 is selected as an interrupt source, the input port for it can be selected by bits 0 and

________

1 of the interrupt source select register 0 (address 035E

). Similarly, when INT5 is selected as an interrupt source, the

input port for it can be selected by bits 2 and 3 of the interrupt source select register 0 (address 035E

). After having

set an interrupt request cause and interrupt input ports, be sure to set the corresponding interrupt request bit to "0"

before enabling an interrupt.

Either of the interrupt control registers - 0058

, 0059

- has the polarity-switching bit. Be sure to set this bit to "0" to

select an timer as the interrupt request cause.

As for external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge by setting

_______

"1" in the INTi interrupt polarity switching bit of the interrupt request cause select register 1 (035F

). To select two

edges, set the polarity switching bit of the corresponding interrupt control register to `falling edge' ("0").

________

When INT4 input pin select bits = "11", INT4 interrupt polarity switching bit = "0", and polarity select bit = "1" of the INT4

interrupt control register, an interrupt is generated by a rising edge on the input port when the exclusive pin is "H", as

shown by "Single edge, Rise" in Figure 1.10.12. When the exclusive pin is "H", interrupts can only be generated by an

________

active transition on a single edge. The same applies to INT5.

Figure 1.10.10 shows the interrupt request cause select register.

Figure 1.10.10. Interrupt request cause select registers 0, 1

Interrupt request cause select register 1

Bit name

Function

Bit

symbol

Symbol

Address

When reset

IFSR1

035F

IFSR10

INT0 interrupt polarity
switching bit

0 : Timer A3
1 : INT4

0 : Timer A4
1 : INT5

0 : One edge
1 : Two edges

INT1 interrupt polarity
switching bit

INT2 interrupt polarity
switching bit

INT3 interrupt polarity
switching bit

INT4 interrupt polarity
switching bit

INT5 interrupt polarity
switching bit

0 : One edge
1 : Two edges

Interrupt request cause
select bit

IFSR11

IFSR12

IFSR13

IFSR14

IFSR15

IFSR16

IFSR17

Interrupt request cause select register 0

Bit name

Function

Bit

symbol

Symbol

Address

When reset

IFSR0

035E

X0000000

IFSR00

INT4 input pin select bit

00: No INT4 input
01: P4

input enabled

10: P4

input enabled

11: P4

, P4

input enabled

0 : Timer A5
1 :

Bus collision detection

INT5 input pin select bit

Interrupt request cause
select bitt

Reserved bit

Must always be set to "0"

IFSR01

IFSR02

IFSR03

IFSR04

00: No INT5 input
01: P8

input enabled

10: P8

input enabled

11: P8

, P8

input enabled

Nothing is assigned.

In an attempt to write to this bit, write "0". The value, if read, turns out
to be

indeterminate.

______

_______

INT Interrupt, NMI Interrupt

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

TAiOUT/INT

i+1

TAiIN/INT

i+1

INTi+1
input pin
select bit

i=3, 4

Two edge detect

Interrupt edge
select bit

Interrupt
request

Polarity select bit

(bit4 of interrupt control register)

Falling edge

Rising edge

"H"

"L"

INT4, INT5 interrupt polarity switching bit

(Bits 4, 5 of interrupt request cause select register 1)

One edge

Two edges

______

NMI Interrupt

______

An NMI interrupt is generated when the input to the P7

/NMI pin changes from "H" to "L". The NMI interrupt

is a non-maskable external interrupt. The pin level can be checked in the port P7

03ED

This pin cannot be used as a normal port input.

________

Figure 1.10.11. Constitution of INT4 and INT5

________

Figure 1.10.12. Typical timings in two input interrupt of INT4 and INT5 selected

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Key Input Interrupt

Figure 1.10.13. Block diagram of key input interrupt

Key Input Interrupt

A key input interrupt request is generated when an active edge selected by the key input mode register's

P1, P2 key input select bits occurs on one of input ports P1

to P1

, P2

to P2

, or P3

to P3

whose

direction register is set for input and which has been enabled for key input by the key input enable bit. For

to P3

, key input interrupt requests are always generated by a falling edge.

A key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop

mode. When using an oscillator connected between X

CIN

--X

COUT

and the corresponding port has been set

to have a pullup, if the P1, P2 key input select bits (bits 0, 2 at address 0126

) are set for "Two edges" and

the P1, P2 key input enable bits (bits 1, 3 at address 0126

) are "Enabled", pullups on P1

to P1

and P2

to P2

are automatically turned on and the port is pulled "H" for only a period of about 244 us (Note) at

intervals of approximately 7.8 ms (Note), as shown in Figure 1.10.15. And if the key input enable bit (bit 1,

3 and 4 at the address 0126

) is set to "enable", sometimes the interrupt request bit may be set to "1",

therefore set the interrupt request bit to "0" with a program.

Figure 1.10.13 shows a block diagram for key input interrupts. Note that when a "L" signal is applied to any

pin which has had its key input enable bit set to "0" and is not processed for input inhibition, input to other

pins are not detected as an interrupt. The f

C32

is affected by a clock prescaler reset flag.

Note : X

CIN

= 32.768kH

(Address 004D

)

/KI

Port P1

-P1

pull-up select bit

Port P1

direction register

Pull-up
transistor

/KI

Pull-up
transistor

Port P3

direction register

Port P3

direction register

Two edge detect

P1 key input select bit · P1 key input enable bit

P1 key input select bit

Port P3

direction register

Port P3 pull-up select bit

1/8

C32

CK Q

Port P1, P2 pull-up select bit

"0"

"1"

"0"

CK Q

Two edge detect

"0"

"1"

"0"

Pull-up
transistor

CK Q

Two edge detect

"0"

"1"

"0"

CK Q

Two edge detect

"0"

"1"

"0"

P1 key input enable bit

P2 key input enable bit

P1 key input enable bit

Port P1

direction register

Port P1

direction register

Port P2

direction register

Port P2

direction register

P3 key input enable bit

Interrupt control circuit

Key input interrupt control register

Key input interrupt
request

One-shot
generating circuit

Key Input Interrupt

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Figure 1.10.14. Key input mode register

Key input mode register

Bit name

Function

Bit

symbol

Symbol

Address

When reset

KUPM

0126

01100000

P1KIS

P1 key input select bit (Note 1)

0 : Falling edge
1 : Two edges (Note 2)

0 : Disable
1 : Enable

0 : Falling edge
1 : Two edges (Note 2)

0 : Disable
1 : Enable

P1 key input enable bit

P2 key input select bit (Note 1)

P2 key input enable bit

P3 key input enable bit

P12

to P12

pull-up (Note 3)

The corresponding port is
pulled high with a pull-up
resistor
0 : Not pulled high
1 : Pulled high

P12

to P12

pull-up (Note 3)

P13

to P13

pull-up (Note 3)

P1KIE

P2KIS

P2KIE

P3KIE

PUP12L

PUP12H

PUP13

Note 1 : If this bit is set for "Two edges" when the corresponding port has been

specified to have a pullup, the port is automatically pulled high intermittently.
Operating sub-clock.

Note 2 : When this bit is set for "Two edges" and the input from either of the

corresponding pin is "L", if the pullup control register 0 of the corresponding port

(bit 2 to 5 at the address 03FC

) is changed, there may be the thing that the

key input interruption request is set to "1".

Note 3 : The pull-up resistance is not connected for pins that are set for output from

peripheral functions, regardless of the setting in the pull-up control register.

Figure 1.10.15. Intermittent pull-up operation

Direction register

Output

Input

Key input select bit

Falling edge

Two edges

Pull-up control

Pulled high

Key input enable bit

Disable

Enable

Pull-up

("H" : Pulled high
"L" : Not pulled high)

Approx. 244µs

(Note 1)(Note 2)

Approx. 244µs

(Note 1)

Approx. 7.8ms

(Note 1)

Intermittent pull-up operation starts

Approx. 7.8ms

(Note 1)

Key input value latch

Note 1 : X

CIN

= 32.768kHz

Not pulled high

Note 2 : There may be the thing that the key input interrupt request bit is set to "1" when input "L"

in the first key input value latch timing.

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Address Match Interrupt

Address Match Interrupt

An address match interrupt is generated when the address match interrupt address register contents match

the program counter value. Two address match interrupts can be set, each of which can be enabled and

disabled by an address match interrupt enable bit. Address match interrupts are not affected by the inter-

rupt enable flag (I flag) and processor interrupt priority level (IPL). The value of the program counter (PC)

for an address match interrupt varies depending on the instruction being executed.

Figure 1.10.16 shows the address match interrupt-related registers.

Figure 1.10.16. Address match interrupt-related registers

Bit name

Bit symbol

Symbol

Address When

reset

AIER

0009

XXXXXX00

Address match interrupt enable register

Function

Address match interrupt 0

enable bit

0 : Interrupt disabled
1 : Interrupt enabled

AIER0

Address match interrupt 1

enable bit

AIER1

Symbol

Address

When reset

RMAD0

0012

to 0010

X00000

RMAD1

0016

to 0014

X00000

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to
be indeterminated.

Address setting register for address match interrupt

Function

Values that can be set

Address match interrupt register i (i = 0, 1)

00000

to FFFFF

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to
be indeterminated.

0 : Interrupt disabled
1 : Interrupt enabled

b0 b7

(b19)

(b16)

(b15)

(b8)

(b23)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Precautions for Interrupts

Precautions for Interrupts

(1) Reading address 00000

· When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and

interrupt request level) in the interrupt sequence.

The interrupt request bit of the certain interrupt written in address 00000

will then be set to "0".

Reading address 00000

by software sets enabled highest priority interrupt source request bit to "0".

Though the interrupt is generated, the interrupt routine may not be executed.

Do not read address 00000

by software.

(2) Setting the stack pointer

· The value of the stack pointer immediately after reset is initialized to 0000

. Accepting an interrupt

before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in

_______

the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack

pointer at the beginning of a program. Concerning the first instruction immediately after reset, generat-

_______

ing any interrupts including the NMI interrupt is prohibited.

_______

(3) The NMI interrupt

_______

·The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc via a resistor (pull-up) if

unused. Be sure to work on it.

_______

· The NMI pin also serves as P7

, which is exclusively input. Reading the contents of the P7 register

allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time

_______

when the NMI interrupt is input.

_______

· Do not reset the CPU with the input to the NMI pin being in the "L" state.

_______

· Do not attempt to go into stop mode with the input to the NMI pin being in the "L" state. With the input to

_______

the NMI being in the "L" state, the CM10 is fixed to "0", so attempting to go into stop mode is turned

down.

_______

· Do not attempt to go into wait mode with the input to the NMI pin being in the "L" state. With the input to

_______

the NMI pin being in the "L" state, the CPU stops but the oscillation does not stop, so no power is saved.

In this instance, the CPU is returned to the normal state by a later interrupt.

_______

· Signals input to the NMI pin require an "L" level of 1 clock or more, from the operation clock of the CPU.

(4) External interrupt

________

· Either an "L" level or an "H" level of at least 250 ns width is necessary for the signal input to pins INT

________

through INT

regardless of the CPU operation clock.

________

· When the polarity of the INT

to INT

pins is changed, the interrupt request bit is sometimes set to "1".

After changing the polarity, set the interrupt request bit to "0". Figure 1.10.17 shows the procedure for

______

changing the INT interrupt generate factor.

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Precautions for Interrupts

Example 1:

INT_SWITCH1:

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear TA0IC int. priority level and int. request bit.

NOP

; Four NOP instructions are required when using HOLD function.

NOP
FSET

; Enable interrupts.

Example 2:

INT_SWITCH2:

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear TA0IC int. priority level and int. request bit.

MOV.W MEM, R0

; Dummy read.

FSET

; Enable interrupts.

Example 3:

INT_SWITCH3:

PUSHC FLG

; Push Flag register onto stack

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear TA0IC int. priority level and int. request bit.

POPC

FLG

; Enable interrupts.

(5) Rewrite the interrupt control register

· To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for

that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after

the interrupt is disabled. The program examples are described as follow:

· When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the

interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-

ated. This will depend on the instruction. If this creates problems, use the below instructions to change

the register.

Instructions : AND, OR, BCLR, BSET

Watchdog Timer

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Watchdog Timer

The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is

a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog

timer interrupt is generated when an underflow occurs in the watchdog timer. When X

is selected for the

BCLK

bit 7 of the watchdog timer control register (address 000F

) selects the prescaler division ratio (by

16 or by 128). When X

CIN

is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7

of the watchdog timer control register (address 000F

). Thus the watchdog timer's period can be calcu-

lated as given below. The watchdog timer's period is, however, subject to an error due to the prescaler.

BCLK

Write to the watchdog timer
start register
(address 000E

)

RESET

Watchdog timer
interrupt request

Watchdog timer

Set to
"7FFF

1/128

1/16

"CM07 = 0"
"WDC7 = 1"

"CM07 = 0"
"WDC7 = 0"

"CM07 = 1"

1/2

Prescaler

For example, suppose that BCLK runs at 10 MHz and that 16 has been chosen for the dividing ratio of the

prescaler, then the watchdog timer's period becomes approximately 52.4 ms.

The watchdog timer is initialized by writing to the watchdog timer start register (address 000E

) and when

a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is

reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by

writing to the watchdog timer start register (address 000E

). In stop mode and wait mode, the watchdog

timer and prescaler are stopped. Counting is resumed from the held value when the modes or state are

released.

Figure 1.11.1 shows the block diagram of the watchdog timer. Figure 1.11.2 shows the watchdog timer-

related registers.

With X

chosen for BCLK

Watchdog timer period =

prescaler dividing ratio (16 or 128) X watchdog timer count (32768)

BCLK

Figure 1.11.1. Block diagram of watchdog timer

With X

CIN

chosen for BCLK

Watchdog timer period =

prescaler dividing ratio (2) X watchdog timer count (32768)

BCLK

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMAC

DMAC

This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to

memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a

higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this

account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16-

bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 1.12.1 shows the block diagram

of the DMAC. Table 1.12.1 shows the DMAC specifications. Figures 1.12.2 to 1.12.4 show the registers

used by the DMAC.

Figure 1.12.1. Block diagram of DMAC

Data bus low-order bits

DMA latch high-order bits

DMA latch low-order bits

DMA0 source pointer SAR0(20)

DMA0 destination pointer DAR0 (20)

DMA0 forward address pointer (20) (Note)

Data bus high-order bits

Address bus

DMA1 destination pointer DAR1 (20)

DMA1 source pointer SAR1 (20)

DMA1 forward address pointer (20) (Note)

DMA0 transfer counter reload register TCR0 (16)

DMA0 transfer counter TCR0 (16)

DMA1 transfer counter reload register TCR1 (16)

DMA1 transfer counter TCR1 (16)

(addresses 0029

, 0028

)

(addresses 0039

, 0038

)

(addresses 0022

to 0020

)

(addresses 0026

to 0024

)

(addresses 0032

to 0030

)

(addresses 0036

to 0034

)

Note: Pointer is incremented by a DMA request.

Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer

request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the

interrupt priority level. The DMA transfer doesn't affect any interrupts either.

If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request

signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA

transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the

number of transfers. For details, see the description of the DMA request bit.

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMAC

Item

Specification

No. of channels

2 (cycle steal method)

Transfer memory space

· From any address in the 1M bytes space to a fixed address
· From a fixed address to any address in the 1M bytes space
· From a fixed address to a fixed address

(Note that DMA-related registers [0020

to 003F

] cannot be accessed)

Maximum No. of bytes transferred

128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)

DMA request factors (Note)

________

Falling edge of INT0 or INT1 or both edge
Timer A0 to timer A7 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 transfer and reception interrupt requests
UART1 transfer and reception interrupt requests
UART2 transfer and reception interrupt requests
A-D conversion interrupt requests
Software triggers

Channel priority

DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously

Transfer unit

8 bits or 16 bits

Transfer address direction

forward/fixed (forward direction cannot be specified for both source and
destination simultaneously)

Transfer mode

· Single transfer mode

After the transfer counter underflows, the DMA enable bit turns to

"0", and the DMAC turns inactive

· Repeat transfer mode

After the transfer counter underflows, the value of the transfer counter
reload register is reloaded to the transfer counter.

The DMAC remains active unless a "0" is written to the DMA enable bit.

DMA interrupt request generation timing When an underflow occurs in the transfer counter

Active

When the DMA enable bit is set to "1", the DMAC is active.

When the DMAC is active, data transfer starts every time a DMA
transfer request signal occurs.

Inactive

· When the DMA enable bit is set to "0", the DMAC is inactive.

· After the transfer counter underflows in single transfer mode
At the time of starting data transfer immediately after turning the DMAC active, the
value of one of source pointer and destination pointer - the one specified for the
forward direction - is reloaded to the forward direction address pointer, and the value
of the transfer counter reload register is reloaded to the transfer counter.

Writing to register

Registers specified for forward direction transfer are always write enabled.
Registers specified for fixed address transfer are write-enabled when
the DMA enable bit is "0".

Reading the register

Can be read at any time.
However, when the DMA enable bit is "1", reading the register set up as the

forward register is the same as reading the value of the forward address pointer.

Table 1.12.1. DMAC specifications

Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable

flag (I flag) nor by the interrupt priority level.

Reload timing for forward ad-

dress pointer and transfer

counter

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMAC

DMA0 request cause select register

Symbol

Address

When reset

DM0SL

03B8

Function

Bit symbol

DMA request cause

select bit

DSEL0

DSEL1

DSEL2

DSEL3

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".

Software DMA
request bit

If software trigger is selected, a
DMA request is generated by
setting this bit to "1" (When read,
the value of this bit is always "0")

DSR

b3 b2 b1 b0

Bit name

0 0 0 0 : Falling edge of INT0 pin
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3
0 1 1 0 : Timer A4 (DMS=0)

/two edges of INT0 pin (DMS=1)

0 1 1 1 : Timer B0 (DMS=0)

/Timer B3 (DMS=1)

1 0 0 0 : Timer B1 (DMS=0)

/Timer B4 (DMS=1)

1 0 0 1 : Timer B2 (DMS=0)

/Timer B5 (DMS=1)

1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART2 transmit
1 1 0 1 : UART2 receive
1 1 1 0 : A-D conversion
1 1 1 1 : UART1 transmit

DMA request cause
expansion select bit

DMS

0 : Normal
1 : Expanded cause

Figure 1.12.2. DMAC register (1)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMAC

DMAi control register

Symbol

Address

When reset

DMiCON(i=0,1)

002C

, 003C

00000X00

Bit name

Function

Bit symbol

Transfer unit bit select bit

0 : 16 bits
1 : 8 bits

DMBIT

DMASL

DMAS

DMAE

Repeat transfer mode

select bit

0 : Single transfer
1 : Repeat transfer

DMA request bit (Note 1)

0 : DMA not requested
1 : DMA requested

0 : Disabled
1 : Enabled

0 : Fixed
1 : Forward

DMA enable bit

Source address direction
select bit (Note 3)

Destination address
direction select bit (Note 3)

0 : Fixed
1 : Forward

DSD

DAD

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".

Note 1: DMA request can be cleared by resetting the bit.
Note 2: This bit can only be set to "0".
Note 3: Source address direction select bit and destination address direction select bit

cannot be set to "1" simultaneously.

(Note 2)

DMA1 request cause select register

Symbol

Address

When reset

DM1SL

03BA

Function

Bit symbol

DMA request cause

select bit

DSEL0

DSEL1

DSEL2

DSEL3

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".

Software DMA
request bit

If software trigger is selected, a
DMA request is generated by
setting this bit to "1" (When read,
the value of this bit is always "0")

DSR

b3 b2 b1 b0

0 0 0 0 : Falling edge of INT1 pin
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2(DMS=0)

/timer A5(DMS=1)

0 1 0 1 : Timer A3(DMS=0)

/timer A6 (DMS=1)

0 1 1 0 : Timer A4 (DMS=0)

/timer A7 (DMS=1)

0 1 1 1 : Timer B0 (DMS=0)

/two edges of INT1 (DMS=1)

1 0 0 0 : Timer B1
1 0 0 1 : Timer B2
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART2 transmit
1 1 0 1 : UART2 receive
1 1 1 0 : A-D conversion
1 1 1 1 : UART1 receive

Bit name

DMA request cause
expansion select bit

DMS

0 : Normal
1 : Expanded cause

Figure 1.12.3. DMAC register (2)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMAC

(b8)

(b15)

Function

R W

· Transfer counter
Set a value one less than the transfer count

Symbol

Address

When reset

TCR0

0029

, 0028

Indeterminate

TCR1

0039

, 0038

Indeterminate

DMAi transfer counter (i = 0, 1)

Transfer count

specification

0000

to FFFF

(b23)

(b8)

(b16)(b15)

(b19)

Function

R W

· Source pointer
Stores the source address

Symbol

Address

When reset

SAR0

0022

to 0020

Indeterminate

SAR1

0032

to 0030

Indeterminate

DMAi source pointer (i = 0, 1)

Transfer address

specification

00000

to FFFFF

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".

Symbol

Address

When reset

DAR0

0026

to 0024

Indeterminate

DAR1

0036

to 0034

Indeterminate

(b8)

(b15)

(b16)

(b19)

Function

R W

· Destination pointer
Stores the destination address

DMAi destination pointer (i = 0, 1)

Transfer address

specification

00000

to FFFFF

(b23)

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".

Figure 1.12.4. DMAC register (3)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMAC

(1) Transfer cycle

The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area

(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination

write). The number of read and write bus cycles depends on the source and destination addresses. Also,

the bus cycle itself is longer when software waits are inserted.

(a) Effect of source and destination addresses

When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd

addresses, there are one more source read cycle and destination write cycle than when the source

and destination both start at even addresses.

(b) Effect of software wait

When the SFR area or a memory area with a software wait is accessed, the number of cycles is

increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK.

Figure 1.12.5 shows the example of the transfer cycles for a source read. For convenience, the destina-

tion write cycle is shown as one cycle and the source read cycles for the different conditions are shown.

In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the

transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respec-

tive conditions to both the destination write cycle and the source read cycle.

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMAC

BCLK

(Internal signal)

Address bus

(Internal signal)

RD signal

(Internal signal)

WR signal

(Internal signal)

Data bus

(Internal signal)

CPU use

Source

Destination

Dummy
cycle

(1) 8-bit transfers

16-bit transfers and the source address is even.

BCLK

(Internal signal)

Address bus

(Internal signal)

RD signal

(Internal signal)

WR signal

(Internal signal)

Data bus

(Internal signal)

CPU use

Source

Destination

Dummy
cycle

(3) One wait is inserted into the source read under the conditions in (1)

BCLK

(Internal signal)

Address bus

(Internal signal)

RD signal

(Internal signal)

WR signal

(Internal signal)

Data bus

(Internal signal)

CPU use

Source

Destination

Dummy
cycle

Source + 1

(2) 16-bit transfers and the source address is odd

BCLK

(Internal signal)

Address bus

(Internal signal)

RD signal

(Internal signal)

WR signal

(Internal signal)

Data bus

(Internal signal)

CPU use

Source

Destination

Dummy
cycle

Source + 1

(4) One wait is inserted into the source read under the conditions in (2)

Note: The same timing changes occur with the respective conditions at the destination as at the source.

Figure 1.12.5. Example of the transfer cycles for a source read

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMAC

DMA enable bit

Setting the DMA enable bit to "1" makes the DMAC active. The DMAC carries out the following operations

at the time data transfer starts immediately after DMAC is turned active.

(1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the

forward direction - to the forward direction address pointer.

(2) Reloads the value of the transfer counter reload register to the transfer counter.

Thus overwriting "1" to the DMA enable bit with the DMAC being active carries out the operations given

above, so the DMAC operates again from the initial state at the instant "1" is overwritten to the DMA

enable bit.

DMA request bit

The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of

DMA request factors for each channel.

DMA request factors include the following.

* Factors effected by using the interrupt request signals from the built-in peripheral functions and software

DMA factors (internal factors) effected by a program.

* External factors effected by utilizing the input from external interrupt signals.

For the selection of DMA request factors, see the descriptions of the DMAi factor selection register.

The DMA request bit turns to "1" if the DMA transfer request signal occurs regardless of the DMAC's state

(regardless of whether the DMA enable bit is set "1" or "0"). It turns to "0" immediately before data transfer

starts.

In addition, it can be set to "0" by use of a program, but cannot be set to "1".

There can be instances in which a change in DMA request factor selection bit causes the DMA request bit

to turn to "1". So be sure to set the DMA request bit to "0" after the DMA request factor selection bit is

changed.

The DMA request bit turns to "1" if a DMA transfer request signal occurs, and turns to "0" immediately

before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the

DMA request bit, if read by use of a program, turns out to be "0" in most cases. To examine whether the

DMAC is active, read the DMA enable bit.

Here follows the timing of changes in the DMA request bit.

(1) Internal factors

Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to "1" due

to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to

turn to "1" due to several factors.

Turning the DMA request bit to "0" due to an internal factor is timed to be effected immediately before the

transfer starts.

(2) External factors

An external factor is a factor caused to occur by the leading edge of input from the INTi pin (i depends on

which DMAC channel is used).

Selecting the INTi pins as external factors using the DMA request factor selection bit causes input from

these pins to become the DMA transfer request signals.

The timing for the DMA request bit to turn to "1" when an external factor is selected synchronizes with the

signal's edge applicable to the function specified by the DMA request factor selection bit (synchronizes

with the trailing edge of the input signal to each INTi pin, for example).

With an external factor selected, the DMA request bit is timed to turn to "0" immediately before data

transfer starts similarly to the state in which an internal factor is selected.

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMAC

(3) The priorities of channels and DMA transfer timing

If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period from

the leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels concurrently

turn to "1". If the channels are active at that moment, DMA0 is given a high priority to start data transfer.

When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU finishes single bus

access, then DMA1 starts data transfer and gives the bus right to the CPU.

An example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer

request signals due to external factors concurrently occur.

Figure 1.12.6 An example of DMA transfer effected by external factors.

BCLK

DMA0

DMA1

DMA0
request bit

DMA1
request bit

CPU

INT0

INT1

Obtainm
ent of the
bus right

An example in which DMA transmission is carried out in minimum
cycles at the time when DMA transmission request signals due to
external factors concurrently occur.

Figure 1.12.6. An example of DMA transfer effected by external factors

Timer

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer

There are fourteen 16-bit timers. These timers can be classified by function into timers A (eight) and timers

B (six). All these timers function independently. Figures 1.13.1 and 1.13.2 show the block diagram of

timers.

Figure 1.13.1. Timer A block diagram

· Timer mode
· One-shot mode
· PWM mode

· Event counter mode

TA0

TA1

TA2

TA3

(Note 1)

TA4

(Note 2)

Timer A0

Timer A1

Timer A2

Timer A3

Timer A4

C132

Timer A0 interrupt

Timer A1 interrupt

Timer A2 interrupt

Timer A3 interrupt

Timer A4 interrupt

Noise

filter

Noise

filter

Noise

filter

Noise

filter

Noise

filter

1/8

1/4

Timer B2 overflow

Note 1: The TA3

pin (P4

) is shared with INT

pin, so be careful.

Note 2: The TA4

pin (P8

) is shared with INT

pin, so be careful.

· Timer mode
· One-shot mode
· PWM mode

· Event counter mode

TA5

TA6

TA7

Timer A5

Timer A6

Timer A7

Noise

filter

Noise

filter

Noise

filter

1/32

C32

CIN

Clock prescaler reset flag (bit 7
at address 0381

) set to "1"

Reset

Clock prescaler

C132

132

clock select bit

(bit 4 at address 0007

)

Port P0 real time
output trigger

Port P1 real time
output trigger

Port P12 real time
output trigger

Timer A5 interrupt

Timer A6 interrupt

Timer A7 interrupt

Port P2 real time
output trigger

Timer B5 overflow

Timer

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Figure 1.13.2. Timer B block diagram

· Event counter mode

· Timer mode
· Pulse width measuring mode

TB0

TB1

TB2

Timer B0

Timer B1

Timer B2

C132

Timer B0 interrupt

Noise

filter

Noise

filter

Noise

filter

1/32

C32

1/8

1/4

CIN

Clock prescaler reset flag (bit 7
at address 0381

) set to "1"

Reset

Clock prescaler

Timer A0 to timer A4

· Event counter mode

· Timer mode
· Pulse width measuring mode

TB3

TB4

TB5

Timer B3

Timer B4

Timer B5

Timer B3 interrupt

Noise

filter

Noise

filter

Noise

filter

Timer B1 interrupt

Timer B2 interrupt

Timer B4 interrupt

Timer B5 interrupt

C132

Timer A5 to timer A7

132

clock select bit

(bit 4 at address 0007

)

Timer A

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer A

Figure 1.13.3 shows the block diagram of timer A. Figures 1.13.4 to 1.13.8 show the timer A-related

registers.

Use the timer Ai mode register (i = 0 to 7) bits 0 and 1 to choose the desired mode.

Timer A has the four operation modes listed as follows:

· Timer mode: The timer counts an internal count source.

· Event counter mode: The timer counts pulses from an external source or a timer over flow.

· One-shot timer mode: The timer stops counting when the count reaches "0000

· Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.

Figure 1.13.4. Timer A-related registers (1)

Figure 1.13.3. Block diagram of timer A

Count start flag

(Address 0340

, 0380

)

Up count/down count

TAi

Addresses

TAj

TAk

TBm

Timer A0

0387

0386

Timer A4

Timer A1

Timer B2

Timer A1

0389

0388

Timer A0

Timer A2

Timer B2

Timer A2

038B

038A

Timer A1

Timer A3

Timer B2

Timer A3

038D

038C

Timer A2

Timer A4

Timer B2

Timer A4

038F

038E

Timer A3

Timer A0

Timer B2

Timer A5

0347

0346

Timer A7

Timer A6

Timer B5

Timer A6

0349

0348

Timer A5

Timer A7

Timer B5

Timer A7

034B

034A

Timer A6

Timer A5

Timer B5

Always down count except
in event counter mode

Reload register (16)

Counter (16)

Low-order
8 bits

High-order
8 bits

Clock source
selection

· Timer
(gate function)

· Timer
· One shot
· PWM

External
trigger

TAi

(i = 0 to 7)

TBm overflow

(m = 2 when i 4, m = 5 when i 5)

· Event counter

C132

Clock selection

TAj overflow

(j = i 1. Note, however, that j = 4 when i = 0,
j = 6 when i = 5, j = 5 when i = 7)

Pulse output

Toggle flip-flop

TAi

OUT

(i = 0 to 7)

Data bus low-order bits

Data bus high-order bits

Up/down flag

Down count

(Address 0344

, 0384

)

TAk overflow

(k = i + 1. Note, however, that k = 0 when i = 4,
k = 7 when i = 5, k = 6 when i = 7)

Polarity

selection

Timer Ai mode register

Symbol

Address

When reset

TAiMR(i=0 to 4)

0396

to 039A

(i=5 to 7)

0356

to 0358

Bit name

Function

Bit symbol

0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation

(PWM) mode

b1 b0

TCK1

MR3

MR2

MR1

TMOD1

MR0

TMOD0

TCK0

Function varies with each operation mode

Count source select bit
(Function varies with each operation mode)

Operation mode select bit

Timer A

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Figure 1.13.5. Timer A-related registers (2)

Symbol

Address

When reset

TABSR0

0380

Count start flag 0

Bit name

Function

Bit symbol

Timer B2 count start flag

Timer B1 count start flag

Timer B0 count start flag

Timer A4 count start flag

Timer A3 count start flag

Timer A2 count start flag

Timer A1 count start flag

Timer A0 count start flag

0 : Stops counting
1 : Starts counting

TB2S

TB1S

TB0S

TA4S

TA3S

TA2S

TA1S

TA0S

Symbol

Address

When reset

TA0

0387

,0386

Indeterminate

TA1

0389

,0388

Indeterminate

TA2

038B

,038A

Indeterminate

TA3

038D

,038C

Indeterminate

TA4

038F

,038E

Indeterminate

TA5

0347

,0346

Indeterminate

TA6

0349

,0348

Indeterminate

TA7

034B

,034A

Indeterminate

b0 b7

(b15)

(b8)

Timer Ai register (Note 1)

· Timer mode

0000

to FFFF

Counts an internal count source

Function

Values that can be set

· Event counter mode

0000

to FFFF

Counts pulses from an external source or timer overflow

· One-shot timer mode

0000

to FFFF

Counts a one shot width

(Note 2, Note 4)

· Pulse width modulation mode (16-bit PWM)
Functions as a 16-bit pulse width modulator

· Pulse width modulation mode (8-bit PWM)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator

0000

to FFFE

(Note 3, Note 4)

Symbol

Address

When reset

TABSR1

0340

000XX000

Count start flag 1

Bit name

Function

Bit symbol

Timer B5 count start flag

Timer B4 count start flag

Timer B3 count start flag

Timer A7 count start flag

Timer A6 count start flag

Timer A5 count start flag

0 : Stops counting
1 : Starts counting

TB5S

TB4S

TB3S

TA7S

TA6S

TA5S

0 : Stops counting
1 : Starts counting

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.

Note 1: Read and write data in 16-bit units.
Note 2: When the timer Ai register is set to "0000

", the counter does not

operate and the timer Ai interrupt request is not generated. When the
pulse is set to output, the pulse does not output from the TAi

OUT

pin.

Note 3: When the timer Ai register is set to "0000

", the pulse width

modulator does not operate and the output level of the TAi

OUT

remains "L" level, therefore the timer Ai interrupt request is not
generated. This also occurs in the 8-bit pulse width modulator mode
when the significant 8 high-order bits in the timer Ai register are set to
"00

Note 4: Use MOV instruction to write to this register.

to FE

(High-order address)

to FF

(Low-order address)

(Note 3, Note 4)

Timer A

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Figure 1.13.6. Timer A-related registers (3)

Timer A7 up/down flag

Timer A6 up/down flag

Timer A5 up/down flag

Timer A7 two-phase pulse
signal processing select bit

Symbol

Address

When reset

UDF1

0344

XX0XX000

TA7P

Up/down flag 1 (Note)

Bit name

Function

Bit symbol

TA7UD

TA6UD

TA5UD

0 : Down count
1 : Up count

This specification becomes valid
when the up/down flag content is
selected for up/down switching
cause

0 : two-phase pulse signal

processing disabled

1 : two-phase pulse signal

processing enabled

When not using the two-phase
pulse signal processing function,
set the select bit to "0"

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.

Timer A4 up/down flag

Timer A3 up/down flag

Timer A2 up/down flag

Timer A1 up/down flag

Timer A0 up/down flag

Timer A2 two-phase pulse
signal processing select bit

Timer A3 two-phase pulse
signal processing select bit

Timer A4 two-phase pulse
signal processing select bit

Symbol

Address

When reset

UDF0

0384

TA4P

TA3P

TA2P

Up/down flag 0 (Note)

Bit name

Function

Bit symbol

TA4UD

TA3UD

TA2UD

TA1UD

TA0UD

0 : Down count
1 : Up count

This specification becomes valid
when the up/down flag content is
selected for up/down switching
cause

0 : two-phase pulse signal

processing disabled

1 : two-phase pulse signal

processing enabled

When not using the two-phase
pulse signal processing function,
set the select bit to "0"

TA1OS

TA2OS

TA0OS

One-shot start flag 0

Symbol

Address

When reset

ONSF0

0382

00X00000

Timer A0 one-shot start flag

Timer A1 one-shot start flag

Timer A2 one-shot start flag

Timer A3 one-shot start flag

Timer A4 one-shot start flag

TA3OS

TA4OS

Bit name

Function

Bit symbol

Nothing is assigned.
In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate.

TA0TGL

TA0TGH

0 0 :

Input on TA0

is selected (Note)

0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected

Timer A0 event/trigger
select bit

b7 b6

Note: Set the corresponding port direction register to "0".

1 : Timer start
When read, the value is "0"

Note : Use MOV instruction to write to this register.

Timer A

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Figure 1.13.7. Timer A-related registers (4)

TA1TGL

Symbol

Address

When reset

TRGSR0

0383

Timer A1 event/trigger
select bit

0 0 :

Input on TA1

is selected (Note)

0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected

Trigger select register 0

Bit name

Function

Bit symbol

0 0 :

Input on TA2

is selected (Note)

0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected

0 0 :

Input on TA3

is selected (Note)

0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected

0 0 :

Input on TA4

is selected (Note)

0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected

Timer A2 event/trigger
select bit

Timer A3 event/trigger
select bit

Timer A4 event/trigger
select bit

TA1TGH

TA2TGL

TA2TGH

TA3TGL

TA3TGH

TA4TGL

TA4TGH

b1 b0

b3 b2

b5 b4

b7 b6

Note: Set the corresponding port direction register to "0".

TA6TGL

Symbol

Address

When reset

TRGSR1

0343

XXXX0000

Timer A6 event/trigger
select bit

0 0 :

Input on TA6

is selected (Note)

0 1 : TB5 overflow is selected
1 0 : TA5 overflow is selected
1 1 : TA7 overflow is selected

Trigger select register 1

Bit name

Function

Bit symbol

0 0 :

Input on TA7

is selected (Note)

0 1 : TB5 overflow is selected
1 0 : TA5 overflow is selected
1 1 : TA6 overflow is selected

Timer A7 event/trigger
select bit

TA6TGH

TA7TGL

TA7TGH

b1 b0

b3 b2

Note: Set the corresponding port direction register to "0".

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.

TA6OS

TA7OS

TA5OS

One-shot start flag 1

Symbol

Address

When reset

ONSF1

0342

00XXX000

Timer A5 one-shot start flag

Timer A6 one-shot start flag

Timer A7 one-shot start flag

Bit name

Function

Bit symbol

TA5TGL

TA5TGH

0 0 :

Input on TA5

is selected (Note)

0 1 : TB5 overflow is selected
1 0 : TA6 overflow is selected
1 1 : TA7 overflow is selected

Timer A5 event/trigger
select bit

b7 b6

Note: Set the corresponding port direction register to "0".

1 : Timer start
When read, the value is "0"

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.

Timer A

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Item

Specification

Count source

, f

C132

Count operation

· Down count

· When the timer underflows, it reloads the reload register contents before continuing counting

Divide ratio

1/(n+1)

n : Set value

Count start condition

Count start flag is set (= 1)

Count stop condition

Count start flag is reset (= 0)

Interrupt request generation timing

When the timer underflows

TAi

pin function

Programmable I/O port or gate input

TAi

OUT

pin function

Programmable I/O port or pulse output

Read from timer

Count value can be read out by reading timer Ai register

Write to timer

· When counting stopped

When a value is written to timer Ai register, it is written to both reload register and counter

· When counting in progress

When a value is written to timer Ai register, it is written to only reload register

(Transferred to counter at next reload time)

Select function

· Gate function

Counting can be started and stopped by the TAi

pin's input signal

· Pulse output function

Each time the timer underflows, the TAi

OUT

pin's polarity is reversed

(1) Timer mode

In this mode, the timer counts an internally generated count source. (See Table 1.13.1.) Figure 1.13.9

shows the timer Ai mode register in timer mode.

Table 1.13.1. Specifications of timer mode

Figure 1.13.9. Timer Ai mode register in timer mode

Note 1: The settings of the corresponding port register and port direction register

are invalid.

Note 2: The bit can be "0" or "1".

Note 3: Set the corresponding port direction register to "0" .

Timer Ai mode register

Symbol

Address

When reset

TAiMR(i=0 to 4)

0396

to 039A

(i=5 to 7)

0356

to 0358

Bit name

Function

Bit symbol

Operation mode
select bit

0 0 : Timer mode

b1 b0

TMOD1

TMOD0

MR0

Pulse output function
select bit

0 : Pulse is not output
(TA

iOUT

pin is a normal port pin)

1 : Pulse is output (Note 1)
(TA

iOUT

pin is a pulse output pin)

Gate function select bit

0 X

(Note 2)

: Gate function not available

(TAi

pin is a normal port pin)

1 0 : Timer counts only when TA

iIN

pin is

held "L" (Note 3)

1 1 : Timer counts only when TA

iIN

pin is

held "H" (Note 3)

b4 b3

MR2

MR1

MR3

0 (Must always be "0" in timer mode)

0 0 : f

0 1 : f

1 0 : f

1 1 : f

C132

b7 b6

TCK1

TCK0

Count source select bit

0 0

Timer A

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Item

Specification

Count source

· External signals input to TAi

pin (effective edge can be selected by software)

· TB2 overflow, TB5 overflow, TAj overflow, TAk overflow

Count operation

· Up count or down count can be selected by external signal or software

· When the timer overflows or underflows, it reloads the reload register con

tents before continuing counting (Note)

Divide ratio

1/ (FFFF

- n + 1) for up count

1/ (n + 1) for down count

n : Set value

Count start condition

Count start flag is set (= 1)

Count stop condition

Count start flag is reset (= 0)

Interrupt request generation timing The timer overflows or underflows
TAi

pin function

Programmable I/O port or count source input

TAi

OUT

pin function

Programmable I/O port, pulse output, or up/down count select input

Read from timer

Count value can be read out by reading timer Ai register

Write to timer

· When counting stopped

When a value is written to timer Ai register, it is written to both reload register and counter

· When counting in progress

When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)

Select function

· Free-run count function

Even when the timer overflows or underflows, the reload register content is not reloaded to it

· Pulse output function

Each time the timer overflows or underflows, the TAi

OUT

pin's polarity is reversed

Note: This does not apply when the free-run function is selected.

(2) Event counter mode

In this mode, the timer counts an external signal or an internal timer's overflow. Timers A0, A1, A5 and A6
can count a single-phase external signal. Timers A2, A3, A4 and A7 can count a single-phase and a two-
phase external signal. Table 1.13.2 lists timer specifications when counting a single-phase external
signal. Figure 1.13.10 shows the timer Ai mode register in event counter mode.
Table 1.13.3 lists timer specifications when counting a two-phase external signal. Figure 1.13.11 shows

the timer Ai mode register in event counter mode.

Table 1.13.2. Timer specifications in event counter mode (when not processing two-phase pulse signal)

Figure 1.13.10. Timer Ai mode register in event counter mode

Timer Ai mode register
(When not using two-phase pulse signal processing)

Note 1: In event counter mode, the count source is selected by the event / trigger select bit.

(addresses 0342

, 0343

, 0382

, and 0383

)

Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Valid only when counting an external signal.
Note 4: When an "L" signal is input to the TAi

OUT

pin, the downcount is activated. When "H",

the upcount is activated. Set the corresponding port direction register to "0".

Symbol

Address

When reset

TAiMR(i = 0 to 4) 0396

to 039A

(i = 5 to 7) 0356

to 0358

Operation mode select bit

0 1 : Event counter mode

(Note 1)

b1 b0

TMOD0

MR0

Pulse output function
select bit

0 : Pulse is not output

(TA

iOUT

pin is a normal port pin)

1 : Pulse is output (Note 2)

(TA

iOUT

pin is a pulse output pin)

Count polarity
select bit (Note 3)

MR2

MR1

MR3

0 (Must always be "0" in event counter mode)

TCK0

Count operation type
select bit

0 : Counts external signal's falling edge
1 : Counts external signal's rising edge

Up/down switching
cause select bit

0 : Up/down flag's content
1 : TA

iOUT

pin's input signal (Note 4)

0 : Reload type
1 : Free-run type

Bit symbol

Bit name

Function

R W

TCK1

Invalid in event counter mode
Can be "0" or "1"

TMOD1

Timer A

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Item

Specification

Count source

· Two-phase pulse signals input to TAi

or TAi

OUT

Count operation

· Up count or down count can be selected by two-phase pulse signal

· When the timer overflows or underflows, the reload register content is

reloaded and the timer starts over again (Note 1)

Divide ratio

1/ (FFFF

n + 1) for up count

1/ (n + 1) for down count

n : Set value

Count start condition

Count start flag is set (= 1)

Count stop condition

Count start flag is reset (= 0)

Interrupt request generation timing

Timer overflows or underflows

TAi

pin function

Two-phase pulse input

TAi

OUT

pin function

Two-phase pulse input

Read from timer

Count value can be read out by reading timer A2, A3, A4 or A7 register

Write to timer

· When counting stopped

When a value is written to timer A2, A3, A4 or A7 register, it is written to both

reload register and counter

· When counting in progress

When a value is written to timer A2, A3, A4 or A7 register, it is written to only

reload register. (Transferred to counter at next reload time.)

Select function (Note 2)

· Normal processing operation

The timer counts up rising edges or counts down falling edges on the TAi

pin when input signal on the TAi

OUT

pin is "H"

· Multiply-by-4 processing operation

If the phase relationship is such that the TAi

pin goes "H" when the input

signal on the TAi

OUT

pin is "H", the timer counts up rising and falling edges

on the TAi

OUT

and TAi

pins. If the phase relationship is such that the

TAi

pin goes "L" when the input signal on the TAi

OUT

pin is "H", the timer

counts down rising and falling edges on the TAi

OUT

and TAi

pins.

Note 1: This does not apply when the free-run function is selected.

Note 2: Timer A3 alone can be selected. Timer A2 and timer A7 are fixed to normal processing operation,

and timer A4 is fixed to multiply-by-4 processing operation.

Table 1.13.3. Timer specifications in event counter mode (when processing two-phase pulse signal with timers A2, A3, A4 and A7)

TAi

OUT

Up
count

Down
count

TAi

(i=2, 3, 7)

TAi

OUT

TAi

(i=3, 4)

Count up all edges

Count down all edges

Timer A

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Figure 1.13.11. Timer Ai mode register in event counter mode

Note 1 : This bit is valid for timer A3 mode register. Timer A2 and timer A7 are fixed to normal

processing operation, and timer A4 is fixed to multiply-by-4 processing operation.

Note 2 : When performing two-phase pulse signal processing, make sure the two-phase pulse

signal processing operation select bit (addresses 0384

and 0344

) is set to "1".

Also, always be sure to set the event/trigger select bit (addresses 0383

and 0343

)

to "00".

Timer Ai mode register
(When using two-phase pulse signal processing)

Symbol

Address

When reset

TAiMR(i = 2 to 4) 0398

to 039A

(i = 7)

0358

Operation mode select bit

0 1 : Event counter mode

b1 b0

TMOD1

TMOD0

MR0

0 (Must always be "0" when using two-phase pulse signal
processing)

MR2

MR1

MR3

0 (Must always be "0" when using two-phase pulse signal
processing)

TCK1

TCK0

0 1

1 (Must always be "1" when using two-phase pulse signal
processing)

Bit symbol

Bit name

Function

Count operation type
select bit

Two-phase pulse
processing operation
select bit (Note 1)(Note 2)

0 : Reload type
1 : Free-run type

0 : Normal processing operation
1 : Multiply-by-4 processing operation

Timer A

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Item

Specification

Count source

, f

C132

Count operation

· The timer counts down

· When the count reaches 0000

, the timer stops counting after reloading a new count

· If a trigger occurs when counting, the timer reloads a new count and restarts counting

Divide ratio

1/n n : Set value

Count start condition

· An external trigger is input

· The timer overflows

· The one-shot start flag is set (= 1)

Count stop condition

· A new count is reloaded after the count has reached 0000

· The count start flag is reset (= 0)

Interrupt request generation timing

The count reaches 0000

TAi

pin function

Programmable I/O port or trigger input

TAi

OUT

pin function

Programmable I/O port or pulse output

Read from timer

When timer Ai register is read, it indicates an indeterminate value

Write to timer

· When counting stopped

When a value is written to timer Ai register, it is written to both reload

· When counting in progress

When a value is written to timer Ai register, it is written to only reload register

(Transferred to counter at next reload time)

Table 1.13.4. Timer specifications in one-shot timer mode

Figure 1.13.12. Timer Ai mode register in one-shot timer mode

(3) One-shot timer mode

In this mode, the timer operates only once. (See Table 1.13.4.) When a trigger occurs, the timer starts up
and continues operating for a given period. Figure 1.13.12 shows the timer Ai mode register in one-shot
timer mode.

Bit name

Timer Ai mode register

Symbol

Address

When reset

TAiMR(i = 0 to 4) 0396

to 039A

(i = 5 to 7) 0356

to 0358

Function

Bit symbol

Operation mode select bit

1 0 : One-shot timer mode

b1 b0

TMOD1

TMOD0

MR0

Pulse output function
select bit

0 : Pulse is not output
(TA

iOUT

pin is a normal port pin)

1 : Pulse is output (Note 1)
(TAi

OUT

pin is a pulse output pin)

MR2

MR1

MR3

0 (Must always be "0" in one-shot timer mode)

0 0 : f

0 1 : f

1 0 : f

1 1 : f

C132

b7 b6

TCK1

TCK0

Count source select bit

1 0

0 : One-shot start flag is valid
1 : Selected by event/trigger select

Trigger select bit

External trigger select
bit (Note 2)

0 : Falling edge of TAi

pin's input signal (Note 3)

1 : Rising edge of TAi

pin's input signal (Note 3)

Note 1: The settings of the corresponding port register and port direction register are invalid.
Note 2: Valid only when the TA

iIN

pin is selected by the event/trigger select bit

(addresses 0342

, 0343

, 0382

and 0383

). If timer overflow is selected,

this bit can be "1" or "0" .

Note 3: Set the corresponding port direction register to "0" .

Timer A

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

(4) Pulse width modulation (PWM) mode

In this mode, the timer outputs pulses of a given width in succession. (See Table 1.13.5.) In this mode, the

counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure

1.13.13 shows the timer Ai mode register in pulse width modulation mode. Figure 1.13.14 shows the

example of how a 16-bit pulse width modulator operates. Figure 1.13.15 shows the example of how an 8-

bit pulse width modulator operates.

Figure 1.13.13. Timer Ai mode register in pulse width modulation mode

Table 1.13.5. Timer specifications in pulse width modulation mode

Item

Specification

Count source

, f

C132

Count operation

· The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)
· The timer reloads a new count at a rising edge of PWM pulse and continues counting
· The timer is not affected by a trigger that occurs when counting

16-bit PWM

· High level width

n / fj

n : Set value fj=f

, f

C132

· Cycle time

-1) / fj fixed

8-bit PWM

· High level width n (m+1) / fj

n : values set to timer Ai register's high-order address

· Cycle time

-1) (m+1) / fj

m : values set to timer Ai register's low-order address

Count start condition

· External trigger is input
· The timer overflows
· The count start flag is set (= 1)

Count stop condition

· The count start flag is reset (= 0)

Interrupt request generation timing

PWM pulse goes "L"

TAi

pin function

Programmable I/O port or trigger input

TAi

OUT

pin function

Pulse output

Read from timer

When timer Ai register is read, it indicates an indeterminate value

Write to timer

· When counting stopped

When a value is written to timer Ai register, it is written to both reload
register and counter

· When counting in progress

When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)

Bit name

Timer Ai mode register

Symbol

Address

When reset

TAiMR(i=0 to 4)

0396

to 039A

(i=5 to 7)

0356

to 0358

Function

Bit symbol

Operation mode
select bit

1 1 : PWM mode

b1 b0

TMOD1

TMOD0

MR0

MR2

MR1

MR3

0 0 : f

0 1 : f

1 0 : f

1 1 : f

C132

b7 b6

TCK1

TCK0

Count source select bit

1 (Must always be "1" in PWM mode)

16/8-bit PWM mode
select bit

0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator

Trigger select bit

External trigger select
bit (Note 1)

0: Falling edge of TAi

pin's input signal (Note 2)

1: Rising edge of TAi

pin's input signal (Note 2)

0: Count start flag is valid
1: Selected by event/trigger select register

Note 1: Valid only when the TA

iIN

pin is selected by the event/trigger select bit

(addresses 0342

, 0343

, 0382

and 0383

). If timer overflow is selected,

this bit can be "1" or "0".

Note 2: Set the corresponding port direction register to "0" .

Timer A

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Figure 1.13.14. Example of how a 16-bit pulse width modulator operates

Figure 1.13.15. Example of how an 8-bit pulse width modulator operates

1 / f

(2 1)

Count source

iIN

input signal

PWM pulse output
from TA

iOUT

Condition : Reload register = 0003

, when external trigger

(rising edge of TA

iIN

pin input signal) is selected

Trigger is not generated by this signal

"H"

"L"

Timer Ai interrupt
request bit

"1"

"0"

Cleared to "0" when interrupt request is accepted, or cleared by software

: Frequency of count source

, f

C132

)

Note: n = 0000

to FFFE

1 / f

Count source (Note1)

iIN

pin input signal

Underflow signal of
8-bit prescaler (Note2)

PWM pulse output
from TA

iOUT

"H"

"L"

"1"

"0"

Timer Ai interrupt
request bit

Cleared to "0" when interrupt request is accepted, or cleaerd by software

: Frequency of count source

, f

C132

)

Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 00

to FF

; n = 00

to FE

Condition : Reload register high-order 8 bits = 02

Reload register low-order 8 bits = 02

External trigger (falling edge of TA

iIN

pin input signal) is selected

1 / f

X (m

+ 1) X (2 1)

1 / f

X (m + 1) X n

1 / f

X (m + 1)

Timer B

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer B

Figure 1.13.16 shows the block diagram of timer B. Figures 1.13.17 and 1.13.18 show the timer B-related

registers.

Use the timer Bi mode register (i = 0 to 5) bits 0 and 1 to choose the desired mode.

Timer B has three operation modes listed as follows:

· Timer mode: The timer counts an internal count source.

· Event counter mode: The timer counts pulses from an external source or a timer overflow.

· Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or

pulse width.

Figure 1.13.16. Block diagram of timer B

Timer Bi mode register

Symbol

Address

When reset

TBiMR(i = 0 to 2) 039B

to 039D

00XX0000

TBiMR(i = 3 to 5) 035B

to 035D

00XX0000

Bit name

Function

Bit symbol

0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/pulse width

measurement mode

1 1 : Must not be set

b1 b0

TCK1

MR3

MR2

MR1

TMOD1

MR0

TMOD0

TCK0

Function varies with each operation mode

Count source select bit
(Function varies with each operation mode)

Operation mode select bit

(Note 1)

(Note 2)

Note 1: Timer B0, timer B3.
Note 2: Timer B1, timer B2, timer B4, timer B5.

Clock source selection

(address 0380

)

· Event counter

· Timer
· Pulse period/pulse width measurement

Reload register (16)

Low-order 8 bits

High-order 8 bits

Data bus low-order bits

Data bus high-order bits

TBj overflow
(j = i 1. Note, however,
j = 2 when i = 0,
j = 5 when i = 3)

Can be selected in only
event counter mode

Count start flag

C132

Polarity switching
and edge pulse

TBi

(i = 0 to 5)

Counter reset circuit

Counter (16)

TBi Address

TBj

Timer B0 0391

0390

Timer B2

Timer B1 0393

0392

Timer B0

Timer B2 0395

0394

Timer B1

Timer B3 0351

0350

Timer B5

Timer B4 0353

0352

Timer B3

Timer B5 0355

0354

Timer B4

Figure 1.13.17. Timer B-related registers (1)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer B

Symbol

Address

When reset

TABSR 0

0380

Count start flag 0

Bit name

Bit symbol

Timer B2 count start flag

Timer B1 count start flag

Timer B0 count start flag

Timer A4 count start flag

Timer A3 count start flag

Timer A2 count start flag

Timer A1 count start flag

Timer A0 count start flag

0 : Stops counting
1 : Starts counting

TB2S

TB1S

TB0S

TA4S

TA3S

TA2S

TA1S

TA0S

Function

Symbol

Address

When reset

TB0

0391

, 0390

Indeterminate

TB1

0393

, 0392

Indeterminate

TB2

0395

, 0394

Indeterminate

TB3

0351

, 0350

Indeterminate

TB4

0353

, 0352

Indeterminate

TB5

0355

, 0354

Indeterminate

b0 b7

(b15)

(b8)

Timer Bi register (Note)

· Pulse period / pulse width measurement mode
Measures a pulse period or width

· Timer mode

0000

to FFFF

Counts the timer's period

Function

Values that can be set

· Event counter mode

0000

to FFFF

Counts external pulses input or a timer overflow

Note: Read and write data in 16-bit units.

Symbol

Address

When reset

CPSRF

0381

0XXXXXXX

Clock prescaler reset flag

Bit name

Function

Bit symbol

Clock prescaler reset flag

0 : No effect
1 : Prescaler is reset
(When read, the value is "0")

CPSR

Nothing is assigned.

In an attempt to write to these bits, write "0". The value, if read, turns
out to be

indeterminate.

Symbol

Address

When reset

TABSR1

0340

000XX000

Count start flag 1

Bit name

Function

Bit symbol

Timer B5 count start flag

Timer B4 count start flag

Timer B3 count start flag

Timer A7 count start flag

Timer A6 count start flag

Timer A5 count start flag

0 : Stops counting
1 : Starts counting

TB5S

TB4S

TB3S

TA7S

TA6S

TA5S

0 : Stops counting
1 : Starts counting

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.

Figure 1.13.18. Timer B-related registers (2)

Timer B

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Item

Specification

Count source

, f

C132

Count operation

· Counts down

· When the timer underflows, it reloads the reload register contents before

continuing counting

Divide ratio

1/(n+1)

n : Set value

Count start condition

Count start flag is set (= 1)

Count stop condition

Count start flag is reset (= 0)

Interrupt request generation timing

The timer underflows

TBi

pin function

Programmable I/O port

Read from timer

Count value is read out by reading timer Bi register

Write to timer

· When counting stopped

When a value is written to timer Bi register, it is written to both reload register and counter

· When counting in progress

When a value is written to timer Bi register, it is written to only reload register

(Transferred to counter at next reload time)

(1) Timer mode

In this mode, the timer counts an internally generated count source. (See Table 1.13.6.) Figure 1.13.19

shows the timer Bi mode register in timer mode.

Table 1.13.6. Timer specifications in timer mode

Note 1: Timer B0, timer B3.
Note 2: Timer B1, timer B2, timer B4, timer B5.

Timer Bi mode register

Symbol

Address

When reset

TBiMR(i=0 to 2)

039B

to 039D

00XX0000

(i=3 to 5)

035B

to 035D

00XX0000

Bit name

Function

Bit symbol

Operation mode select bit

0 0 : Timer mode

b1 b0

TMOD1

TMOD0

MR0

Invalid in timer mode
Can be "0" or "1"

MR2

MR1

MR3

0 0 : f

0 1 : f

1 0 : f

1 1 : f

C132

TCK1

TCK0

Count source select bit

Invalid in timer mode.
In an attempt to write to this bit, write "0". The value, if read in
timer mode, turns out to be indeterminate.

0 (Must always be "0" in timer mode ; i = 0, 3)

Nothing is assiigned (i = 1, 2, 4, 5).
In an attempt to write to this bit, write "0". The value, if read, turns out
to be indeterminate.

(Note 1)

(Note 2)

b7 b6

Figure 1.13.19. Timer Bi mode register in timer mode

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer B

Item

Specification

Count source

· External signals input to TBi

· Effective edge of count source can be a rising edge, a falling edge, or falling

and rising edges as selected by software

Count operation

· Counts down

· When the timer underflows, it reloads the reload register contents before

continuing counting

Divide ratio

1/(n+1)

n : Set value

Count start condition

Count start flag is set (= 1)

Count stop condition

Count start flag is reset (= 0)

Interrupt request generation timing The timer underflows

TBi

pin function

Count source input

Read from timer

Count value can be read out by reading timer Bi register

Write to timer

· When counting stopped

When a value is written to timer Bi register, it is written to both reload register and counter

· When counting in progress

When a value is written to timer Bi register, it is written to only reload register

(Transferred to counter at next reload time)

(2) Event counter mode

In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.13.7.)

Figure 1.13.20 shows the timer Bi mode register in event counter mode.

Table 1.13.7. Timer specifications in event counter mode

Figure 1.13.20. Timer Bi mode register in event counter mode

Timer Bi mode register

Symbol

Address

When reset

TBiMR(i=0 to 2)

039B

to 039D

00XX0000

(i=3 to 5)

035B

to 035D

00XX0000

Bit name

Function

Bit symbol

Operation mode select bit

0 1 : Event counter mode

b1 b0

TMOD1

TMOD0

MR0

Count polarity select
bit

(Note 1)

MR2

MR1

MR3

Invalid in event counter mode.
In an attempt to write to this bit, write "0". The value, if read in
event counter mode, turns out to be indeterminate.

TCK1

TCK0

0 1

0 0 : Counts external signal's

falling edges

0 1 : Counts external signal's

rising edges

1 0 : Counts external signal's

falling and rising edges

1 1 : Must not be set

b3 b2

Nothing is assigned (i = 1, 2, 4, 5).
In an attempt to write to this bit, write "0". The value, if read,
turns out to be indeterminate.

Note 1: Valid only when input from the TBi

pin is selected as the event clock.

If timer's overflow is selected, this bit can be "0" or "1".

Note 2: Timer B0, timer B3.
Note 3: Timer B1, timer B2, timer B4, timer B5.
Note 4: Set the corresponding port direction register to "0".

Invalid in event counter mode.
Can be "0" or "1".

Event clock select

0 : Input from TBi

pin (Note 4)

1 : TBj overflow

(j = i 1; however, j = 2 when i = 0,

j = 5 when i = 3)

0 (Must always be "0" in event counter mode; i = 0, 3)

(Note 2)

(Note 3)

Timer B

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Item

Specification

Count source

, f

C132

Count operation

· Up count

· Counter value "0000

" is transferred to reload register at measurement

pulse's effective edge and the timer continues counting

Count start condition

Count start flag is set (= 1)

Count stop condition

Count start flag is reset (= 0)

Interrupt request generation timing · When measurement pulse's effective edge is input

(Note 1)

· When an overflow occurs. (Simultaneously, the timer Bi overflow flag

changes to "1". The timer Bi overflow flag changes to "0" when the count

start flag is "1" and a value is written to the timer Bi mode register.)

TBi

pin function

Measurement pulse input

Read from timer

When timer Bi register is read, it indicates the reload register's content

(measurement result)

(Note 2)

Write to timer

Cannot be written to

(3) Pulse period/pulse width measurement mode

In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.13.8.)

Figure 1.13.21 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure

1.13.22 shows the operation timing when measuring a pulse period. Figure 1.13.23 shows the operation

timing when measuring a pulse width.

Table 1.13.8. Timer specifications in pulse period/pulse width measurement mode

Figure 1.13.21. Timer Bi mode register in pulse period/pulse width measurement mode

Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting.

Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer.

Timer Bi mode register

Symbol

Address

When reset

TBiMR(i=0 to 2)

039B

to 039D

00XX0000

(i=3 to 5)

035B

to 035D

00XX0000

Bit name

Bit symbol

Operation mode
select bit

1 0 : Pulse period / pulse width

measurement mode

b1 b0

TMOD1

TMOD0

MR0

Measurement mode
select bit

MR2

MR1

MR3

TCK1

TCK0

0 0 : Pulse period measurement (Interval between

measurement pulse's falling edge to falling edge)

0 1 : Pulse period measurement (Interval between

measurement pulse's rising edge to rising edge)

1 0 : Pulse width measurement (Interval between

measurement pulse's falling edge to rising edge,
and between rising edge to falling edge)

1 1 : Must not be set

Function

b3 b2

Nothing is assigned (i = 1, 2, 4, 5).
In an attempt to write to this bit, write "0". The value, if read, turns out to be
indeterminate.

Count source
select bit

Timer Bi overflow
flag ( Note 1)

0 : Timer did not overflow
1 : Timer has overflowed

0 0 : f

0 1 : f

1 0 : f

1 1 : f

C132

b7 b6

Note 1: The timer Bi overflow flag changes to "0" when the count start flag is "1" and a value is written to the

timer Bi mode register. This flag cannot be set to "1" by software.

Note 2: Timer B0, timer B3.
Note 3: Timer B1, timer B2, timer B4, timer B5.

0 (Must always be "0" in pulse period/pulse width measurement mode; i = 0, 3)

(Note 2)

(Note 3)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer B

Figure 1.13.23. Operation timing when measuring a pulse width

Measurement pulse

"H"

Count source

Count start flag

Timer Bi interrupt
request bit

Timing at which counter
reaches "0000

"1"

Transfer
(measured value)

"L"

"0"

Timer Bi overflow flag

"1"

"0"

Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.

(Note 1)

Transfer
(measured
value)

(Note 1)

Cleared to "0" when interrupt request is accepted, or cleared by software.

(Note 2)

Transfer
(indeterminate
value)

Reload register counter
transfer timing

Figure 1.13.22. Operation timing when measuring a pulse period

Count source

Measurement pulse

Count start flag

Timer Bi interrupt
request bit

Timing at which counter
reaches "0000

"H"

"1"

Transfer
(indeterminate value)

"L"

"0"

Timer Bi overflow flag

"1"

"0"

Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.

(Note 1)

When measuring measurement pulse time interval from falling edge to falling edge

(Note 2)

Cleared to "0" when interrupt request is accepted, or cleared by software.

Transfer
(measured value)

"1"

Reload register counter
transfer timing

Real time Port

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Real time Port

When real time port output is selected, the real time port data written to the port Pm register is latched into

the real time port latch each time the corresponding timer Ai underflows, with the data output from each

corresponding port. The real time port data is written to the corresponding port Pm register. When the real

time port mode select bit changes state from "0" to "1", the value of the real time port latch becomes "0",

which is output from the corresponding pin. It is when timer Ai underflows first that the real time port data is

output. If the real time port data is modified when the real time port function is enabled, the modified value

is output when timer Ai underflows next time. The port functions as an ordinary port when the real time port

function is disabled.

Make sure timer Ai for real time port output is set for timer mode, and is set to have "no gate function" using

the gate function select bit. Also, before setting the real time port mode select bit to "1", temporarily turn off

the timer Ai used and write its set value to the timer Ai register. Figure 1.14.1 shows the block diagram for

real time port output. Figure 1.14.2 shows the real time control register.

Figure 1.14.1. Block diagram for real time port output

· Timer mode

TAi

Timer Ai

C132

Timer Ai interrupt

Noise
filter

Timer Bj overflow

Port
latch

Data bus

Pm7

Pm0

Timer Ai+1
overflow

Timer Ak
overflow

j=2, k=4, 0, m=0, 1 when i=0, 1
j=5, k=7, 5, m=2, 12 when i=5, 6

Pm4 to Pm7 real time
port mode select bit

Port
latch

Data bus

Pm3

to Pm

real time port

mode select bit

Port
latch

Data bus

Pm4

Timer Ai mode register's set value used in real time port

Timer Ai mode register (Addresses 0356

, 0357

, 0396

and 0397

16)

Real time port latch

to Pm

real time port

mode select bit

to Pm

real time port

mode select bit

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Real time Port

Figure 1.14.3. Timing in real time port output operation

Figure 1.14.2. Real time port control register

Counter content (hex)

Time

Start count

Underflow

Count start flag

"1"

"0"

Timer Ai interrupt request bit

(i=0, 1, 5, 6)

"1"

"0"

Real time port output

Writing to port Pm register
(m=0, 1, 2, 12)

Value to port Pm (example)

"1"

"0"

Real time port mode

select bit

Real time port control register

Symbol

Address

When reset

RTP

03FF

Bit name

Function

Bit symbol

RTP2

to P1

real time port

mode select bi

RTP3

to P1

real time port

mode select bit

RTP4

to P2

real time port

mode select bi

RTP5

to P2

real time port

mode select bit

0 : I/O port
1 : Real time port output (Note)

RTP1

to P0

real time port

mode select bit

RTP0

to P0

real time port

mode select bit

RTP6

P12

to P12

real time port

mode select bit

RTP7

P12

to P12

real time port

mode select bit

Note : The corresponding port direction register is invalidated.

Serial I/O

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Serial I/O

Serial I/O is configured as three channels: UART0, UART1, UART2.

UART0 to 2

UART0, UART1 and UART2 each have an exclusive timer to generate a transfer clock, so they operate

independently of each other.

Figure 1.15.1 shows the block diagram of UART0, UART1 and UART2. Figures 1.15.2 and 1.15.3 show

the block diagram of the transmit/receive unit.

UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous

serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses

03A0

, 03A8

and 0378

) determine whether UARTi is used as a clock synchronous serial I/O or as a

UART. Although a few functions are different, UART0, UART1 and UART2 have almost the same functions.

UART2, in particular, is used for the SIM interface with some extra settings added in clock-asynchronous

serial I/O mode (Note). It also has the bus collision detection function that generates an interrupt request if

the TxD pin and the RxD pin are different in level.

Table 1.15.1 shows the comparison of functions of UART0 through UART2, and Figures 1.15.4 to 1.15.8

show the registers related to UARTi.

Note: SIM : Subscriber Identity Module

Note 1: Only when clock synchronous serial I/O mode.
Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode.
Note 3: Only when UART mode.
Note 4: Using for SIM interface.

UART0

UART1

UART2

Function

CLK polarity selection

Continuous receive mode selection

LSB first / MSB first selection

Impossible

Transfer clock output from multiple
pins selection

Impossible

Serial data logic switch

Impossible

Sleep mode selection

Impossible

TxD, RxD I/O polarity switch

Impossible

Possible

CMOS output

TxD, RxD port output format

CMOS output

N-channel open-drain
output

Impossible

Parity error signal output

Impossible

Bus collision detection

Impossible

Possible

(Note 1)

Possible

(Note 1)

Possible

(Note 1)

Possible

(Note 3)

Possible

(Note 1)

Possible

(Note 1)

Possible

(Note 1)

Possible

(Note 1)

Possible

(Note 3)

Possible

(Note 1)

Possible

(Note 2)

Possible

(Note 1)

Possible

(Note 4)

Possible

(Note 4)

Table 1.15.1. Comparison of functions of UART0 through UART2

Serial I/O

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Figure 1.15.1. Block diagram of UARTi (i = 0 to 2)

n0 : Values set to UART0 bit rate generator (BRG0)
n1 : Values set to UART1 bit rate generator (BRG1)
n2 : Values set to UART2 bit rate generator (BRG2)

RxD

Reception

control circuit

Transmission
control circuit

1 / (n

+1)

1/16

1/2

Bit rate generator

(address 0379

)

Clock synchronous type
(when internal clock is selected)

UART reception

Clock synchronous type

UART transmission

Clock synchronous type

(when internal clock is selected)

Clock synchronous type
(when external clock is
selected)

Receive
clock

Transmit
clock

CLK

CTS

/ RTS

Vcc

RTS

CTS

TxD

(UART2)

RxD polarity

reversing circuit

TxD

polarity

reversing

circuit

RxD

1 / (n

+1)

1/2

Bit rate generator

(address 03A1

)

Clock synchronous type
(when internal clock is selected)

UART reception

Clock synchronous type

UART transmission

Clock synchronous type

Clock synchronous type
(when internal clock is selected)

Clock synchronous type
(when external clock is
selected)

Receive
clock

Transmit
clock

CLK

Clock source selection

CTS

/ RTS

Reception

control circuit

Transmission
control circuit

Internal

External

Vcc

RTS

CTS

TxD

Transmit/

receive

unit

RxD

1 / (n

+1)

1/16

1/2

Bit rate generator

(address 03A9

)

Clock synchronous type
(when internal clock is selected)

UART reception

Clock synchronous type

UART transmission

Clock synchronous type

(when internal clock is selected)

Clock synchronous type
(when external clock is
selected)

Receive
clock

Transmit
clock

CLK

Clock source selection

Reception

control circuit

Transmission
control circuit

Internal

External

RTS

CTS

TxD

(UART1)

(UART0)

CLK

polarity

reversing

circuit

CLK

polarity

reversing

circuit

CTS/RTS disabled

Clock output pin
select switch

CTS

/ RTS

CLKS

CTS/RTS disabled

CTS/RTS selected

CTS/RTS disabled

CTS/RTS selected

CTS/RTS disabled

CTS/RTS
selected

CLK

polarity

reversing

circuit

Internal

External

Clock source selection

Transmit/

receive

unit

Transmit/

receive

unit

1/16

Serial I/O

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Figure 1.15.2. Block diagram of UARTi (i = 0, 1) transmit/receive unit

PAR

2SP

1SP

UART

UART (7 bits)
UART (8 bits)

UART (7 bits)

UART (9 bits)

Clock
synchronous
type

Clock synchronous
type

TxDi

UARTi transmit register

PAR
enabled

PAR
disabled

SP: Stop bit
PAR: Parity bit

UARTi transmit
buffer register

MSB/LSB conversion circuit

UART (8 bits)
UART (9 bits)

Clock synchronous
type

UARTi receive
buffer register

UARTi receive register

2SP

1SP

PAR
enabled

PAR
disabled

UART

UART (7 bits)

UART (9 bits)

Clock
synchronous
type

Clock
synchronous type

UART (7 bits)
UART (8 bits)

RxDi

Clock
synchronous type

UART (8 bits)
UART (9 bits)

Address 03A6

Address 03A7

Address 03AE

Address 03AF

Address 03A2

Address 03A3

Address 03AA

Address 03AB

Data bus low-order bits

MSB/LSB conversion circuit

PAR

"0"

Data bus high-order bits

Serial I/O

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

PAR

2SP

1SP

UART

UART
(7 bits)
UART
(8 bits)

UART(7 bits)

UART
(9 bits)

Clock
synchronous
type

Clock
synchronous type

Data bus low-order bits

TxD2

UART2 transmit register

PAR
disabled

PAR
enabled

UART2 transmit
buffer register

UART
(8 bits)
UART
(9 bits)

Clock
synchronous type

UART2 receive
buffer register

UART2 receive register

2SP

1SP

UART
(7 bits)
UART
(8 bits)

UART(7 bits)

UART
(9 bits)

Clock
synchronous type

RxD2

UART
(8 bits)
UART
(9 bits)

Address 037E

Address 037F

Address 037A

Address 037B

Data bus high-order bits

PAR

"0"

Reverse

No reverse

Error signal

output circuit

RxD data

reverse circuit

Error signal output
enable

Error signal output
disable

Reverse

No reverse

Logic reverse circuit + MSB/LSB conversion circuit

PAR
enabled

PAR
disabled

UART

Clock
synchronous
type

TxD data

reverse circuit

SP: Stop bit
PAR: Parity bit

Figure 1.15.3. Block diagram of UART2 transmit/receive unit

Serial I/O

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Figure 1.15.4. Serial I/O-related registers (1)

UARTi bit rate generator (Note 1, Note 2)

Symbol

Address

When reset

U0BRG

03A1

Indeterminate

U1BRG

03A9

Indeterminate

U2BRG

0379

Indeterminate

Function

Assuming that set value = n, BRGi divides the count source by
n + 1

to FF

Values that can be set

(b15)

(b8)

UARTi transmit buffer register (Note)

Function

Transmit data

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turn out to be indeterminate.

Symbol

Address

When reset

U0TB

03A3

, 03A2

Indeterminate

U1TB

03AB

, 03AA

Indeterminate

U2TB

037B

, 037A

Indeterminate

(b15)

Symbol

Address

When reset

U0RB

03A7

, 03A6

Indeterminate

U1RB

03AF

, 03AE

Indeterminate

U2RB

037F

, 037E

Indeterminate

(b8)

UARTi receive buffer register

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

Bit name

Bit

symbol

0 : No framing error
1 : Framing error found

0 : No parity error
1 : Parity error found

0 : No error
1 : Error found

Note 1: Bits 15 through 12 are set to "0" when the serial I/O mode select bit (bits 2 to 0 at addresses 03A0

03A8

and 0378

) are set to "000

" or the receive enable bit is set to "0".

(Bit 15 is set to "0" when bits 14 to 12 all are set to "0".) Bits 14 and 13 are also set to "0" when the
lower byte of the UARTi receive buffer register (addresses 03A6

, 03AE

and 037E

) is read out.

Note 2: Arbitration lost detecting flag is allocated to U2RB and noting but "0" may be written. Nothing is

assigned in bit 11 of U0RB and U1RB. These bits can neither be set or reset. When read, the value
of this bit is "0".

Invalid

OER

FER

PER

SUM

Overrun error flag (Note 1)

Framing error flag (Note 1)

Parity error flag (Note 1)

Error sum flag (Note 1)

0 : No overrun error
1 : Overrun error found

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".

Receive data

ABT

Arbitration lost detecting
flag (Note 2)

Invalid

0 : Not detected
1 : Detected

Note 1: Write a value to this register while transmit/receive halts.
Note 2: Use MOV instruction to write to this register.

Note: Use MOV instruction to write to this register.

Serial I/O

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

UARTi transmit/receive mode register

Symbol

Address

When reset

UiMR(i=0,1)

03A0

, 03A8

Bit name

Bit

symbol

Must be fixed to 001

0 0 0 : Serial I/O invalid
0 1 0 : Must not be set
0 1 1 : Must not be set
1 1 1 : Must not be set

b2 b1 b0

CKDIR

SMD1

SMD0

Serial I/O mode select bit

SMD2

Internal/external clock
select bit

STPS

PRY

PRYE

SLEP

Parity enable bit

0 : Internal clock
1 : External clock (Note)

Stop bit length select bit

Odd/even parity select bit

Sleep select bit

0 : One stop bit
1 : Two stop bits

0 : Parity disabled
1 : Parity enabled

0 : Sleep mode deselected
1 : Sleep mode selected

1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Must not be set
0 1 1 : Must not be set
1 1 1 : Must not be set

b2 b1 b0

0 : Internal clock
1 : External clock (Note)

Invalid

Valid when bit 6 = "1"
0 : Odd parity
1 : Even parity

Invalid

Must always be "0"

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

UART2 transmit/receive mode register

Symbol

Address

When reset

U2MR

0378

Bit name

Bit

symbol

Must be fixed to 001

0 0 0 : Serial I/O invalid
0 1 0 : (Note 1)
0 1 1 : Must not be set
1 1 1 : Must not be set

b2 b1 b0

CKDIR

SMD1

SMD0

Serial I/O mode select bit

SMD2

Internal/external clock
select bit

STPS

PRY

PRYE

IOPOL

Parity enable bit

0 : Internal clock
1 : External clock (Note 2)

Stop bit length select bit

Odd/even parity select bit

TxD, RxD I/O polarity
reverse bit

0 : One stop bit
1 : Two stop bits

0 : Parity disabled
1 : Parity enabled

0 : No reverse
1 : Reverse

Usually set to "0"

b2 b1 b0

Invalid

Valid when bit 6 = "1"
0 : Odd parity
1 : Even parity

Invalid

0 : No reverse
1 : Reverse

Usually set to "0"

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

Note 1: Bit 2 to bit 0 are set to "010

" when I

C mode is used.

Note 2: Set the corresponding port direction register to "0".

Must always be "0"

Note : Set the corresponding port direction register to "0".

Figure 1.15.5. Serial I/O-related registers (2)

Serial I/O

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

UARTi transmit/receive control register 0

Symbol

Address

When reset

UiC0(i=0,1)

03A4

, 03AC

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

TXEPT

CLK1

CLK0

CRS

CRD

NCH

CKPOL

BRG count source
select bit

Transmit register empty
flag

0 : Transmit data is output at

falling edge of transfer clock
and receive data is input at
rising edge

1 : Transmit data is output at

rising edge of transfer clock
and receive data is input at
falling edge

CLK polarity select bit

CTS/RTS function
select bit

CTS/RTS disable bit

Data output select bit

0 0 : f

is selected

0 1 : f

is selected

1 0 : f

is selected

1 1 : Must not be set

b1 b0

0 : LSB first
1 : MSB first

0 : Data present in transmit

1 : No data present in transmit

0 : CTS/RTS function enabled
1 : CTS/RTS function disabled

(P6

and P6

function as

programmable I/O port)

0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel

open-drain output

UFORM Transfer format select bit

0 0 : f

is selected

0 1 : f

is selected

1 0 : f

is selected

1 1 : Must not be set

b1 b0

Valid when bit 4 = "0"

0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)

Valid when bit 4 = "0"
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)

0 : Data present in transmit register

(during transmission)

1 : No data present in transmit

0: TXDi pin is CMOS output
1: TXDi pin is N-channel

open-drain output

Must always be "0"

Bit name

Bit

symbol

Must always be "0"

Note 1: Set the corresponding port direction register to "0".
Note 2: The settings of the corresponding port register and port direction register are invalid.

0 : CTS/RTS function enabled
1 : CTS/RTS function disabled

(P6

and P6

function as

programmable I/O port)

UART2 transmit/receive control register 0

Symbol

Address

When reset

U2C0

037C

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

TXEPT

CLK1

CLK0

CRS

CRD

CKPOL

BRG count source
select bit

Transmit register empty
flag

0 : Transmit data is output at

falling edge of transfer clock
and receive data is input at
rising edge

1 : Transmit data is output at

rising edge of transfer clock
and receive data is input at
falling edge

CLK polarity select bit

CTS/RTS function
select bit

CTS/RTS disable bit

0 0 : f

is selected

0 1 : f

is selected

1 0 : f

is selected

1 1 : Must not be set

b1 b0

0 : LSB first
1 : MSB first

0 : Data present in transmit

1 : No data present in transmit

0 : CTS/RTS function enabled
1 : CTS/RTS function disabled

(P7

functions

programmable I/O port)

0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel

open-drain output

UFORM Transfer format select bit

(Note 3)

0 0 : f

is selected

0 1 : f

is selected

1 0 : f

is selected

1 1 : Must not be set

b1 b0

Valid when bit 4 = "0"

0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)

Valid when bit 4 = "0"
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)

0 : Data present in transmit register

(during transmission)

1 : No data present in transmit

0: TXDi pin is CMOS output
1: TXDi pin is N-channel

open-drain output

Must always be "0"

Bit name

Bit

symbol

Note 1: Set the corresponding port direction register to "0".
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.

0 : CTS/RTS function enabled
1 : CTS/RTS function disabled

(P7

functions programmable

I/O port)

Nothing is assigned.

In an attempt to write to this bit, write "0". The value, if read, turns out to be "0".

0 : LSB first
1 : MSB first

Figure 1.15.6. Serial I/O-related registers (3)

Serial I/O

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Figure 1.15.7. Serial I/O-related registers (4)

UARTi transmit/receive control register 1

Symbol

Address

When reset

UiC1(i=0,1)

03A5

03AD

Bit name

Bit

symbol

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

Transmit enable bit

Receive enable bit

Receive complete flag

Transmit buffer
empty flag

0 : Transmission disabled
1 : Transmission enabled

0 : Data present in

transmit buffer register

1 : No data present in

transmit buffer register

0 : Reception disabled
1 : Reception enabled

0 : Transmission disabled
1 : Transmission enabled

0 : Data present in

transmit buffer register

1 : No data present in

transmit buffer register

0 : Reception disabled
1 : Reception enabled

0 : No data present in

receive buffer register

1 : Data present in

receive buffer register

0 : No data present in

receive buffer register

1 : Data present in

receive buffer register

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".

UART2 transmit/receive control register 1

Symbol

Address

When reset

U2C1

037D

Bit name

Bit

symbol

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

Transmit enable bit

Receive enable bit

Receive complete flag

Transmit buffer
empty flag

0 : Transmission disabled
1 : Transmission enabled

0 : Data present in

transmit buffer register

1 : No data present in

transmit buffer register

0 : Reception disabled
1 : Reception enabled

0 : Transmission disabled
1 : Transmission enabled

0 : Data present in

transmit buffer register

1 : No data present in

transmit buffer register

0 : Reception disabled
1 : Reception enabled

0 : No data present in

receive buffer register

1 : Data present in

receive buffer register

0 : No data present in

receive buffer register

1 : Data present in

receive buffer register

U2IRS

UART2 transmit interrupt
cause select bit

0 : Transmit buffer empty

(TI = 1)

1 : Transmit is completed

(TXEPT = 1)

0 : Transmit buffer empty

(TI = 1)

1 : Transmit is completed

(TXEPT = 1)

U2RRM UART2 continuous

receive mode enable bit

0 : Continuous receive

mode disabled

1 : Continuous receive

mode enabled

Must always be "0"

Data logic select bit

0 : No reverse
1 : Reverse

U2LCH

U2ERE Error signal output

enable bit

Must always be "0"

0 : Output disabled
1 : Output enabled

Serial I/O

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Note: When using multiple pins to output the transfer clock, the following requirements must be met:

· UART1 internal/external clock select bit (bit 3 at address 03A8

) = "0".

UART transmit/receive control register 2

Symbol

Address

When reset

UCON

03B0

X0000000

Bit

name

Bit

symbol

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

CLKMD0

CLKMD1

UART0 transmit
interrupt cause select bit

UART0 continuous
receive mode enable bit

0 : Continuous receive

mode disabled

1 : Continuous receive

mode enable

UART1 continuous
receive mode enable bit

CLK/CLKS select bit 0

UART1 transmit
interrupt cause select bit

0 :

Transmit buffer empty (Tl = 1)

1 : Transmission completed

(TXEPT = 1)

0 :

Transmit buffer empty (Tl = 1)

1 : Transmission completed

(TXEPT = 1)

0 : Normal mode

(CLK output is CLK1 only)

1 : Transfer clock output

from multiple pins
function selected

0 : Continuous receive

mode disabled

1 : Continuous receive

mode enabled

Nothing is assigned.
In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate.

0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed

(TXEPT = 1)

0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed

(TXEPT = 1)

Must always be "0"

U0IRS

U1IRS

U0RRM

U1RRM

Must always be "0"

Invalid

CLK/CLKS select
bit 1 (Note)

Valid when bit 5 = "1"
0 : Clock output to CLK1
1 : Clock output to CLKS1

UART2 special mode register

Symbol

Address

When reset

U2SMR

0377

b4 b3

Bit

name

Bit

symbol

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

ABSCS

ACSE

SSS

IIC mode selection bit

Bus busy flag

0 : STOP condition detected
1 : START condition detected

SCLL sync output
enable bit

Bus collision detect
sampling
clock select bit

Arbitration lost detecting
flag control bit

0 : Normal mode
1 : IIC mode

0 : Update per bit
1 : Update per byte

IICM

ABC

BBS

LSYN

0 : Ordinary
1 : Falling edge of RxD2

0 : Disabled
1 : Enabled

Transmit start condition
select bit

Must always be "0"

0 : Rising edge of transfer

clock

1 : Underflow signal of timer A0

Auto clear function
select bit of transmit
enable bit

0 : No auto clear function
1 : Auto clear at occurrence of

bus collision

Must always be "0"

Note: Nothing but "0" may be written.

(Note)

Reserved bit

Must always be set to "0"

Reserved bit

Must always be set to "0"

Figure 1.15.8. Serial I/O-related registers (5)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Clock synchronous serial I/O mode

(1) Clock synchronous serial I/O mode

The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 1.15.2
and 1.15.3 list the specifications of the clock synchronous serial I/O mode. Figure 1.15.9 shows the

UARTi transmit/receive mode register.

Table 1.15.2. Specifications of clock synchronous serial I/O mode (1)

Item

Specification

Transfer data format

· Transfer data length: 8 bits

Transfer clock

· When internal clock is selected (bit 3 at addresses 03A0

, 03A8

, 0378

= "0") : fi/ 2(n+1)

(Note 1) fi = f

, f

· When external clock is selected (bit 3 at addresses 03A0

, 03A8

, 0378

= "1") : Input from CLKi pin

Transmission/reception control

_______

CTS

function,

RTS

function,

CTS

and

RTS

function invalid: selectable

Transmission start condition

· To start transmission, the following requirements must be met:

Transmit enable bit (bit 0 at addresses 03A5

, 03AD

, 037D

) = "1"

Transmit buffer empty flag (bit 1 at addresses 03A5

, 03AD

, 037D

) = "0"

_______

When CTS function selected, CTS input level = "L"

· Furthermore, if external clock is selected, the following requirements must also be met:

CLKi polarity select bit (bit 6 at addresses 03A4

, 03AC

, 037C

) = "0":

CLKi input level = "H"

CLKi polarity select bit (bit 6 at addresses 03A4

, 03AC

, 037C

) = "1":

CLKi input level = "L"

Reception start condition

· To start reception, the following requirements must be met:

Receive enable bit (bit 2 at addresses 03A5

, 03AD

, 037D

) = "1"

Transmit enable bit (bit 0 at addresses 03A5

, 03AD

, 037D

) = "1"

Transmit buffer empty flag (bit 1 at addresses 03A5

, 03AD

, 037D

) = "0"

· Furthermore, if external clock is selected, the following requirements must

also be met:

CLKi polarity select bit (bit 6 at addresses 03A4

, 03AC

, 037C

) = "0":

CLKi input level = "H"

CLKi polarity select bit (bit 6 at addresses 03A4

, 03AC

, 037C

) = "1":

CLKi input level = "L"

· When transmitting

Transmit interrupt cause select bit (bits 0, 1 at address 03B0

, bit 4 at

address 037D

) = "0": Interrupts requested when data transfer from UARTi

transfer buffer register to UARTi transmit register is completed

Transmit interrupt cause select bit (bits 0, 1 at address 03B0

, bit 4 at

address 037D

) = "1": Interrupts requested when data transmission from

UARTi transfer register is completed

· When receiving

Interrupts requested when data transfer from UARTi receive register to

UARTi receive buffer register is completed

Error detection

· Overrun error (Note 2)

This error occurs when the next data is ready before contents of UARTi

receive buffer register are read out

Interrupt request
generation timing

Note 1: "n" denotes the value 00

to FF

that is set to the UART bit rate generator.

Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that

the UARTi receive interrupt request bit does not change.

Clock synchronous serial I/O mode

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Item

Specification

Select function

· CLK polarity selection

Whether transmit data is output/input timing at the rising edge or falling edge

of thetransfer clock can be selected

· LSB first/MSB first selection

Whether transmission/reception begins with bit 0 or bit 7 can be selected

· Continuous receive mode selection

Reception is enabled simultaneously by a read from the receive buffer register

· Transfer clock output from multiple pins selection (UART1)

UART1 transfer clock can be chosen by software to be output from one of

the two pins set

· Switching serial data logic (UART2)

Whether to reverse data in writing to the transmission buffer register or

reading the reception buffer register can be selected.

· TxD, RxD I/O polarity reverse (UART2)

This function is reversing TxD port output and RxD port input. All I/O data

level is reversed.

Table 1.15.3. Specifications of clock synchronous serial I/O mode (2)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Clock synchronous serial I/O mode

Figure 1.15.9. UARTi transmit/receive mode register in clock synchronous serial I/O mode

Symbol

Address

When reset

UiMR(i=0,1)

03A0

, 03A8

CKDIR

UARTi transmit/receive mode registers

Internal/external clock
select bit

STPS

PRY

PRYE

SLEP

0 : Internal clock
1 : External clock (Note)

Bit name

Function

Bit symbol

0 (Must always be "0" in clock synchronous serial I/O mode)

0 1

SMD0

SMD1

SMD2

Serial I/O mode select bit

0 0 1 : Clock synchronous serial

I/O mode

b2 b1 b0

Invalid in clock synchronous serial I/O mode

Symbol

Address

When reset

U2MR

0378

CKDIR

UART2 transmit/receive mode register

Internal/external clock
select bit

STPS

PRY

PRYE

IOPOL

0 : Internal clock
1 : External clock (Note2)

Bit name

Function

Bit symbol

0 1

SMD0

SMD1

SMD2

Serial I/O mode select bit

0 0 1 : Clock synchronous serial

I/O mode

b2 b1 b0

Invalid in clock synchronous serial I/O mode

TxD, RxD I/O polarity
reverse bit (Note1)

0 : No reverse
1 : Reverse

Note1 : Usually set to "0".
Note2 : Set the corresponding port direction register to "0".

Note : Set the corresponding port direction register to "0".

Clock synchronous serial I/O mode

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Table 1.15.4 lists the functions of the input/output pins during clock synchronous serial I/O mode. This

table shows the pin functions when the transfer clock output from multiple pins function is not selected.

Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi

pin outputs a "H". (If the N-channel open-drain is selected, this pin is in floating state.)

Table 1.15.4. Input/output pin functions in clock synchronous serial I/O mode

(when transfer clock output from multiple pins is not selected)

Pin name

Function

Method of selection

TxDi
(P6

, P6

, P7

)

Serial data output

Serial data input

Transfer clock output

Transfer clock input

Programmable I/O port

(Outputs dummy data when performing reception only)

RxDi
(P6

, P6

, P7

)

CLKi
(P6

, P6

, P7

)

Internal/external clock select bit (bit 3 at address 03A0

, 03A8

, 0378

) = "0"

Internal/external clock select bit (bit 3 at address 03A0

, 03A8

, 0378

) = "1"

Port P6

, P6

and P7

direction register (bits 1 and 5 at address 03EE

bit 2 at address 03EF

) = "0"

Port P6

, P6

and P7

direction register (bits 2 and 6 at address 03EE

bit 1 at address 03EF

)= "0"

(Can be used as an input port when performing transmission only)

CTS/RTS disable bit (bit 4 at address 03A4

, 03AC

, 037C

) ="0"

CTS/RTS function select bit (bit 2 at address 03A4

, 03AC

, 037C

) = "0"

Port P6

, P6

and P7

direction register (bits 0 and 4 at address 03EE

bit 3 at address 03EF

) = "0"

CTS/RTS disable bit (bit 4 at address 03A4

, 03AC

, 037C

16)

= "0"

CTS/RTS function select bit (bit 2 at address 03A4

, 03AC

, 037C

) = "1"

CTS/RTS disable bit (bit 4 at address 03A4

, 03AC

, 037C

) = "1"

CTS input

RTS output

CTSi/RTSi
(P6

, P6

, P7

)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Clock synchronous serial I/O mode

100

Figure 1.15.10. Typical transmit/receive timings in clock synchronous serial I/O mode

· Example of transmit timing (when internal clock is selected)

1 / f

EXT

Dummy data is set in UARTi transmit buffer register

Transmit enable
bit (TE)

Transmit buffer
empty flag (Tl)

CLKi

RxDi

Receive complete
flag (Rl)

RTSi

"H"

"L"

"0"

"1"

"0"

"1"

"0"

"1"

Receive enable
bit (RE)

"0"

"1"

Receive data is taken in

Transferred from UARTi transmit buffer register to UARTi transmit register

Read out from UARTi receive buffer register

The above timing applies to the following settings:
· External clock is selected.
· RTS function is selected.
· CLK polarity select bit = "0".

EXT

: frequency of external clock

Transferred from UARTi receive register

to UARTi receive buffer register

Receive interrupt
request bit (IR)

"0"

"1"

Shown in ( ) are bit symbols.

Meet the following conditions are met when the CLK
input before data reception = "H"
· Transmit enable bit "1"
· Receive enable bit "1"
· Dummy data write to UARTi transmit buffer register

Cleared to "0" when interrupt request is accepted, or cleared by software

· Example of receive timing (when external clock is selected)

CLK

Stopped pulsing because transfer enable bit = "0"

Data is set in UARTi transmit buffer register

Tc = TCLK = 2(n + 1) / fi

fi: frequency of BRGi count source (f

, f

)

n: value set to BRGi

Transfer clock

Transmit enable
bit (TE)

Transmit buffer
empty flag (Tl)

CLKi

TxDi

Transmit
register empty
flag (TXEPT)

"H"

"L"

"0"

"1"

"0"

"1"

"0"

"1"

CTSi

The above timing applies to the following settings:
· Internal clock is selected.
· CTS function is selected.
· CLK polarity select bit = "0".
· Transmit interrupt cause select bit = "0".

Transmit interrupt
request bit (IR)

"0"

"1"

Stopped pulsing because CTS = "H"

Transferred from UARTi transmit buffer register to UARTi transmit register

Shown in ( ) are bit symbols.

Cleared to "0" when interrupt request is accepted, or cleared by software

Clock synchronous serial I/O mode

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

101

(a) Polarity select function

As shown in Figure 1.15.11, the CLK polarity select bit (bit 6 at addresses 03A4

, 03AC

, 037C

)

allows selection of the polarity of the transfer clock.

· When CLK polarity select bit = "1"

Note 2: The CLK pin level when not

transferring data is "L".

CLK

· When CLK polarity select bit = "0"

Note 1: The CLK pin level when not

transferring data is "H".

CLK

Figure 1.15.11. Polarity of transfer clock

(b) LSB first/MSB first select function

As shown in Figure 1.15.12, when the transfer format select bit (bit 7 at addresses 03A4

, 03AC

037C

) = "0", the transfer format is "LSB first"; when the bit = "1", the transfer format is "MSB first".

Figure 1.15.12. Transfer format

LSB first

· When transfer format select bit = "0"

CLK

· When transfer format select bit = "1"

CLK

MSB first

Note: This applies when the CLK polarity select bit = "0".

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102

(c) Transfer clock output from multiple pins function (UART1)

This function allows the setting two transfer clock output pins and choosing one of the two to output a

clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B0

). (See Figure 1.15.3.)

The multiple pins function is valid only when the internal clock is selected for UART1. Note that when

_______ _______

this function is selected, UART1 CTS/RTS function cannot be used.

Figure 1.15.13. The transfer clock output from the multiple pins function usage

Microcomputer

(P6

)

CLKS

(P6

)

CLK

(P6

)

CLK

Note: This applies when the internal clock is selected and transmission

is performed only in clock synchronous serial I/O mode.

(d) Continuous receive mode

If the continuous receive mode enable bit (bits 2 and 3 at address 03B0

, bit 5 at address 037D

) is

set to "1", the unit is placed in continuous receive mode. In this mode, when the receive buffer register

is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to

the transmit buffer register back again.

(e) Serial data logic switch function (UART2)

When the data logic select bit (bit6 at address 037D

) = "1", and writing to transmit buffer register or

reading from receive buffer register, data is reversed. Figure 1.15.14 shows the example of serial data

logic switch timing.

Figure 1.15.14. Serial data logic switch timing

Transfer clock

TxD

(no reverse)

TxD

(reverse)

"H"

"L"

"H"

"L"

"H"

"L"

·When LSB first

Clock asynchronous serial I/O (UART) mode

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Item

Specification

Transfer data format

· Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected

· Start bit: 1 bit

· Parity bit: Odd, even, or nothing as selected

· Stop bit: 1 bit or 2 bits as selected

Transfer clock

· When internal clock is selected (bit 3 at addresses 03A0

, 03A8

, 0378

= "0") :

fi/16(n+1) (Note 1)

fi = f

, f

· When external clock is selected (bit 3 at addresses 03A0

, 03A8

="1") :

EXT

/16(n+1) (Note 1) (Note 2) (Do not set external clock for UART2)

Transmission/reception control

_______

CTS

function,

RTS

function,

CTS

and

RTS

function invalid: selectable

Transmission start condition

· To start transmission, the following requirements must be met:

- Transmit enable bit (bit 0 at addresses 03A5

, 03AD

, 037D

) = "1"

- Transmit buffer empty flag (bit 1 at addresses 03A5

, 03AD

, 037D

) = "0"

_______

- When CTS function selected, CTS input level = "L"

Reception start condition

· To start reception, the following requirements must be met:

- Receive enable bit (bit 2 at addresses 03A5

, 03AD

, 037D

) = "1"

- Start bit detection

Interrupt request

· When transmitting

generation timing

ransmit interrupt cause select bits (bits 0,1 at address 03B0

, bit4 at

address 037D

) = "0": Interrupts requested when data transfer from UARTi

transfer buffer register to UARTi transmit register is completed

- Transmit interrupt cause select bits (bits 0, 1 at address 03B0

, bit4 at

address 037D

) = "1": Interrupts requested when data transmission from

UARTi transfer register is completed

When receiving

- Interrupts requested when data transfer from UARTi receive register to

UARTi receive buffer register is completed

Error detection

· Overrun error (Note 3)

This error occurs when the next data is ready before contents of UARTi

receive buffer register are read out

· Framing error

This error occurs when the number of stop bits set is not detected

· Parity error

This error occurs when if parity is enabled, the number of 1's in parity and

character bits does not match the number of 1's set

· Error sum flag

This flag is set (= 1) when any of the overrun, framing, and parity errors is

encountered

(2) Clock asynchronous serial I/O (UART) mode

The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 1.15.5 and 1.15.6 list the specifications of the UART mode. Figure 1.15.15 shows
the UARTi transmit/receive mode register.

Table 1.15.5. Specifications of UART Mode (1)

Note 1: `n' denotes the value 00

to FF

that is set to the UARTi bit rate generator.

Note 2: f

EXT

is input from the CLKi pin.

Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that

the UARTi receive interrupt request bit does not change.

Clock asynchronous serial I/O (UART) mode

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Figure 1.15.15. UARTi transmit/receive mode register in UART mode

Symbol

Address

When reset

UiMR(i=0,1)

03A0

, 03A8

CKDIR

UARTi transmit / receive mode registers

Internal / external clock
select bit

STPS

PRY

PRYE

SLEP

0 : Internal clock
1 : External clock (Note)

Bit name

Function

Bit symbol

SMD0

SMD1

SMD2

Serial I/O mode select bit

b2 b1 b0

0 : One stop bit
1 : Two stop bits

0 : Parity disabled
1 : Parity enabled

0 : Sleep mode deselected
1 : Sleep mode selected

1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long

Valid when bit 6 = "1"
0 : Odd parity
1 : Even parity

Stop bit length select bit

Odd / even parity
select bit

Parity enable bit

Sleep select bit

Symbol

Address

When reset

U2MR

0378

CKDIR

UART2 transmit / receive mode register

Internal / external clock
select bit

STPS

PRY

PRYE

IOPOL

Must always be "0"

Bit name

Function

Bit symbol

SMD0

SMD1

SMD2

Serial I/O mode select bit

b2 b1 b0

0 : One stop bit
1 : Two stop bits

0 : Parity disabled
1 : Parity enabled

0 : No reverse
1 : Reverse

1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long

Valid when bit 6 = "1"
0 : Odd parity
1 : Even parity

Stop bit length select bit

Odd / even parity
select bit

Parity enable bit

TxD, RxD I/O polarity
reverse bit (Note)

Note : Usually set to "0".

Note : Set the corresponding port direction register to "0".

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Table 1.15.7 lists the functions of the input/output pins during UART mode. Note that for a period from

when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a "H". (If the N-

channel open-drain is selected, this pin is in floating state.)

Table 1.15.7. Input/output pin functions in UART mode

Pin name

Function

Method of selection

TxDi
(P6

, P6

, P7

)

Serial data output

Serial data input

Programmable I/O port

Transfer clock input

Programmable I/O port

RxDi
(P6

, P6

, P7

)

CLKi
(P6

, P6

, P7

)

Internal/external clock select bit (bit 3 at address 03A0

, 03A8

, 0378

) = "0"

Internal/external clock select bit (bit 3 at address 03A0

, 03A8

) = "1"

Port P6

, P6

direction register (bits 1 and 5 at address 03EE

) = "0"

(Do not set external clock for UART2)

Port P6

, P6

and P7

direction register (bits 2 and 6 at address 03EE

bit 1 at address 03EF

)= "0"

(Can be used as an input port when performing transmission only)

CTS/RTS disable bit (bit 4 at address 03A4

, 03AC

, 037C

) ="0"

CTS/RTS function select bit (bit 2 at address 03A4

, 03AC

, 037C

) = "0"

Port P6

, P6

and P7

direction register (bits 0 and 4 at address 03EE

bit 3 at address 03EF

) = "0"

CTS/RTS disable bit (bit 4 at address 03A4

, 03AC

, 037C

16)

= "0"

CTS/RTS function select bit (bit 2 at address 03A4

, 03AC

, 037C

) = "1"

CTS/RTS disable bit (bit 4 at address 03A4

, 03AC

, 037C

) = "1"

CTS input

RTS output

CTSi/RTSi
(P6

, P6

, P7

)

Clock asynchronous serial I/O (UART) mode

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Transmit enable
bit(TE)

Transmit buffer
empty flag(TI)

Transmit register
empty flag (TXEPT)

Start

bit

Parity

bit

TxDi

CTSi

The above timing applies to the following settings :
· Parity is enabled.
· One stop bit.
· CTS function is selected.
· Transmit interrupt cause select bit = "1".

"1"

"0"

"1"

"L"

"H"

"0"

"1"

Tc = 16 (n + 1) / fi or 16 (n + 1) / f

EXT

fi : frequency of BRGi count source (f

, f

)

EXT

: frequency of BRGi count source (external clock)

n : value set to BRGi

Transmit interrupt
request bit (IR)

"0"

"1"

Cleared to "0" when interrupt request is accepted, or cleared by software

Transmit enable
bit(TE)

Transmit buffer
empty flag(TI)

TxDi

Transmit register
empty flag (TXEPT)

"0"

"1"

"0"

"1"

"0"

"1"

The above timing applies to the following settings :
· Parity is disabled.
· Two stop bits.
· CTS function is disabled.
· Transmit interrupt cause select bit = "0".

Transfer clock

Tc = 16 (n + 1) / fi or 16 (n + 1) / f

EXT

fi : frequency of BRGi count source (f

, f

)

EXT

: frequency of BRGi count source (external clock)

n : value set to BRGi

Transmit interrupt
request bit (IR)

"0"

"1"

Shown in ( ) are bit symbols.

Transfer clock

Stopped pulsing because transmit enable bit = "0"

Stop

bit

Transferred from UARTi transmit buffer register to UARTi transmit register

Start

bit

The transfer clock stops momentarily as CTS is "H" when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTS changes to "L".

Data is set in UARTi transmit buffer register

SPSP

Transferred from UARTi transmit buffer register to UARTi transmit register

Stop

bit

Stop

bit

Data is set in UARTi transmit buffer register.

"0"

Cleared to "0" when interrupt request is accepted, or cleared by software

· Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)

· Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)

Figure 1.15.16. Typical transmit timings in UART mode (UART0,UART1)

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Clock asynchronous serial I/O (UART) mode

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Figure 1.15.17. Typical transmit timings in UART mode (UART2)

Start

bit

Parity

bit

Cleared to "0" when interrupt request is accepted, or cleared by software

Stop

bit

Data is set in UART2 transmit buffer register

Transferred from UART2 transmit buffer register to UARTi transmit register

Transmit enable
bit(TE)

Transmit buffer
empty flag(TI)

Transmit register
empty flag (TXEPT)

"0"

"1"

"0"

"1"

"0"

"1"

Transmit interrupt
request bit (IR)

"0"

"1"

Transfer clock

TxD

The above timing applies to the following settings :
· Parity is enabled.
· One stop bit.
· Transmit interrupt cause select bit = "1".

Tc = 16 (n + 1) / fi

fi : frequency of BRG2 count source (f

, f

)

n : value set to BRG2

Shown in ( ) are bit symbols.

Note

Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.

· Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)

Clock asynchronous serial I/O (UART) mode

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· Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)

Figure 1.15.18. Typical receive timing in UART mode

(a) Sleep mode (UART0, UART1)

This mode is used to transfer data between specific microcomputers among multiple microcomputers

connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses

03A0

, 03A8

) is set to "1" during reception. In this mode, the unit performs receive operation when

the MSB of the received data = "1" and does not perform receive operation when the MSB = "0".

Start bit

Sampled "L"

Receive data taken in

BRGi count
source

Receive enable bit

RxDi

Transfer clock

Receive
complete flag

RTSi

Stop bit

"1"

"0"

"1"

"H"

"L"

The above timing applies to the following settings :
·Parity is disabled.
·One stop bit.
·RTS function is selected.

Receive interrupt
request bit

"0"

"1"

Transferred from UARTi receive register to
UARTi receive buffer register

Reception triggered when transfer clock
is generated by falling edge of start bit

Cleared to "0" when interrupt request is accepted, or cleared by software

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Clock asynchronous serial I/O (UART) mode

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(b) Function for switching serial data logic (UART2)

When the data logic select bit (bit 6 of address 037D

) is assigned 1, data is inverted in writing to the

transmission buffer register or reading the reception buffer register. Figure 1.15.19 shows the ex-

ample of timing for switching serial data logic.

Figure 1.15.19. Timing for switching serial data logic

ST : Start bit
P : Even parity
SP : Stop bit

Transfer clock

TxD

(no reverse)

TxD

(reverse)

"H"

"L"

"H"

"L"

"H"

"L"

· When LSB first, parity enabled, one stop bit

(c) TxD, RxD I/O polarity reverse function (UART2)

This function is to reverse T

D pin output and R

D pin input. The level of any data to be input or output

(including the start bit, stop bit(s), and parity bit) is reversed. Set this function to "0" (not to reverse) for

usual use.

(d) Bus collision detection function (UART2)

This function is to sample the output level of the T

D pin and the input level of the R

D pin at the rising

edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.15.20

shows the example of detection timing of a bus collision (in UART mode).

Figure 1.15.20. Detection timing of a bus collision (in UART mode)

ST : Start bit
SP : Stop bit

Transfer clock

TxD

RxD

Bus collision detection

interrupt request signal

"H"

"L"

"H"

"L"

"H"

"L"

"1"

"0"

Bus collision detection

interrupt request bit

"1"

"0"

Clock asynchronous serial I/O (UART) mode

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111

Item

Specification

Transfer data format

· Transfer data 8-bit UART mode (bit 2 through bit 0 of address 0378

= "101

· One stop bit (bit 4 of address 0378

= "0")

· With the direct format chosen

Set parity to "even" (bit 5 and bit 6 of address 0378

= "1" and "1" respectively)

Set data logic to "direct" (bit 6 of address 037D

= "0").

Set transfer format to LSB (bit 7 of address 037C

= "0").

· With the inverse format chosen

Set parity to "odd" (bit 5 and bit 6 of address 0378

= "0" and "1" respectively)

Set data logic to "inverse" (bit 6 of address 037D

= "1")

Set transfer format to MSB (bit 7 of address 037C

= "1")

Transfer clock

· With the internal clock chosen (bit 3 of address 0378

= "0") : fi / 16 (n + 1) (Note 1) : fi=f

, f

(Do not set external clock)

Transmission / reception control

_______

· Disable the CTS and RTS function (bit 4 of address 037C

= "1")

Other settings

· The sleep mode select function is not available for UART2

· Set transmission interrupt factor to "transmission completed" (bit 4 of address 037D

= "1")

Transmission start condition · To start transmission, the following requirements must be met:

- Transmit enable bit (bit 0 of address 037D

) = "1"

- Transmit buffer empty flag (bit 1 of address 037D

) = "0"

Reception start condition

· To start reception, the following requirements must be met:

- Reception enable bit (bit 2 of address 037D

) = "1"

- Detection of a start bit

· When transmitting

When data transmission from the UART2 transfer register is completed

(bit 4 of address 037D

= "1")

· When receiving

When data transfer from the UART2 receive register to the UART2 receive

buffer register is completed

Error detection

· Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2)

· Framing error (see the specifications of clock-asynchronous serial I/O)

· Parity error (see the specifications of clock-asynchronous serial I/O)

- On the reception side, an "L" level is output from the T

pin by use of the parity error

signal output function (bit 7 of address 037D

= "1") when a parity error is detected

- On the transmission side, a parity error is detected by the level of input to

the R

pin when a transmission interrupt occurs

· The error sum flag (see the specifications of clock-asynchronous serial I/O)

(3) Clock-asynchronous serial I/O mode (compliant with the SIM interface)

The SIM interface is used for connecting the microcomputer with a memory card or the like; adding some

extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table

1.15.8 shows the specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface).

Interrupt request

generation timing

Note 1: `n' denotes the value 00

to FF

that is set to the UART2 bit rate generator.

Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also

that the UART2 receive interrupt request bit does not change.

Table 1.15.8. Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface)

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Clock asynchronous serial I/O (UART) mode

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Figure 1.15.21. Typical transmit/receive timing in UART mode (compliant with the SIM interface)

Transmit enable
bit(TE)

Transmit buffer
empty flag(TI)

Transmit register
empty flag (TXEPT)

Start

bit

Parity

bit

The above timing applies to the following settings :
· Parity is enabled.
· One stop bit.
· Transmit interrupt cause select bit = "1".

"0"

"1"

"0"

"1"

"0"

"1"

Tc = 16 (n + 1) / fi

fi : frequency of BRG2 count source (f

, f

)

n : value set to BRG2

Transmit interrupt
request bit (IR)

"0"

"1"

Shown in ( ) are bit symbols.

Transfer clock

Stop

bit

Data is set in UART2 transmit buffer register

A "L" level returns from TxD

due to

the occurrence of a parity error.

The level is detected by the
interrupt routine.

The level is
detected by the
interrupt routine.

Receive enable
bit (RE)

Receive complete
flag (RI)

Start

bit

Parity

bit

RxD

The above timing applies to the following settings :
· Parity is enabled.
· One stop bit.
· Transmit interrupt cause select bit = "0".

"0"

"1"

"0"

"1"

Tc = 16 (n + 1) / fi

fi : frequency of BRG2 count source (f

, f

)

n : value set to BRG2

Receive interrupt
request bit (IR)

"0"

"1"

Shown in ( ) are bit symbols.

Transfer clock

Stop

bit

A "L" level returns from TxD

due to

the occurrence of a parity error.

TxD

Read to receive buffer

Signal conductor level
(Note 2)

TxD

RxD

Signal conductor level
(Note 2)

Note 1 : The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Note 2 : Equal in waveform because TxD

and RxD

are connected.

Transferred from UART2 transmit buffer register to UART2 transmit register

Cleared to "0" when interrupt request is accepted, or cleared by software

Note 1

Clock asynchronous serial I/O (UART) mode

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113

(a) Function for outputting a parity error signal

With the error signal output enable bit (bit 7 of address 037D

) assigned "1", you can output an "L"

level from the TxD

pin when a parity error is detected. In step with this function, the generation timing

of a transmission completion interrupt changes to the detection timing of a parity error signal. Figure

1.15.22 shows the output timing of the parity error signal.

Figure 1.15.22. Output timing of the parity error signal

ST : Start bit
P : Even Parity
SP : Stop bit

Hi-Z

Transfer

clock

RxD

TxD

Receive

complete flag

"H"

"L"

"H"

"L"

"H"

"L"

"1"

· LSB first

"0"

(b) Direct format/inverse format

Connecting the SIM card allows you to switch between direct format and inverse format. If you choose

the direct format, D

data is output from TxD

. If you choose the inverse format, D

data is inverted

and output from TxD

Figure 1.15.23 shows the SIM interface format.

Figure 1.15.23. SIM interface format

P : Even parity

Transfer

clcck

TxD

(direct)

TxD

(inverse)

UART2 Special Mode Register

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UART2 Special Mode Register

The UART2 special mode register (address 0377

) is used to control UART2 in various ways.

Figure 1.15.25 shows the UART2 special mode register.

UART2 special mode register

Symbol

Address

When reset

U2SMR

0377

b6 b5

Bit name

Bit

symbol

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

ABSCS

ACSE

SSS

I C mode selection bit

Bus busy flag

0 : STOP condition detected
1 : START condition detected

SCLL sync output
enable bit

Bus collision detect
sampling clock select bit

Arbitration lost detecting
flag control bit

0 : Normal mode
1 : I C mode

0 : Update per bit
1 : Update per byte

IICM

ABC

BBS

LSYN

0 : Ordinary
1 : Falling edge of RxD2

0 : Disabled
1 : Enabled

Transmit start condition
select bit

Must always be "0"

0 : Rising edge of transfer

clock

1 : Underflow signal of timer A0

Auto clear function
select bit of transmit
enable bit

0 : No auto clear function
1 : Auto clear at occurrence of

bus collision

Must always be "0"

Note: Nothing but "0" may be written.

(Note)

Reserved bit

Must always be set to "0"

Figure 1.15.25. UART2 special mode register

Function

Normal mode

C mode (Note 1)

Factor of interrupt number 15 (Note 2)

UART2 transmission

No acknowledgment detection (NACK)

Factor of interrupt number 16 (Note 2)

UART2 reception

Start condition detection or stop
condition detection

UART2 transmission output delay

Not delayed

Delayed

at the time when UART2 is in use

TxD

(output)

SDA (input/output) (Note 3)

at the time when UART2 is in use

RxD

(input)

SCL (input/output)

at the time when UART2 is in use

CLK

DMA1 factor at the time when 1 1 0 1 is assigned
to the DMA request factor selection bits

UART2 reception

Must not be set

Noise filter width

15ns

50ns

Reading P7

Reading the terminal when 0 is
assigned to the direction register

Reading the terminal regardless of the
value of the direction register

Note 1: Make the settings given below when I

C mode is in use.

Set 0 1 0 in bits 2, 1, 0 of the UART2 transmission/reception mode register.
Disable the RTS/CTS function. Choose the MSB First function.

Note 2: Follow the steps given below to switch from a factor to another.

1. Disable the interrupt of the corresponding number.
2. Switch from a factor to another.
3. Reset the interrupt request flag of the corresponding number.
4. Set an interrupt level of the corresponding number.

Note 3: Set an initial value of SDA transmission output when serial I/O is invalid.

Factor of interrupt number 10 (Note 2)

Bus collision detection

Acknowledgment detection (ACK)

Initial value of UART2 output

H level (when 0 is assigned to
the CLK polarity select bit)

The value set in latch P7

when the port is

selected

Table 1.15.9. Features in I

C mode

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UART2 Special Mode Register

116

Figure 1.15.26 shows the functional block diagram for I

C mode. Setting "1" in the I

C mode selection bit

(IICM) causes ports P7

, P7

, and P7

to work as data transmission-reception terminal SDA, clock input-

output terminal SCL, and port P7

respectively. A delay circuit is added to the SDA transmission output,

so the SDA output changes after SCL fully goes to "L". An attempt to read Port P7

(SCL) results in

getting the terminal's level regardless of the content of the port direction register. The initial value of SDA

transmission output in this mode goes to the value set in port P7

. The interrupt factors of the bus collision

detection interrupt, UART2 transmission interrupt, and of UART2 reception interrupt turn to the start/stop

condition detection interrupt, acknowledgment non-detection interrupt, and acknowledgment detection

interrupt respectively.

The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA

terminal (P7

) is detected with the SCL terminal (P7

) staying "H". The stop condition detection interrupt

refers to the interrupt that occurs when the rising edge of the SDA terminal (P7

) is detected with the SCL

terminal (P7

) staying "H". The bus busy flag (bit 2 of the UART2 special mode register) is set to "1" by the

start condition detection, and set to "0" by the stop condition detection.

In the first place, the control bits related to the I

C bus (simplified I

C bus) interface are explained.

Bit 0 of the UART special mode register (0377

) is used as the I

C mode selection bit.

Setting "1" in the I

C mode select bit (bit 0) goes the circuit to achieve the I

C bus (simplified I

C bus)

interface effective.

Table 1.15.9 shows the relation between the I

C mode select bit and respective control workings.

Since this function uses clock-synchronous serial I/O mode, set this bit to "0" in UART mode.

through P7

conforming to the simplified I C bus

Selector

I/O

Timer

delay

Noize

Filter

Timer

UART2

Selector

(Port P7

output data latch)

I/O

/TxD

/SDA

/RxD

/SCL

Reception register

CLK

Internal clock

UART2

External clock

Selector

UART2

I/O

Timer

/CLK

Arbitration

Start condition detection

Stop condition detection

Data bus

Falling edge
detection

NACK

ACK

UART2

UART2 transmission/
NACK interrupt
request

UART2 reception/ACK
interrupt request
DMA1 request

9th pulse

IICM=1

IICM=0

IICM=1

IICM=0

IICM=1

IICM=0

IICM=1

IICM=0

IICM=1

IICM=0

Port reading

With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P7

of the direction register.

L-synchronous
output enabling bit

R Q

Bus busy

IICM=1

IICM=0

Bus collision/start, stop
condition detection
interrupt request

Bus collision
detection

Noize
Filter

Transmission
register

To DMA0, DMA1

Noize

Filter

To DMA0

Figure 1.15.26. Functional block diagram for I

C mode

UART2 Special Mode Register

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M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

117

The acknowledgment non-detection interrupt refers to the interrupt that occurs when the SDA terminal

level is detected still staying "H" at the rising edge of the 9th transmission clock. The acknowledgment

detection interrupt refers to the interrupt that occurs when SDA terminal's level is detected already went

to "L" at the 9th transmission clock. Bit 1 of the UART2 special mode register (0377

) is used as the

arbitration lost detecting flag control bit. Arbitration means the act of detecting the nonconformity between

transmission data and SDA terminal data at the timing of the SCL rising edge. This detecting flag is

located at bit 3 of the UART2 reception buffer register (037F

), and "1" is set in this flag when nonconfor-

mity is detected. Use the arbitration lost detecting flag control bit to choose which way to use to update

the flag, bit by bit or byte by byte. When setting this bit to "1" and updated the flag byte by byte if noncon-

formity is detected, the arbitration lost detecting flag is set to "1" at the falling edge of the 9th transmission

clock.

If update the flag byte by byte, must judge and clear ("0") the arbitration lost detecting flag after complet-

ing the first byte acknowledge detect and before starting the next one byte transmission.

Bit 3 of the UART2 special mode register is used as SCL- and L-synchronous output enable bit. Setting

this bit to "1" goes the P7

data register to "0" in synchronization with the SCL terminal level going to "L".

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

UART2 Special Mode Register

118

1. Bus collision detect sampling clock select bit (Bit 4 of the UART2 special mode register)

0: Rising edges of the transfer clock

CLK

Timer A0

1: Timer A0 overflow

2. Auto clear function select bit of transmt enable bit (Bit 5 of the UART2 special mode register)

CLK

TxD/RxD

Bus collision
detect interrupt
request bit

Transmit
enable bit

3. Transmit start condition select bit (Bit 6 of the UART2 special mode register)

CLK

TxD

Enabling transmission

CLK

TxD

RxD

With "1: falling edge of RxD

" selected

0: In normal state

TxD/RxD

Figure 1.15.27. Some other functions added

Some other functions added are explained here. Figure 1.15.27 shows their workings.

Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock select bit. The

bus collision detect interrupt occurs when the RxD

level and TxD

level do not match, but the nonconfor-

mity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to "0". If

this bit is set to "1", the nonconformity is detected at the timing of the overflow of timer A0 rather than at

the rising edge of the transfer clock.

Bit 5 of the UART2 special mode register is used as the auto clear function select bit of transmit enable

bit. Setting this bit to "1" automatically resets the transmit enable bit to "0" when "1" is set in the bus

collision detect interrupt request bit (nonconformity).

Bit 6 of the UART2 special mode register is used as the transmit start condition select bit. Setting this bit

to "1" starts the TxD transmission in synchronization with the falling edge of the RxD terminal.

UART2 Special Mode Register 2

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

119

UART2 Special Mode Register 2

UART2 special mode register 2 (address 0376

) is used to further control UART2 in I

C mode. Figure

1.15.28 shows the UART2 special mode register 2.

UART2 special mode register 2

Symbol

Address

When reset

U2SMR2

0376

b6 b5

Bit name

Bit

symbol

Function

STAC

SWC2

SDHI

I C mode selection bit 2

SCL wait output bit

0 : Disabled
1 : Enabled

SDA output stop bit

UART2 initialization bit

Clock-synchronous bit

Refer to Table 1.15.10

0 : Disabled
1 : Enabled

IICM2

CSC

SWC

ASL

0 : Disabled
1 : Enabled

SDA output disable bit

SCL wait output bit 2

0: Enabled
1: Disabled (high impedance)

0 : Disabled
1 : Enabled

0: UART2 clock
1: 0 output

SHTC

Start/stop condition
control bit

Set this bit to "1" in I

C mode

(refer to Table 1.15.11)

Figure 1.15.28. UART2 special mode register 2

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M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

UART2 Special Mode Register 2

120

Bit 0 of the UART2 special mode register 2 (address 0376

) is used as the I

C mode selection bit 2.

Table 1.15.10 shows the types of control to be changed by I

C mode selection bit 2 when the I

C mode

selection bit is set to "1". Table 1.15.11 shows the timing characteristics of detecting the start condition

and the stop condition. Set the start/stop condition control bit (bit 7 of UART2 special mode register 2) to

"1" in I

C mode.

Function

IICM2 = 1

IICM2 = 0

Factor of interrupt number 15

No acknowledgment detection (NACK)

UART2 transmission (the rising edge
of the final bit of the clock)

Factor of interrupt number 16

Acknowledgment detection (ACK)

UART2 reception (the falling edge
of the final bit of the clock)

DMA1 factor at the time when 1 1 0 1
is assigned to the DMA request
factor selection bits

Must not be set

UART2 reception (the falling edge of
the final bit of the clock)

Timing for transferring data from the
UART2 reception shift register to the
reception buffer.

The rising edge of the final bit of the
reception clock

The falling edge of the final bit of the
reception clock

Timing for generating a UART2
reception/ACK interrupt request

The rising edge of the final bit of the
reception clock

The falling edge of the final bit of the
reception clock

3 to 6 cycles < duration for setting-up (Note2)

3 to 6 cycles < duration for holding (Note2)

Note 1 : When the start/stop condition count bit is "1" .
Note 2 : "cycles" is in terms of the input oscillation frequency f(X

) of the main clock.

Duration for

setting up

Duration for

holding

SCL

SDA

(Start condition)

SDA

(Stop condition)

Table 1.15.10. Functions changed by I

C mode selection bit 2

Table 1.15.11. Timing characteristics of detecting the start condition and the stop condition(Note1)

UART2 Special Mode Register 2

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M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

121

IICM=1
and IICM2=0

IICM=0
or
IICM2=1

IICM=0
or IICM2=1

To DMA0, DMA1

To DMA0

I/0

Noize
Filter

/RXD

/SCL

Reception register

CLK
control

UART2

Noize
Filter

UART2

/CLK

UART2

IICM=1

IICM=0

IICM=1

IICM=0

SWC

Falling of 9th pulse

SWC2

Start condition detection

Stop condition detection

Falling edge
detection

L-synchronous
output enabling bit

Data register

Selector

Internal clock

External clock

Selector

I/0

Timer

Port reading

Bus
busy

UART2 transmission/
NACK interrupt
request

UART2 reception/ACK interrupt request
DMA1 request

NACK

ACK

IICM=1

IICM=0

With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P7

of the direction register.

Bus collision
detection

9th pulse

Bus collision/start, stop condition detection
interrupt request

I/0

delay

Noize
Filter

UART2

/TXD

/SDA

UART2

IICM=1

IICM=0

ALS

SDHI

Selector

Timer

Arbitration

Transmission register

Functions available in I

C mode are shown in Figure 1.15.29 -- a functional block diagram.

Bit 3 of the UART2 special mode register 2 (address 0376

) is used as the SDA output stop bit. Setting

this bit to "1" causes an arbitration loss to occur, and the SDA pin turns to high-impedance state at the

instant when the arbitration lost detectng flag is set to "1".

Bit 1 of the UART2 special mode register 2 (address 0376

) is used as the clock synchronization bit.

With this bit set to "1" at the time when the internal SCL is set to "H", the internal SCL turns to "L" if the

falling edge is found in the SCL pin; and the baud rate generator reloads the set value, and start counting

within the "L" interval. When the internal SCL changes from "L" to "H" with the SCL pin set to "L", stops

counting the baud rate generator, and starts counting it again when the SCL pin turns to "H". Due to this

function, the UART2 transmission-reception clock becomes the logical product of the signal flowing

through the internal SCL and that flowing through the SCL pin. This function operates over the period

from the moment earlier by a half cycle than falling edge of the UART2 first clock to the rising edge of the

ninth bit. To use this function, choose the internal clock for the transfer clock.

Bit 2 of the UART2 special mode register 2 (0376

) is used as the SCL wait output bit. Setting this bit to

"1" causes the SCL pin to be fixed to "L" at the falling edge of the ninth bit of the clock. Setting this bit to

"0" frees the output fixed to "L".

Figure 1.15.29. Functional block diagram for I

C mode

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

UART2 Special Mode Register 2

122

Bit 4 of the UART2 special mode register 2 (address 0376

) is used as the UART2 initialization bit.

Setting this bit to "1", and when the start condition is detected, the microcomputer operates as follows.

(1) The transmission shift register is initialized, and the content of the transmission register is transferred

to the transmission shift register. This starts transmission by dealing with the clock entered next as the

first bit. The UART2 output value, however, doesn't change until the first bit data is output after the

entrance of the clock, and remains unchanged from the value at the moment when the microcomputer

detected the start condition.

(2) The reception shift register is initialized, and the microcomputer starts reception by dealing with the

clock entered next as the first bit.

(3) The SCL wait output bit turns to "1". This turns the SCL pin to "L" at the falling edge of the ninth bit of

the clock.

Starting to transmit/receive signals to/from UART2 using this function doesn't change the value of the

transmission buffer empty flag. To use this function, choose the external clock for the transfer clock.

Bit 5 of the UART2 special mode register 2 (0376

) is used as the SCL pin wait output bit 2. Setting this

bit to "1" with the serial I/O specified allows the user to forcibly output an "L" from the SCL pin even if

UART2 is in operation. Setting this bit to "0" frees the "L" output from the SCL pin, and the UART2 clock

is input/output.

Bit 6 of the UART2 special mode register 2 (0376

) is used as the SDA output disable bit. Setting this bit

to "1" forces the SDA pin to turn to the high-impedance state. Refrain from changing the value of this bit

at the rising edge of the UART2 transfer clock. There can be instances in which arbitration lost detectng

flag is turned on.

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M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

LCD Drive Control Circuit

123

Table 1.16.1. Maximum number of display pixels at each duty ratio

LCD Drive Control Circuit

The M30220 group has the built-in Liquid Crystal Display (LCD) drive control circuit consisting of the following.

LCD display RAM

Segment output enable register

LCD mode register

Charge-pump

Selector

Timing controller

Common driver

Segment driver

Bias control circuit

A maximum of 48 segment output pins and 4 common output pins can be used.

Up to 192 pixels can be controlled for LCD display. When the LCD enable bit is set to "1" after data is set in

the LCD mode register, the segment output enable register and the LCD display RAM, the LCD drive control

circuit starts reading the display data automatically, performs the bias control and the duty ratio control, and

displays the data on the LCD panel. When using the output port function, write data into the LCD display

RAM while the time division select bit are "00" and the LCD output enable bit is "0", and if the LCDRAM

output bit is set to "1", the SEG

- SEG

pin and the pin which are selected as segment output by the

segment output enable register will respectively output the contents of the bit corresponds to the COM

LCD display RAM.

Table 1.16.1 shows maximum number of display pixels at each duty ratio. Figure 1.16.1 shows the block

diagram of LCD controller / driver.

Duty ratio

Maximum number of display pixel

96 dots or 8 segment LCD 12 digits

144 dots or 8 segment LCD 18 digits

192 dots or 8 segment LCD 24 digits

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M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

LCD Drive Control Circuit

124

Figure 1.16.1. Block diagram of LCD controller/driver

Data bus low-order bits

Timing controller

1/8

COM

SEG

Address 0100

Address 0101

LCDCK

LCDCK count source

select bit

Bias control bit

LCD enable bit

Duty ratio select bits

Selector

LCD display

RAM

Address 0117

/SEG

Level

shift

Level

shift

Level

shift

Level

shift

Level

shift

Level

shift

Common

driver

Common

driver

Common

driver

Common

driver

Charge-pump

control bit

Level

Shift

Level

Shift

Level

Shift

Level

Shift

Segment

driver

Segment

driver

Segment

driver

Segment

driver

Segment

driver

Segment

driver

Bias control

Data bus high-order bits

LCD output

enable bit

1/2

LCD frame frequency control counter (8)

"0"

"1"

Reload register (8)

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

LCD Drive Control Circuit

125

Figure 1.16.2. LCD-related registers

LCD frame frequency counter (Note)

Symbol

Address

When reset

LCDTIM

0124

Function

8 bits timer

to FF

Values that can be set

Segment output enable register

Symbol

Address

When reset

SEG

0122

Bit name

Function

Bit symbol

SEGO0

Segment output enable
bit 0

0 : I/O ports P11

to P11

1 :

Segment output SEG

to SEG

SEGO1

Segment output enable
bit 1

0 : I/O ports P11

, P11

1 :

Segment output SEG

SEG

SEGO2

Segment output enable
bit 2

0 : I/O ports P11

1 :

Segment output SEG

SEGO3

Segment output enable
bit 3

0 : I/O ports P12

to P12

1 :

Segment output SEG

to SEG

SEGO4

Segment output enable
bit 4

0 : I/O ports P12

, P12

1 :

Segment output SEG

, SEG

SEGO5

Segment output enable
bit 5

0 : I/O ports P10

to P10

1 :

Segment output SEG

to SEG

SEGO6

Segment output enable
bit 6

0 : I/O ports P0

to P0

1 :

Segment output SEG

to SEG

SEGO7

0 : disable
1 : enable

LCD output enable bit

Note 1: LCDCK is a clock for a LCD timing controller.
Note 2: When the Charge-pump is enabled, set "0" to the bias control bit
without fail.

LCD mode register

Symbol

Address

When reset

LCDM

0120

0X000000

Bit name

Function

Bit symbol

0 0 : Output port
0 1 : 2 duty (use COM

, COM

)

1 0 : 3 duty (use COM

COM

)

1 1 : 4 duty (use COM

COM

)

b1 b0

PUMP

LCDEN

LCDT1

BIAS

LCDT0

Bias control bit

0 : 1/3 bias
1 : 1/2 bias

LCD enable bit

0 : LCD OFF
1 : LCD ON

Charge-pump
control bit

0 : Charge-pump disable
1 : Charge-pump enable(Note2)

LCDCK count source
select bit (Note 1)

0 : f

1 : f

LSRC

LRAMOUT

LCDRAM output bit

0 : LCD waveform output
1 : LCDRAM data output

Duty ratio select bit

Nothing is assigned.
In an attempt to write to this bit, write "0". The value, if read, turns out to be
indeterminate.

Note: Set this register when LCD output enable bit is "0" (disable).

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

LCD Drive Control Circuit

126

Charge-pump

The charge-pump performs threefold boosting. This circuit inputs a reference voltage for boosting from

LCD power input pin V

To activate the charge-pump, by the segment output enable register and the LCD mode register, choose

the segment/port, select the time division and the bias control, and set up the LCD frame frequency

counter, and select the count source for LCDCK, then set the LCD output enable bit (bit 7 at the address

0122

) to "enable", apply a voltage equal to or greater than 1.3 V but not exceeding 2.1 V to the V

pin,

after that, set the charge-pump control bit (bit 4 at address 0120

) to "step up enabled". However, set the

bias control to "1/3 bias" without fail.

When using the charge-pump, a voltage that is twice as large as V

occurs at V

pin, and a voltage that

is three times as large as V

occurs at the V

pin.

The charge-pump control bit (bit 4 of the address 0120

) controls the charge-pump.

When not using the charge-pump, enable the LCD output enable bit and apply an appropriate voltage to

the LCD power supply input pins (V

to V

). When the LCD output enable bit is disabled, the V

pin is

connected to V

internally.

Bias Control and Applied Voltage to LCD Power Input Pins

To the LCD power input pins (V

to V

), apply the voltage shown in Table 1.16.2 according to the bias value.

Select a bias value by the bias control bit (bit 2 of the address 0120

Table 1.16.2. Bias control and applied voltage to V

to V

Bias value

Voltage value

= V

LCD

1/3 bias

= 2/3 V

LCD

= 1/3 V

LCD

1/2 bias

= V

LCD

= V

= 1/2 V

LCD

Note : V

LCD

is the maximum value of supplied voltage for the LCD panel.

Figure 1.16.3. Example of circuit at each bias

1/3 bias
when using the charge-pump

1/3 bias
when not using the charge-pump

Open

R1=R2=R3

Contrast control

1/2 bias

Open

R4=R5

Contrast control

When selecting output port function
(not using LCD panel)

Open

LCD

When not using the charge-pump

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

LCD Drive Control Circuit

127

Common Pin and Duty Ratio Control

The common pins (COM

to COM

) to be used are determined by duty ratio.

Select duty ratio by the duty ratio select bits (bits 0 and 1 of address 0120

LCD Display RAM

Address 0100

to 0117

is the designated RAM for the LCD display. When "1" are written to these

addresses, the corresponding segments of the LCD display panel are turned on.

Figure 1.16.4 shows the LCD display RAM map.

Table 1.16.3. Duty ratio control and common pins used

Duty

Duty ratio select bit

Common pins used

ratio

Bit 1

Bit 0

COM

, COM

(Note 1)

COM

to COM

(Note 2)

COM

to COM

LCD Drive Timing

The LCDCK timing frequency (LCD drive timing) is generated internally and the frame frequency can be

determined with the following equation. The LCDCK count source frequency is f

(same frequency as

CIN

) or f

(divide-by-32 of X

frequency).

Figure 1.16.4. LCD display RAM map

Note 1 : COM

and COM

are open.

Note 2 : COM

is open.

0106

0107

0108

0109

010A

010B

010C

010D

010E

010F

SEG

Bit

Address

0100

0101

0102

0103

0104

0105

SEG

0110

0111

0112

0113

SEG

0114

0115

0116

0117

SEG

COM

16 X (LCD frame frequency count value + 1)

f(LCDCK)=

f(LCDCK)

duty ratio

Frame frequency=

(frequency of count source for LCDCK)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A-D Converter

130

Item

Performance

Method of A-D conversion Successive approximation (capacitive coupling amplifier)

Analog input voltage (Note 1) 0V to AV

)

Operating clock

(Note 2) V

= 4.0 to 5.5V f

/divide-by-2 of f

/divide-by-4 of f

, f

=f(X

)

= 2.7 to 4.0V divide-by-2 of f

/divide-by-4 of f

, f

=f(X

)

Resolution

8-bit or 10-bit (selectable)

Absolute precision

= 5V

· Without sample and hold function

3LSB

· With sample and hold function (8-bit resolution)

2LSB

· With sample and hold function (10-bit resolution)

3LSB

= 3V

· Without sample and hold function (8-bit resolution)

2LSB

Operating modes

One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,

and repeat sweep mode 1

Analog input pins

8pins (AN

to AN

)

A-D conversion start condition · Software trigger

A-D conversion starts when the A-D conversion start flag changes to "1"

· External trigger (can be retriggered)

A-D conversion starts when the A-D conversion start flag is "1" and the

___________

TRG

/P13

input changes from "H" to "L"

Conversion speed per pin · Without sample and hold function

8-bit resolution: 49

cycles, 10-bit resolution: 59

cycles

· With sample and hold function

8-bit resolution: 28

cycles, 10-bit resolution: 33

cycles

A-D Converter

The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling

amplifier. Pins P9

to P9

also function as the analog signal input pins. The direction registers of these pins for A-

D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D7

) can be used to isolate

the resistance ladder of the A-D converter from the reference voltage input pin (V

REF

) when the A-D converter is not

used. Doing so stops any current flowing into the resistance ladder from V

REF

, reducing the power dissipation.

When using the A-D converter, start A-D conversion only after setting bit 5 of 03D7

to connect V

REF

The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low

8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low

8 bits are stored in the even addresses.

Table 1.17.1 shows the performance of the A-D converter. Figure 1.17.1 shows the block diagram of the

A-D converter, and Figures 1.17.2 and 1.17.3 show the A-D converter-related registers.

Note 1: Does not depend on use of sample and hold function.

Note 2: Without sample and hold function, set the

frequency to 250kH

min.

With the sample and hold function, set the

frequency to 1MH

min.

Table 1.17.1. Performance of A-D converter

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A-D Converter

131

Figure 1.17.1. Block diagram of A-D converter

1/2

A-D conversion rate
selection

(03C1

, 03C0

)

(03C3

, 03C2

)

(03C5

, 03C4

)

(03C7

, 03C6

)

(03C9

, 03C8

)

(03CB

, 03CA

)

(03CD

, 03CC

)

(03CF

, 03CE

)

CKS1=1

CKS0=0

A-D register 0(16)

A-D register 1(16)
A-D register 2(16)

A-D register 3(16)

A-D register 4(16)

A-D register 5(16)

A-D register 6(16)

A-D register 7(16)

Resistor ladder

Successive conversion register

/AN

A-D control register 0 (address 03D6

)

A-D control register 1 (address 03D7

)

ref

Data bus high-order

Data bus low-order

REF

/AN

ADGSEL0 = 0

VCUT=0

VCUT=1

CKS0=1

CKS1=0

CH2,CH1,CH0=000

CH2,CH1,CH0=001

CH2,CH1,CH0=010

CH2,CH1,CH0=011

CH2,CH1,CH0=100

CH2,CH1,CH0=101

CH2,CH1,CH0=110

CH2,CH1,CH0=111

Decoder

Comparator

Addresses

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A-D Converter

132

Figure 1.17.2. A-D converter-related registers (1)

A-D control register 0 (Note 1)

Symbol

Address

When reset

ADCON0

03D6

00000XXX

Analog input pin select bit

0 0 0 : AN

is selected

0 0 1 : AN

is selected

0 1 0 : AN

is selected

0 1 1 : AN

is selected

1 0 0 : AN

is selected

1 0 1 : AN

is selected

1 1 0 : AN

is selected

1 1 1 : AN

is selected

(Note 2)

CH0

Bit symbol

Bit name

Function

CH1

CH2

A-D operation mode
select bit 0

0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0

Repeat sweep mode 1

(Note 2)

MD0

MD1

Trigger select bit

0 : Software trigger
1 : AD

TRG

trigger

TRG

ADST

A-D conversion start flag

0 : A-D conversion disabled
1 : A-D conversion started

Frequency select bit 0

0 : f

/4 is selected

1 : f

/2 is selected

CKS0

A-D control register 1 (Note)

Symbol Address

When

reset

ADCON1

03D7

Bit name

Function

Bit symbol

A-D sweep pin select bit

SCAN0

SCAN1

MD2

BITS

8/10-bit mode select bit

0 : 8-bit mode
1 : 10-bit mode

VCUT

Vref connect bit

A-D operation mode
select bit 1

0 : Any mode other than repeat sweep

mode 1

1 : Repeat sweep mode 1

0 : Vref not connected
1 : Vref connected

b2 b1 b0

b4 b3

When single sweep and repeat sweep
mode 0 are selected

0 0 : AN

, AN

(2 pins)

0 1 : AN

to AN

(4 pins)

1 0 : AN

to AN

(6 pins)

1 1 : AN

to AN

(8 pins)

b1 b0

When repeat sweep mode 1 is selected

0 0 : AN

(1 pin)

0 1 : AN

, AN

(2 pins)

1 0 : AN

to AN

(3 pins)

1 1 : AN

to AN

(4 pins)

b1 b0

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is

indeterminate.

Note 2: When changing A-D operation mode, set analog input pin again.

Frequency select bit 1

0 : f

/2 or f

/4 is selected

1 : f

is selected

CKS1

Note: If the A-D control register is rewritten during A-D conversion, the conversion result is

indeterminate.

0 0

Reserved bit

Must always be set to "0"

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A-D Converter

133

Figure 1.17.3. A-D converter-related registers (2)

A-D control register 2 (Note)

Symbol

Address

When reset

ADCON2

03D4

0000XXX0

A-D conversion method
select bit

0 : Without sample and hold
1 : With sample and hold

Bit symbol

Bit name

Function

R W

Note: If the A-D control register is rewritten during A-D conversion, the conversion

result is indeterminate.

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to
be "0".

A-D register i

Symbol

Address

When reset

ADi(i=0 to 7)

03C0

to 03CF

Indeterminate

Eight low-order bits of A-D conversion result

Function

R W

(b15)

(b8)

· During 10-bit mode

Two high-order bits of A-D conversion result

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if
read, turns out to be "0".

· During 8-bit mode

When read, the content is indeterminate

SMP

Reserved bit

0 0 0

Must always be set to "0"

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A-D Converter

134

(1) One-shot mode

In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conver-

sion. Table 1.17.2 shows the specifications of one-shot mode. Figure 1.17.4 shows the A-D control regis-

ter in one-shot mode.

Table 1.17.2. One-shot mode specifications

Figure 1.17.4. A-D conversion register in one-shot mode

A-D control register 0 (Note 1)

Symbol

Address

When reset

ADCON0

03D6

00000XXX

Analog input pin select
bit

Bit symbol

Bit name

Function

CH1

CH2

A-D operation mode
select bit 0

MD0

MD1

Trigger select bit

0 : Software trigger
1 : AD

TRG

trigger

TRG

ADST

A-D conversion start flag

0 : A-D conversion disabled
1 : A-D conversion started

Frequency select bit 0

0: f

/4 is selected

1: f

/2 is selected

CKS0

A-D control register 1 (Note)

Symbol

Address

When reset

ADCON1

03D7

Bit name

Function

Bit symbol

A-D sweep pin
select bit

SCAN0

SCAN1

MD2

BITS

8/10-bit mode select bit

0 : 8-bit mode
1 : 10-bit mode

VCUT

Vref connect bit

A-D operation mode
select bit 1

1 : Vref connected

Invalid in one-shot mode

0 0 0 : AN

is selected

0 0 1 : AN

is selected

0 1 0 : AN

is selected

0 1 1 : AN

is selected

1 0 0 : AN

is selected

1 0 1 : AN

is selected

1 1 0 : AN

is selected

1 1 1 : AN

is selected

(Note 2)

b2 b1 b0

0 0 : One-shot mode

(Note 2)

b4 b3

CH0

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion

result is indeterminate.

Note 2: When changing A-D operation mode, set analog input pin again.

Frequency select bit1

0 : f

/2 or f

/4 is selected

1 : f

is selected

CKS1

Note: If the A-D control register is rewritten during A-D conversion, the conversion

result is indeterminate.

Reserved bit

Must always be set to "0"

Set to "0" when this mode is selected

Item

Specification

Function

The pin selected by the analog input pin select bit is used for one A-D conversion

Start condition

Writing "1" to A-D conversion start flag

Stop condition

· End of A-D conversion (A-D conversion start flag changes to "0", except

when external trigger is selected)

· Writing "0" to A-D conversion start flag

Interrupt request generation timing

End of A-D conversion

Input pin

One of AN

to AN

, as selected

Reading of result of A-D converter

Read A-D register corresponding to selected pin

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A-D Converter

135

(2) Repeat mode

In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion.

Table 1.17.3 shows the specifications of repeat mode. Figure 1.17.5 shows the A-D control register in

repeat mode.

A-D control register 0 (Note 1)

Symbol

Address When

reset

ADCON0

03D6

00000XXX

Analog input pin
select bit

CH0

Bit symbol

Bit name

Function

CH1

CH2

A-D operation mode
select bit 0

MD0

MD1

Trigger select bit

0 : Software trigger
1 : AD

TRG

trigger

TRG

ADST

A-D conversion start flag

0 : A-D conversion disabled
1 : A-D conversion started

Frequency select bit 0

0 : f

/4 is selected

1 : f

/2 is selected

CKS0

A-D control register 1 (Note)

Symbol

Address

When reset

ADCON1

03D7

Bit name

Function

Bit symbol

A-D sweep pin
select bit

SCAN0

SCAN1

MD2

BITS

8/10-bit mode select bit

0 : 8-bit mode
1 : 10-bit mode

VCUT

Vref connect bit

A-D operation mode
select bit 1

1 : Vref connected

Invalid in repeat mode

0 0 0 : AN

is selected

0 0 1 : AN

is selected

0 1 0 : AN

is selected

0 1 1 : AN

is selected

1 0 0 : AN

is selected

1 0 1 : AN

is selected

1 1 0 : AN

is selected

1 1 1 : AN

is selected

(Note 2)

b2 b1 b0

0 1 : Repeat mode

(Note 2)

b4 b3

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion

result is indeterminate.

Note 2: When changing A-D operation mode, set analog input pin again.

Frequency select bit 1

0 : f

/2 or f

/4 is selected

1 : f

is selected

CKS1

Note: If the A-D control register is rewritten during A-D conversion, the conversion

result is indeterminate.

Reserved bit

Must always be set to "0"

Set to "0" when this mode is selected

Figure 1.17.5. A-D conversion register in repeat mode

Item

Specification

Function

The pin selected by the analog input pin select bit is used for repeated A-D conversion

Star condition

Writing "1" to A-D conversion start flag

Stop condition

Writing "0" to A-D conversion start flag

Interrupt request generation timing

None generated

Input pin

One of AN

to AN

, as selected

Reading of result of A-D converter

Read A-D register corresponding to selected pin (at any time)

Table 1.17.3. Repeat mode specifications

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A-D Converter

136

(3) Single sweep mode

In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D

conversion. Table 1.17.4 shows the specifications of single sweep mode. Figure 1.17.6 shows the A-D

control register in single sweep mode.

Table 1.17.4. Single sweep mode specifications

Figure 1.17.6. A-D conversion register in single sweep mode

A-D control register 0 (Note)

Symbol

Address

When reset

ADCON0

03D6

00000XXX

Analog input pin
select bit

CH0

Bit symbol

Bit name

Function

CH1

CH2

A-D operation mode
select bit 0

1 0 : Single sweep mode

MD0

MD1

Trigger select bit

0 : Software trigger
1 : AD

TRG

trigger

TRG

ADST

A-D conversion start flag

0 : A-D conversion disabled
1 : A-D conversion started

Frequency select bit 0

0 : f

/4 is selected

1 : f

/2 is selected

CKS0

A-D control register 1 (Note 1)

Symbol

Address

When reset

ADCON1

03D7

Bit name

Function

Bit symbol

A-D sweep pin select bit

SCAN0

SCAN1

MD2

BITS

8/10-bit mode select bit

0 : 8-bit mode
1 : 10-bit mode

VCUT

Vref connect bit

A-D operation mode
select bit 1

1 : Vref connected

1 0

Invalid in single sweep mode

Note : If the A-D control register is rewritten during A-D conversion, the conversion result

is indeterminate.

b4 b3

When single sweep and repeat sweep mode 0
are selected

0 0 : AN

, AN

(2 pins)

0 1 : AN

to AN

(4 pins)

1 0 : AN

to AN

(6 pins)

1 1 : AN

to AN

(8 pins)

b1 b0

Note: If the A-D control register is rewritten during A-D conversion, the conversion result

is indeterminate.

Frequency select bit 1

0 : f

/2 or f

/4 is selected

1 : f

is selected

CKS1

0 0

Reserved bit

Must always be set to "0"

Set to "0" when this mode is selected

Item

Specification

Function

The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion

Start condition

Writing "1" to A-D converter start flag

Stop condition

· End of A-D conversion (A-D conversion start flag changes to "0", except

when external trigger is selected)

· Writing "0" to A-D conversion start flag

Interrupt request generation timing

End of A-D conversion

Input pin

and AN

(2 pins), AN

to AN

(4 pins), AN

to AN

(6 pins), or AN

to AN

(8 pins)

Reading of result of A-D converter

Read A-D register corresponding to selected pin

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A-D Converter

137

(4) Repeat sweep mode 0

In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep

A-D conversion. Table 1.17.5 shows the specifications of repeat sweep mode 0. Figure 1.17.7 shows the

A-D control register in repeat sweep mode 0.

Figure 1.17.7. A-D conversion register in repeat sweep mode 0

A-D control register 0 (Note)

Symbol

Address

When reset

ADCON0

03D6

00000XXX

Analog input pin
select bit

CH0

Bit symbol

Bit name

Function

CH1

CH2

A-D operation mode
select bit 0

1 1 : Repeat sweep mode 0

MD0

MD1

Trigger select bit

0 : Software trigger
1 : AD

TRG

trigger

TRG

ADST

A-D conversion start flag

0 : A-D conversion disabled
1 : A-D conversion started

Frequency select bit 0

0 : f

/4 is selected

1 : f

/2 is selected

CKS0

A-D control register 1 (Note)

Symbol

Address

When reset

ADCON1

03D7

Bit name

Function

Bit symbol

A-D sweep pin select bit

SCAN0

SCAN1

MD2

BITS

8/10-bit mode select bit

0 : 8-bit mode
1 : 10-bit mode

VCUT

Vref connect bit

A-D operation mode
select bit 1

1 : Vref connected

1 1

Invalid in repeat sweep mode 0

Note : If the A-D control register is rewritten during A-D conversion, the conversion result

is indeterminate.

b4 b3

When single sweep and repeat sweep mode 0
are selected

0 0 : AN

, AN

(2 pins)

0 1 : AN

to AN

(4 pins)

1 0 : AN

to AN

(6 pins)

1 1 : AN

to AN

(8 pins)

b1 b0

Note: If the A-D control register is rewritten during A-D conversion, the conversion result

is indeterminate.

Frequency select bit 1

0 : f

/2 or f

/4 is selected

1 : f

is selected

CKS1

0 0

Reserved bit

Must always be set to "0"

Set to "0" when this mode is selected

Item

Specification

Function

The pins selected by the A-D sweep pin select bit are used for repeat A-D conversion

Start condition

Writing "1" to A-D conversion start flag

Stop condition

Writing "0" to A-D conversion start flag

Interrupt request generation timing

None generated

Input pin

and AN

(2 pins), AN

to AN

(4 pins), AN

to AN

(6 pins), or AN

to AN

(8 pins)

Reading of result of A-D converter

Read A-D register corresponding to selected pin (at any time)

Table 1.17.5. Repeat sweep mode 0 specifications

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A-D Converter

138

Item

Specification

Function

All pins perform repeat A-D conversion, with emphasis on the pin or

pins selected by the A-D sweep pin select bit

Example : AN

selected AN

, etc

Start condition

Writing "1" to A-D conversion start flag

Stop condition

Writing "0" to A-D conversion start flag

Interrupt request generation timing

None generated

Input pin

With emphasis on these pins ; AN

(1 pin), AN

and AN

(2 pins), AN

to AN

(3 pins), AN

to AN

(4 pins)

Reading of result of A-D converter

Read A-D register corresponding to selected pin (at any time)

(5) Repeat sweep mode 1

In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected

using the A-D sweep pin select bit. Table 1.17.6 shows the specifications of repeat sweep mode 1. Figure

1.17.8 shows the A-D control register in repeat sweep mode 1.

A-D control register 0 (Note)

Symbol

Address

When reset

ADCON0

03D6

00000XXX

Analog input pin
select bit

CH0

Bit symbol

Bit name

Function

CH1

CH2

A-D operation mode
select bit 0

1 1 : Repeat sweep mode 1

MD0

MD1

Trigger select bit

0 : Software trigger
1 : AD

TRG

trigger

TRG

ADST

A-D conversion start flag

0 : A-D conversion disabled
1 : A-D conversion started

Frequency select bit 0

0 : f

/4 is selected

1 : f

/2 is selected

CKS0

A-D control register 1 (Note)

Symbol

Address

When reset

ADCON1

03D7

Bit name

Function

Bit symbol

A-D sweep pin select bit

SCAN0

SCAN1

MD2

BITS

8/10-bit mode select bit

0 : 8-bit mode
1 : 10-bit mode

VCUT

Vref connect bit

A-D operation mode
select bit 1

1 : Vref connected

1 1

Invalid in repeat sweep mode 1

Note : If the A-D control register is rewritten during A-D conversion, the conversion result

is indeterminate.

b4 b3

When repeat sweep mode 1 is selected

0 0 : AN

(1 pin)

0 1 : AN

, AN

(2 pins)

1 0 : AN

to AN

(3 pins)

1 1 : AN

to AN

(4 pins)

b1 b0

Note: If the A-D control register is rewritten during A-D conversion, the conversion result

is indeterminate.

Frequency select bit 1

0 : f

/2 or f

/4 is selected

1 : f

is selected

CKS1

0 0

Reserved bit

Must always be set to "0"

Set to "1" when this mode is selected

Figure 1.17.8. A-D conversion register in repeat sweep mode 1

Table 1.17.6. Repeat sweep mode 1 specifications

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

D-A Converter

140

D-A Converter

This is an 8-bit, R-2R type D-A converter. The microcomputer contains three independent D-A converters

of this type.

D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 to 2 (D-A

output enable bits) of the D-A control register decide if the result of conversion is to be output. Do not set the

target port to output mode if D-A conversion is to be performed.

Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register.

V = V

REF

X n/ 256 (n = 0 to 255)

REF

: reference voltage

Table 1.18.1 lists the performance of the D-A converter. Figure 1.18.1 shows the block diagram of the D-A

converter. Figure 1.18.2 shows the D-A control register. Figure 1.18.3 shows the D-A converter equivalent

circuit.

Item

Performance

Conversion method

R-2R method

Resolution

8 bits

Analog output pin

3 channels

Table 1.18.1. Performance of D-A converter

Data bus low-order bits

P13

/DA

D-A register0 (8)

R-2R resistor ladder

D-A0 output enable bit

(Address 03D8

)

P13

/DA

D-A register1 (8)

R-2R resistor ladder

D-A1 output enable bit

(Address 03DA

)

P13

/DA

D-A register2 (8)

R-2R resistor ladder

D-A2 output enable bit

(Address 03DE

)

Figure 1.18.1. Block diagram of D-A converter

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

D-A Converter

141

Figure 1.18.2. D-A control register

D-A control register

Symbol

Address

When reset

DACON

03DC

D-A0 output enable bit

DA0E

Bit symbol

Bit name

Function

R W

0 : Output disabled
1 : Output enabled

D-A1 output enable bit

0 : Output disabled
1 : Output enabled

DA1E

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".

D-A register

Symbol

Address

When reset

DAi (i = 0 to 2)

03D8

03DA

03DE

Indeterminate

Function

R W

Output value of D-A conversion

D-A2 output enable bit

0 : Output disabled
1 : Output enabled

DA2E

REF

DA0

MSB

LSB

D-A0 output enable bit

"0"

"1"

D-A register0

Note 1: The above diagram shows an instance in which the D-A register is assigned 2A

Note 2: The same circuit as this is also used for D-A1 and D-A2.
Note 3: To reduce the current consumption when the D-A converter is not used, set the D-A output enable bit to 0 and set the D-A register to 00

so that no current flows in the resistors Rs and 2Rs.

"0"

"1"

Figure 1.18.3. D-A converter equivalent circuit

Programmable I/O Port

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

142

Programmable I/O Ports

There are 104 programmable I/O ports: P0 to P13 (excluding P7

). Each port can be set independently for

input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P7

an input-only port and has no built-in pull-up resistance.

Figures 1.19.1 to 1.19.4 show the programmable I/O ports. Figure 1.19.5 shows the I/O pins.

Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.

To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input

mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A con-

verter), they function as outputs regardless of the contents of the direction registers. When pins are to be

used as the outputs for the D-A converter, do not set the direction registers to output mode. See the

descriptions of the respective functions for how to set up the built-in peripheral devices.

(1) Direction registers

Figure 1.19.6 shows the direction registers.

These registers are used to choose the direction of the programmable I/O ports. Each bit in these regis-

ters corresponds one for one to each I/O pin.

Note: There is no direction register bit for P7

(2) Port registers

Figure 1.19.7 shows the port registers.

These registers are used to write and read data for input and output to and from an external device. A

port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit

in port registers corresponds one for one to each I/O pin.

(3) Pull-up control registers

Figure 1.19.8 shows the pull-up control registers.

The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports

are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is

set for input. The pull-up resistance is not connected for pins that are set for output from peripheral

functions, regardless of the setting in the pull-up control register. When pull-up is ON for ports P1 and P2,

an intermittent pull-up that pulls up the port for only a set period of time, can be performed from the key

input mode register.

(4) Key input mode register

Figure 1.19.9 shows the key input mode register.

With bits 0 and 1 of this register, it is possible to select both edges or the fall edge of the key input for P1

and P2. Also, with bit 2, it is possible to make the pull-up for a port (P1 or P2), which is set for pull-up using

the pull-up control register, automatically connect as an intermittent pull-up. And, using the significant 3

bits, the pull-up resistance can be connected to and disconnected from ports P12 and P13.

(5) Real-time port control register

Figure 1.19.10 shows the real-time port control register. The real-time port control register can be used to

set the registers of ports P0, P1, P2 and P12 for real-time port output, whereby output is synchronized

with timer overflow of timers A0, A1, A5 and A6 in the timer mode. For details, see "Real-time Port".

Programmable I/O Port

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

143

Figure 1.19.1. Programmable I/O ports (1)

to P1

, P2

to P2

to P0

P12

to P12

Data bus

Direction register

Port latch

Pull-up selected

to P3

to P5

to P7

Data bus

Direction register

Port latch

Pull-up selection

, P3

Port ON/OFF

LCD drive timing

Port/segment

Data bus

Direction register

Port latch

Timer A
overflow

"1"

Segment output

Data bus

Direction register

Port latch

Pull-up selection

Timer A
overflow

Intermittent pull-up control

"1"

Interface logic

level shift circuit

Intermittent pull-up control

Programmable I/O Port

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

147

Figure 1.19.6. Direction register

Port P3 direction register

Symbol

Address

When reset

PD3

03E7

XX000000

Bit name

Function

Bit symbol

PD3_0

Port P3

direction register

PD3_1

Port P3

direction register

PD3_2

Port P3

direction register

PD3_3

Port P3

direction register

PD3_4

Port P3

direction register

0: Input mode
(Functions as an input port)
1: Output mode
(Functions as an output port)

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.

PD3_5

Port P3

direction register

Port Pi direction register (Note)

Bit name

Function

Bit symbol

PDi_0

Port Pi

direction register

PDi_1

Port Pi

direction register

PDi_2

Port Pi

direction register

PDi_3

Port Pi

direction register

PDi_4

Port Pi

direction register

PDi_5

Port Pi

direction register

PDi_6

Port Pi

direction register

PDi_7

Port Pi

direction register

0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)

(i = 0 to 12 except 3 and 7)

Symbol

Address

When reset

PDi

( i = 0 to 12 except 3 and 7)

03E2

, 03E3

, 03E6

, 03EA

, 00

03EB

, 03EE

, 03F2

, 03F3

03F6

, 03F7

, 03FA

Note : Do not access the Port P12 direction register in words.

Port P7 direction register

Symbol

Address

When reset

PD7

03EF

X0000000

Bit name

Function

Bit symbol

PD7_0

Port P7

direction register

PD7_1

Port P7

direction register

PD7_2

Port P7

direction register

PD7_3

Port P7

direction register

PD7_4

Port P7

direction register

0: Input mode
(Functions as an input port)
1: Output mode
(Functions as an output port)

Nothing is assigned.
In an attempt to write to this bit, write "0". The value, if read, turns out to be
indeterminate.

PD7_5

Port P7

direction register

PD7_6

Port P7

direction register

Port P13 direction register

Symbol

Address

When reset

PD13

03FB

XXXXX000

Bit name

Function

Bit symbol

PD13_0

Port P13

direction register

PD13_1

Port P13

direction register

PD13_2

Port P13

direction register

0: Input mode
(Functions as an input port)
1: Output mode
(Functions as an output port)

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.

Programmable I/O Port

Mitsubishi microcomputers

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148

Figure 1.19.7. Port register

Port Pi register

(Note)

Symbol

Address

When reset

Pi ( i = 0 to 12 except 3 and 7) 03E0

, 03E1

, 03E4

, 03E8

, Indeterminate

03E9

16,

03EC

, 03F0

, 03F1

03F4

, 03F5

, 03F8

Bit name

Function

Bit symbol

Port P3 register

Symbol

Address

When reset

03E5

Indeterminate

Bit mame

Function

Bit symbol

Port P7 register

Symbol

Address

When reset

03ED

Indeterminate

Port P13 register

Symbol

Address

When reset

P13

03F9

Indeterminate

Note : Do not access the Port P12 register in words.

Pi_0

Port Pi

Pi_1

Port Pi

Pi_2

Port Pi

Pi_3

Port Pi

Pi_4

Port Pi

Pi_5

Port Pi

Pi_6

Port Pi

Pi_7

Port Pi

Data is input an âtput to and
from each pin by reading and
writing to and from each
corresponding bit
0 : "L" level data
1 : "H" level data

(i = 0 to 12 except 3 and 7)

Data is input and output to and
from each pin by reading and
writing to and from each
corresponding bit
0 : "L" level data
1 : "H" level data

P3_0

Port P3

P3_1

Port P3

P3_2

Port P3

P3_3

Port P3

P3_4

Port P3

P3_5

Port P3

P7_0

Port P7

P7_1

Port P7

P7_2

Port P7

P7_3

Port P7

P7_4

Port P7

P7_5

Port P7

P7_6

Port P7

P7_7

Port P7

Data is input and output to and
from each pin by reading and
writing to and from each
corresponding bit
(except for P7

)

0 : "L" level data
1 : "H" level data (Note)

P13_0

Port P13

P13_1

Port P13

P13_2

Port P13

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.

Bit mame

Function

Bit symbol

Bit mame

Function

Bit symbol

Data is input and output to and
from each pin by reading and
writing to and from each
corresponding bit
0 : "L" level data
1 : "H" level data

Note :

Since P7

and P7

are N-channel open drain ports, the data is high-impedance.

Programmable I/O Port

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

149

Figure 1.19.8. Pull-up control register

Pull-up control register 0 (Note 1)(Note 2)

Symbol

Address

When rese

PUR0

03FC

00000011

Bit name

Function

Bit symbol

PU00

to P0

pull-up

PU01

to P0

pull-up

PU02

to P1

pull-up

PU03

to P1

pull-up

PU04

to P2

pull-up

PU05

to P2

pull-up

PU06

to P3

pull-up

PU07

to P3

pull-up

The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high

Pull-up control register 1 (Note)

Symbol

Address

When rese

PUR1

03FD

Bit name

Function

Bit symbol

PU10

to P4

pull-up

PU11

to P4

pull-up

PU12

to P5

pull-up

PU13

to P5

pull-up

PU14

to P6

pull-up

PU15

to P6

pull-up

PU16

to P7

pull-up

PU17

to P7

pull-up

The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high

Pull-up control register 2 (Note)

Symbol

Address

When reset

PUR2

03FE

11110000

Bit name

Function

Bit symbol

PU20

to P8

pull-up

PU21

to P8

pull-up

PU22

to P9

pull-up

PU23

to P9

pull-up

PU24

P10

to P10

pull-up

PU25

P10

to P10

pull-up

The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high

PU26

P11

to P11

pull-up

PU25

P10

to P10

pull-up

PU27

P11

to P11

pull-up

Note 1 : The pull-up resistance is not connected for pins that are set for output from

peripheral functions, regardless of the setting in the pull-up control register.

Note 2 : Do not access this register in words.

Note : The pull-up resistance is not connected for pins that are set for output from
peripheral functions, regardless of the setting in the pull-up control register.

Programmable I/O Port

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

150

Figure 1.19.9. Key input mode register

Real time port control register

Symbol

Address

When reset

RTP

03FF

Bit name

Function

Bit symbol

RTP2

to P1

real time port

mode select bi

RTP3

to P1

real time port

mode select bit

RTP4

to P2

real time port

mode select bi

RTP5

to P2

real time port

mode select bit

0 : I/O port
1 : Real time port output (Note)

RTP1

to P0

real time port

mode select bit

RTP0

to P0

real time port

mode select bit

RTP6

P12

to P12

real time port

mode select bit

RTP7

P12

to P12

real time port

mode select bit

Note : The corresponding port direction register is invalidated.

Figure 1.19.10. Realtime port control register

Key input mode register

Bit name

Function

Bit

symbol

Symbol

Address

When reset

KUPM

0126

01100000

P1KIS

P1 key input select bit (Note 1)

0 : Falling edge
1 : Two edges (Note 2)

0 : Disable
1 : Enable

P1 key input enable bit

P2 key input select bit (Note 1)

P2 key input enable bit

P3 key input enable bit

P12

to P12

pull-up (Note 3)

The corresponding port is
pulled high with a pull-up
resistor
0 : Not pulled high
1 : Pulled high

P12

to P12

pull-up (Note 3)

P13

to P13

pull-up (Note 3)

P1KIE

P2KIS

P2KIE

P3KIE

PUP12L

PUP12H

PUP13

0 : Falling edge
1 : Two edges (Note 2)

Note 1 : If this bit is set for "Two edges" when the corresponding port has been

specified to have a pullup, the port is automatically pulled high intermittently.
Operating sub-clock.

Note 2 : When this bit is set for "Two edges" and the input from either of the

corresponding pin is "L", if the pullup control register 0 of the corresponding port

(bit 2 to 5 at the address 03FC

) is changed, there may be the thing that the

key input interruption request is set to "1".

Note 3 : The pull-up resistance is not connected for pins that are set for output from

peripheral functions, regardless of the setting in the pull-up control register.

Programmable I/O Port

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

151

Table 1.19.1. Example connection of unused pins in single-chip mode

Figure 1.19.11. Example connection of unused pins

Pin name

Connection

Ports P0 to P13
(excluding P7

)

OUT

(Note 2), X

COUT

, V

REF

After setting for output mode, leave these pins open; or after setting for
input mode, connect every pin to V

via a resistor (Note 1, Note 3).

Open

Connect to V

NMI

Connect this pin to V

via a resistor (pull-up)

, C

, V

Open

Connect to V

CNV

Connect this pin to V

via a resistor (pull-down)

CIN

Connect this pin to V

via a resistor (pull-down)

COM

to COM

Open

SEG

to SEG

Open

If setting these pins in output mode and opening them, ports are in input mode until switched into
output mode by use of software after reset. Thus the voltage levels of the pins become unstable,
and there can be instances in which the power source current increases while the ports are in
input mode.
In view of an instance in which the contents of the direction registers change due to a runaway
generated by noise or other causes, setting the contents of the direction registers periodically by
use of software increases program reliability.
When an external clock is input to the X

pin.

Output "L" if port P7

and P7

are set to output mode.

Port P7

and P7

are N channel open drain.

Note 1:

Note 2:
Note 3:

Port P0 to P13 (except for P7

)

(Input mode)

(Output mode)

NMI

REF

Microcomputer

Open

CNV

CIN

COUT

Open

COM

to COM

Open

SEG

to SEG

Open

Usage precaution

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

152

Timer A (timer mode)

Usage Precaution

Timer A (event counter mode)

(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the

value of the counter. Reading the timer Ai register with the reload timing gets "FFFF

" by underflow

or "0000

" by overflow. Reading the timer Ai register after setting a value in the timer Ai register with

a count halted but before the counter starts counting gets a proper value.

(2) When stop counting in free run type, set timer again.

(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the

value of the counter. Reading the timer Ai register with the reload timing gets "FFFF

". Reading the

timer Ai register after setting a value in the timer Ai register with a count halted but before the counter

starts counting gets a proper value.

(1) Setting the count start flag to "0" while a count is in progress causes as follows:

· The counter stops counting and a content of reload register is reloaded.

· The TAi

OUT

pin outputs "L" level.

· The interrupt request generated and the timer Ai interrupt request bit goes to "1".

(2) The timer Ai interrupt request bit goes to "1" if the timer's operation mode is set using any of the

following procedures:

· Selecting one-shot timer mode after reset.

· Changing operation mode from timer mode to one-shot timer mode.

· Changing operation mode from event counter mode to one-shot timer mode.

Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to "0"

after the above listed changes have been made.

Timer A (one-shot timer mode)

(1) The timer Ai interrupt request bit becomes "1" if setting operation mode of the timer in compliance with

any of the following procedures:

· Selecting PWM mode after reset.

· Changing operation mode from timer mode to PWM mode.

· Changing operation mode from event counter mode to PWM mode.

Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to "0"

after the above listed changes have been made.

(2) Setting the count start flag to "0" while PWM pulses are being output causes the counter to stop

counting. If the TAi

OUT

pin is outputting an "H" level in this instance, the output level goes to "L", and

the timer Ai interrupt request bit goes to "1". If the TAi

OUT

pin is outputting an "L" level in this instance,

the level does not change, and the timer Ai interrupt request bit does not becomes "1".

Timer A (pulse width modulation mode)

Timer B (timer mode, event counter mode)

(1) Reading the timer Bi register while a count is in progress allows reading , with arbitrary timing, the

value of the counter. Reading the timer Bi register with the reload timing gets "FFFF

". Reading the

timer Bi register after setting a value in the timer Bi register with a count halted but before the counter

starts counting gets a proper value.

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Usage precaution

153

Stop Mode and Wait Mode

A-D Converter

(1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt

request bit goes to "1".

(2) When the first effective edge is input after a count is started, an indeterminate value is transferred to

the reload register. At this time, timer Bi interrupt request is not generated.

Timer B (pulse period/pulse width measurement mode)

(1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit

0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs).

In particular, when the Vref connection bit is changed from "0" to "1", start A-D conversion after an

elapse of 1

s or longer.

(2) When changing A-D operation mode, select analog input pin again.

(3) Using one-shot mode or single sweep mode

Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by A-

D conversion interrupt request bit.)

(4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1

Use the undivided main clock as the internal CPU clock.

____________

(1) When returning from stop mode by hardware reset, RESET pin must be set to "L" level until main clock

oscillation is stabilized.

(2) When switching to either wait mode or stop mode, instructions occupying four bytes either from the

WAIT instruction or from the instruction that sets the every-clock stop bit to "1" within the instruction

queue are prefetched and then the program stops. So put at least four NOPs in succession either to

the WAIT instruction or to the instruction that sets the every-clock stop bit to "1".

(3) When the MCU running in low-speed or low power dissipation mode, do not enter WAIT mode with

WAIT peripheral function clock stop bit set to "1".

(1) Make sure timer Ai for real time port output is set for timer mode, and is set to have "no gate function"

using the gate function select bit.

(2) Before setting the real time port mode select bit to "1", temporarily turn off the timer Ai used and write

its set value to the timer Ai register.

Real time port

Serial I/O

When the IIC mode select bit (bit 0 at address 0377

) is set to "1";

(1) When setting up port P7 (address 03EF

), write immediate values. If you use Read/Modify/Write

instructions (BSET, BCLR, AND, OR, etc..) on the port P7 direction register, the value of P7

direction

(2) Only for the mask ROM version, when the internal/external clock select bit (bit 3 of address 0378

) is

set to "1 (set to slave)", the SCL wait output bit (bit 2 of address 0376

) and SCL wait output bit 2 (bit

5 of address 0376

) do not function.

(3) Only for the mask ROM version, when the internal/external clock select bit (bit 3 of address 0378

) is

set to "1 (set to slave)", the port P7

cannot be read unless the port P7

direction register (bit 1 of

address 03EF

) is set to "0", although it is specified as follows; "When IICM=1, the port pin shall be

able to be read even if the P7

direction register=1."

Usage precaution

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

154

Example 1:

INT_SWITCH1:

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear TA0IC int. priority level and int. request bit.

NOP

; Four NOP instructions are required when using HOLD function.

NOP
FSET

; Enable interrupts.

Example 2:

INT_SWITCH2:

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear TA0IC int. priority level and int. request bit.

MOV.W MEM, R0

; Dummy read.

FSET

; Enable interrupts.

Example 3:

INT_SWITCH3:

PUSHC FLG

; Push Flag register onto stack

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear TA0IC int. priority level and int. request bit.

POPC

FLG

; Enable interrupts.

· When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled,

the interrupt request bit is not set sometimes even if the interrupt request for that register has

been generated. This will depend on the instruction. If this creates problems, use the below in-

structions to change the register.

Instructions : AND, OR, BCLR, BSET

(1) Reading address 00000

· When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number

and interrupt request level) in the interrupt sequence.

The interrupt request bit of the certain interrupt written in address 00000

will then be set to "0".

Reading address 00000

by software sets enabled highest priority interrupt source request bit to "0".

Though the interrupt is generated, the interrupt routine may not be executed.

Do not read address 00000

by software.

(2) Setting the stack pointer

· The value of the stack pointer immediately after reset is initialized to 0000

. Accepting an

interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to

_______

set a value in the stack pointer before accepting an interrupt. When using the NMI interrupt,

initialize the stack pointer at the beginning of a program. Concerning the first instruction immedi-

_______

ately after reset, generating any interrupts including the NMI interrupt is prohibited.

_______

(3) The NMI interrupt

_______

· The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc via a resistor (pull-up)

if unused. Be sure to work on it.

_______

· Do not get either into stop mode with the NMI pin set to "L".

(4) External interrupt

________

· When the polarity of the INT

to INT

pins is changed, the interrupt request bit is sometimes set to

"1". After changing the polarity, set the interrupt request bit to "0".

(5) Rewrite the interrupt control register

· To rewrite the interrupt control register, do so at a point that does not generate the interrupt

request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt

control register after the interrupt is disabled. The program examples are described as follow:

Interrupts

Electrical characteristics

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

155

Table 1.21.1. Absolute maximum ratings

Operating ambient temperature

Parameter

Unit

Input
voltage

RESET,

Analog supply voltage

Supply voltage

Output
voltage

0.3 to Vcc+0.3

Power dissipation

Storage temperature

0.3 to 6.5

Rated value

0.3 to 6.5

Condition

AVcc

Vcc

stg

opr

Symbol

40 to 150

300

20 to 85

to P3

, P4

to P4

, P5

to P5

to P0

, P1

to P1

, P2

to P2

to P4

, P5

to P5

, P6

to P6

to P1

, P2

to P2

, P3

to P3

Vcc=AVcc

to P6

, P7

to P7

, P8

to P8

REF

, X

to P9

, P10

to P10

VL1

P13

to P13

0.3 to VL2

VL2

VL1 to VL3

VL3

VL2 to 6.5

, P7

, C

0.3 to 6.5

to P7

, P8

to P8

, P9

to P9

P13

to P13

, X

OUT

to P0

, P10

to P10

P11

to P11

, P12

to P12

0.3 to Vcc

When output port

When segment output

0.3 to VL3

, P7

0.3 to 6.5

(Mask ROM version CNVss)

(flash memory version CNVss)

P11

to P11

, P12

to P12

Ta = 25°C

°C

Electrical characteristics

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

156

Note 1: The mean output current is the mean value within 100ms.

Note 2: The total I

(peak) for ports P0, P1, P2, P3

to P3

, P4, P5, P6, P7

to P7

and P12

to P12

must be 80mA max. The total

(peak) for ports P0, P1, P2, P3

to P3

, P4, P5, P6, P7

to P7

and P12

to P12

must be 80mA max. The total I

(peak)

for ports P8, P9, P10, P11, P12

, P12

and P13

to P13

must be 80mA max. The total I

(peak) for ports P8, P9, P10, P11,

P12

,P12

and P13

to P13

must be 80mA max.

Note 3: Relationship between main clock oscillation frequency and supply voltage.

Table 1.21.2. Recommended operating conditions (referenced to V

= 2.7V to 5.5V at Ta = 20 to 85

unless otherwise specified)

Typ.

Max.

Unit

Parameter

Vcc

Supply voltage

Symbol

Min

Standard

(Xc

)

Subclock oscillation frequency

kHz

32.768

Analog supply voltage

Vcc

AVcc

Analog supply voltage

Vss

AVss

0.8Vcc

Vcc

0.2Vcc

LOW input
voltage

HIGH input
voltage

0.5

LOW peak
output current

10.0

)

Main clock input
oscillation frequency

MHz

OL (peak)

=4.0V to 5.5V

With wait

MHz

OH (avg)

HIGH average
output current

OH (peak)

HIGH peak
output current

OL (avg)

LOW average
output current

2.5

to P0

, P1

to P1

, P2

to P2

, P3

to P3

, P4

to P4

to P0

, P10

to P10

, P11

to P11

, P12

to P12

5.0

=2.7V to 4.0V

10.000

MHz

=4.0V to 5.5V

2.31

MHz

=2.7V to 4.0V

+0.760

No wait

2.7

5.5

5.0

, P7

0.8Vcc

6.5

to P0

, P1

to P1

, P2

to P2

, P3

to P3

, P4

to P4

to P1

, P2

to P2

, P3

to P3

, P4

to P4

10.0

to P0

, P10

to P10

, P11

to P11

, P12

to P12

to P1

, P2

to P2

, P3

to P3

, P4

to P4

0.1

5.0

to P0

, P10

to P10

, P11

to P11

, P12

to P12

to P1

to P2

,P3

to P3

, P4

to P4

5.0

to P0

, P10

to P10

, P11

to P11

, P12

to P12

to P1

, P2

to P2

, P3

to P3

, P4

to P4

(Note 1)

(Note 3)

to P5

, P6

to P6

, P7

to P7

, P8

to P8

, P9

to P9

P10

to P10

, P11

to P11

, P12

to P12

, 13

to P13

to P5

, P6

to P6

, P7

to P7

, P8

to P8

, P9

to P9

P10

to P10

, P11

to P11

, P12

to P12

, 13

to P13

to P5

, P6

to P6

, P7

to P7

, P8

to P8

, P9

to P9

P13

to P13

to P5

, P6

to P6

, P7

to P7

, P8

to P8

, P9

to P9

P13

to P13

to P5

, P6

to P6

, P7

to P7

, P8

to P8

, P9

to P9

P13

to P13

to P5

, P6

to P6

, P7

to P7

, P8

to P8

, P9

to P9

P13

to P13

, RESET, CNV

(Note 2)

5.5

4.0

2.7

0.0

3.5

10.0

Main clock input oscillation frequency

(No wait)

Supply voltage [V]
(BCLK: no division)

Operating maximum frequency [MH

]

5 X Vcc10.000MHz

5.5

4.0

2.7

0.0

10.0

Main clock input oscillation frequency

(With wait)

Supply voltage [V]
(BCLK: no division)

7.0

2.31 X V

+0.760MHz

Operating maximum frequency [MH

]

Electrical characteristics (Vcc = 5V)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

157

Table 1.21.3. Electrical characteristics (referenced to V

= 5V, V

= 0V at Ta = 25

C, f(X

)=10MH

unless otherwise specified)

= 5V

HIGH output
voltage

4.7

= 0.1mA

= 5mA

to P1

, P2

to P2

, P3

to P3

HIGHPOWER

LOWPOWER

= 1mA

= 0.5mA

LOW output
voltage

2.0

=5mA

HIGHPOWER

LOWPOWER

2.0

=1mA

=0.5mA

Hysteresis

HIGH input
current

T+-

T-

0.8

1.8

5.0

TA0

to TA7

, TB0

to TB5

=5V

LOW input
current

When clock is stopped

2.0

=0V

COUT

LOW output
voltage

HIGHPOWER

LOWPOWER

With no load applied

HIGHPOWER

LOWPOWER

1.6

With no load applied

3.0

=0V

30.0

50.0

fXCIN

6.0

to P7

, P8

to P8

, P9

to P9

, P10

to P10

= 200

=200

CTS

, CLK

, NMI,

to P0

, P1

to P1

, P2

to P2

to P3

, P4

to P4

, P5

to P5

(

)

Note : Has no effect during intermittent pullup operation.

TA2

OUT

to TA4

OUT

, TA7

OUT

Electrical characteristics (Vcc = 5V)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

158

Table 1.21.5. A-D conversion characteristics (referenced to V

= AV

= V

REF

= 5V, Vss = AV

= 0V

at Ta = 25

C, f(X

) = 10MH

unless otherwise specified)

= 5V

Symbol

Standard

Typ.

Unit

Measuring condition

Min.

Max.

Parameter

Icc

Power supply current

Square wave, no division

When clock is stopped

Ta=25 °C

1.0

µA

20.0

When clock is stopped

19.0

38.0

f(X

)=10MHz

f(X

CIN

)=32kHz

When a WAIT instruction is executed

4.0

µA

I/o pin is no
load applied

f(X

CIN

)=32kHz

Square wave

90.0

µA

f(X

CIN

)=32kHz

Square wave

Mask ROM version

Flash memory version

200.0

µA

Ta=85 °C

Supply voltage (V

) (Note)

When charge-pump not used

2.7

6.5

Mask ROM, flash
memory versions

Supply voltage (V

)

When charge-pump used

1.3

2.1

1.7

Power supply current (V

)

VL1=1.7V, f

(LCDCK)

= 200Hz

6.0

µA

3.0

Note: Rating: V

=-0.3 V to V

, V

to V

, V

to 6.5V.

Standard

Typ. M

Resolution

Absolute
accuracy

Bits

LSB

REF

Symbol

Parameter

Measuring condition

Unit

REF

= 5V

LADDER

CONV

Conversion time

(10bit)

REF

3.3

Conversion time

(8bit)

2.8

CONV

SAMP

Sampling time

0.3

REF

Sample & hold function not available

(

)

(

)

REF

= V

= 5V

Min.

Typ.

Setup time
Output resistance
R

1.0

1.5

(

Note

)

Table 1.21.4. Electrical characteristics (referenced to V

= 5V, V

= 0V at Ta = 25

C, f(X

)=10MH

unless otherwise specified)

Table 1.21.6. D-A conversion characteristics (referenced to V

= AV

REF

=5V, V

= AV

SS =

0V at Ta = 25

C, f(X

) = 10MH

unless otherwise specified)

Note: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to "00

The A-D converter's ladder resistance is not included.

Also, when the Vref is unconnected at the A-D control register, I

VREF

is sent.

Electrical characteristics (Vcc = 5V)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

159

Timing requirements (referenced to V

= 5V, V

= 0V at Ta = 25

C unless otherwise specified)

Table 1.21.7. External clock input

Table 1.21.9. Timer A input (gating input in timer mode)

Table 1.21.10. Timer A input (external trigger input in one-shot timer mode)

Table 1.21.11. Timer A input (external trigger input in pulse width modulation mode)

Table 1.21.12. Timer A input (up/down input in event counter mode)

= 5V

Max.

External clock rise time

Min.

External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width

External clock fall time

ns
ns

w(H

)

w(L)

Parameter

Symbol

Unit

Standard

100

Standard

Max.

TAi

input LOW pulse width

w(TAL)

Min.

Unit

TAi

input HIGH pulse width

w(TAH)

Parameter

Symbol

c(TA)

TAi

input cycle time

100

Standard

Max.

Min.

Unit

TAi

input cycle time

TAi

input HIGH pulse width

TAi

input LOW pulse width

c(TA)

w(TAH)

w(TAL)

Symbol

Parameter

400

200

Standard

Max.

Min.

Unit

TAi

input cycle time

TAi

input HIGH pulse width

TAi

input LOW pulse width

c(TA)

w(TAH)

w(TAL)

Symbol

Parameter

200

100

Standard

Max.

Min.

Unit

w(TAH)

w(TAL)

Symbol

Parameter

TAi

input HIGH pulse width

TAi

input LOW pulse width

100

Standard

Max.

Min.

Unit

Symbol

Parameter

TAi

OUT

input cycle time

TAi

OUT

input HIGH pulse width

TAi

OUT

input LOW pulse width

TAi

OUT

input setup time

TAi

OUT

input hold time

c(UP)

w(UPH)

w(UPL)

su(UP-T

)

h(T

IN-

UP)

2000

1000

400

Table 1.21.8. Timer A input (counter input in event counter mode)

Electrical characteristics (Vcc = 5V)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

160

Timing requirements (referenced to V

= 5V, V

= 0V at Ta = 25

C unless otherwise specified)

Table 1.21.13. Timer B input (counter input in event counter mode)

Table 1.21.14. Timer B input (pulse period measurement mode)

Table 1.21.15. Timer B input (pulse width measurement mode)

Table 1.21.16. A-D trigger input

Table 1.21.17. Serial I/O

_______

Table 1.21.18. External interrupt INTi inputs

= 5V

Standard

Max.

Min.

TBi

input cycle time (counted on one edge)

TBi

input HIGH pulse width (counted on one edge)

TBi

input LOW pulse width (counted on one edge)

c(TB)

w(TBH)

w(TBL)

Parameter

Symbol

Unit

c(TB)

w(TBL)

w(TBH)

TBi

input HIGH pulse width (counted on both edges)

TBi

input LOW pulse width (counted on both edges)

TBi

input cycle time (counted on both edges)

Standard

Max.

Min.

c(TB)

w(TBH)

Symbol

Parameter

Unit

w(TBL)

TBi

input HIGH pulse width

TBi

input cycle time

TBi

input LOW pulse width

Standard

Max.

Min.

c(TB)

Symbol

Parameter

Unit

w(TBL)

w(TBH)

TBi

input cycle time

TBi

input HIGH pulse width

TBi

input LOW pulse width

Standard

Max.

Min.

c(AD)

w(ADL)

Symbol

Parameter

Unit

TRG

input cycle time (trigger able minimum)

TRG

input LOW pulse width

100

200

400

200
200

400

200

1000

125

Standard

Max.

Min.

w(INH)

w(INL)

Symbol

Parameter

Unit

INTi input LOW pulse width

INTi input HIGH pulse width

Standard

Max.

Min.

CLKi input cycle time

CLKi input HIGH pulse width

CLKi input LOW pulse width

c(CK)

w(CKH)

w(CKL)

Parameter

Symbol

Unit

d(C-Q)

su(D-C)

h(C-Q)

TxDi hold time

RxDi input setup time

TxDi output delay time

h(C-D)

RxDi input hold time

250

200

100

Electrical characteristics (Vcc = 3V)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

163

= 3V

Table 1.21.19. Electrical characteristics (referenced to V

= 3V, V

= 0V at Ta = 25

C, f(X

) =

7MH

, with wait)

Symbol

Standard

Unit

Measuring condition

Parameter

= 20µA

HIGH output
voltage

OUT

HIGHPOWER

0.5

=50µA

Hysteresis

T+-

T-

T+-

T-

0.2

1.8

4.0

µA

TA0

to TA7

, TB0

to TB5

4.0

RAM

LOW output
voltage

With no load applied

1.6

3.0

Pull-up
resistance

PULLUP

fXCIN

Feedback resistance X

CIN

10.0

Feedback resistance X

3.0

to P3

, P4

to P4

, P5

to P5

INT

to INT

, AD

TRG

, CTS

CTS

, CLK

, NMI,

(

)

6.0

500.0

Electrical characteristics (Vcc = 3V)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

164

= 3V

Table 1.21.22. D-A conversion characteristics (referenced to V

= AV

= V

REF

= 3V, V

= AV

SS =

0V, at Ta = 25

C, f(X

) = 7MH

unless otherwise specified)

Note : This applies when using one D-A converter, with the D-A register for the unused D-A converter set to "00

". The

A-D converter's ladder resistance is not included.

Also, when the Vref is unconnected at the A-D control register, IV

REF

is sent.

Table 1.21.21. A-D conversion characteristics (referenced to V

= AV

= V

REF

= 3V, V

= AV

0V at Ta = 25

C, f(X

) = 7MH

, with wait unless otherwise specified)

Symbol

Standard

Typ.

Unit

Measuring condition

Min.

Max.

Parameter

Icc

Power supply current

Square wave, no division

When clock is stopped

Ta=25 °C

1.0

µA

Ta=85 °C

20.0

When clock is stopped

6.0

15.0

f(X

)=7MHz

f(X

CIN

)=32kHz

When a WAIT instruction is executed
Oscillation capacity High (Note)

2.8

µA

I/o pin is no
load applied

f(X

CIN

)=32kHz

Square wave

40.0

µA

Supply voltage (V

) (Note 2)

When charge-pump not used

2.7

6.5

f(X

CIN

)=32kHz

Square wave

Mask ROM version

Flash memory version

150.0

µA

f(X

CIN

)=32kHz

When a WAIT instruction is executed
Oscillation capacity Low (Note 1)

0.9

µA

Mask ROM, flash
memory versions

Supply voltage (V

)

When charge-pump used

1.3

2.1

1.7

Power supply current (V

)

=1.7V, f

(LCDCK)

=200Hz

6.0

µA

3.0

Note 1: With one timer operated using f

C32

Note 2: Rating: V

=-0.3 V to V

, V

to V

, V

to 6.5V.

Standard

Resolution

Bits

REF

Measuring condition

2.7

Conversion time

(8bit)

REF

(

)

. M

(

)

Table 1.21.20. Electrical characteristics (referenced to V

= 3V, V

= 0V at Ta = 25

C, f(X

) =

7MH

, with wait)

Electrical characteristics (Vcc = 3V)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

165

Table 1.21.25. Timer A input (gating input in timer mode)

Table 1.21.26. Timer A input (external trigger input in one-shot timer mode)

Table 1.21.27. Timer A input (external trigger input in pulse width modulation mode)

Table 1.21.28. Timer A input (up/down input in event counter mode)

Table 1.21.24. Timer A input (counter input in event counter mode)

Timing requirements (referenced to V

= 3V, V

= 0V at Ta = 25

C unless otherwise specified)

= 3V

Table 1.21.23. External clock input

Max.

External clock rise time

Min.

External clock input cycle time

External clock input HIGH pulse width
External clock input LOW pulse width

External clock fall time

ns
ns

w(H

)

w(L)

Parameter

Symbol

Unit

Standard

143

Standard

Max.

TAi

input LOW pulse width

w(TAL)

Min.

Unit

TAi

input HIGH pulse width

w(TAH)

Parameter

Symbol

c(TA)

TAi

input cycle time

150

Standard

Max.

Min.

Unit

TAi

input cycle time

TAi

input HIGH pulse width

TAi

input LOW pulse width

c(TA)

w(TAH)

w(TAL)

Symbol

Parameter

600

300

Standard

Max.

Min.

Unit

TAi

input cycle time

TAi

input HIGH pulse width

TAi

input LOW pulse width

c(TA)

w(TAH)

w(TAL)

Symbol

Parameter

300

150

Standard

Max.

Min.

Unit

w(TAH)

w(TAL)

Symbol

Parameter

TAi

input HIGH pulse width

TAi

input LOW pulse width

150

Standard

Max.

Min.

Unit

Symbol

Parameter

TAi

OUT

input cycle time

TAi

OUT

input HIGH pulse width

TAi

OUT

input LOW pulse width

TAi

OUT

input setup time

TAi

OUT

input hold time

c(UP)

w(UPH)

w(UPL)

su(UP-T

)

h(T

IN-

UP)

3000

1500

600

Electrical characteristics (Vcc = 3V)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

166

Timing requirements (referenced to V

= 3V, V

= 0V at Ta = 25

C unless otherwise specified)

= 3V

Table 1.21.29. Timer B input (counter input in event counter mode)

Table 1.21.30. Timer B input (pulse period measurement mode)

Table 1.21.31. Timer B input (pulse width measurement mode)

Table 1.21.32. A-D trigger input

Table 1.21.33. Serial I/O

_______

Table 1.21.34. External interrupt INTi inputs

Standard

Max.

Min.

TBi

input cycle time (counted on one edge)

TBi

input HIGH pulse width (counted on one edge)

TBi

input LOW pulse width (counted on one edge)

c(TB)

w(TBH)

w(TBL)

Parameter

Symbol

Unit

c(TB)

w(TBL)

w(TBH)

TBi

input HIGH pulse width (counted on both edges)

TBi

input LOW pulse width (counted on both edges)

TBi

input cycle time (counted on both edges)

Standard

Max.

Min.

c(TB)

w(TBH)

Symbol

Parameter

Unit

w(TBL)

TBi

input HIGH pulse width

TBi

input cycle time

TBi

input LOW pulse width

Standard

Max.

Min.

c(TB)

Symbol

Parameter

Unit

w(TBL)

w(TBH)

TBi

input cycle time

TBi

input HIGH pulse width

TBi

input LOW pulse width

Standard

Max.

Min.

c(AD)

w(ADL)

Symbol

Parameter

Unit

TRG

input cycle time (trigger able minimum)

TRG

input LOW pulse width

150

160

300

600

300
300

600

300

1500

200

Standard

Max.

Min.

w(INH)

w(INL)

Symbol

Parameter

Unit

INTi input LOW pulse width

INTi input HIGH pulse width

Standard

Max.

Min.

CLKi input cycle time

CLKi input HIGH pulse width

CLKi input LOW pulse width

c(CK)

w(CKH)

w(CKL)

Parameter

Symbol

Unit

d(C-Q)

su(D-C)

h(C-Q)

TxDi hold time

RxDi input setup time

TxDi output delay time

h(C-D)

RxDi input hold time

380

300

150

160

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

168

GZZ SH56 83B <97B0>

MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT

MICROCOMPUTER M30220MA-XXXGP/RP

MASK ROM CONFIRMATION FORM

Mask ROM number

Note : Please complete all items marked .

Checksum code for total EPROM area :

(hex)

(1) Write "FF

to the lined area.

(2) The area from 00000

to 0000F

is for storing

data on the product type name.
The ASCII code for 'M30220MA-' is shown at right.
The data in this table must be written to address
00000

to 0000F

Both address and data are shown in hex.

= 4D

00000

00001

00002

00003

00004

00005

00006

00007

Address

= 2D

00008

00009

0000A

0000B

0000C

0000D

0000E

0000F

Address

EPROM type :

27C201

Address

00000

Product : Area
containing ASCII
code for M30220MA -

ROM(96K)

0000F

00010

27FFF

28000

3FFFF

Microcomputer type No. :

M30220MA-XXXGP

= 30

= 32

= 30

= 4D

= 41

= 33

Supervisor

signature

Receipt

Date :

Section head

signature

Customer

Company

name

Date

issued

Date :

TEL

( )

Issuance

signature

Submitted by

Supervisor

27C401

Address

00000

Product : Area
containing ASCII
code for M30220MA -

ROM(96K)

0000F

00010

67FFF

68000

7FFFF

1. Check sheet

Name the product you order, and choose which to give in, EPROMs or floppy disks.
If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by
means of floppy disks, one floppy disk is required per pattern.

Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.

In the case of EPROMs

M30220MA-XXXRP

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

169

GZZ SH56 83B <97B0>

MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT

MICROCOMPUTER M30220MA-XXXGP/RP

MASK ROM CONFIRMATION FORM

Mask ROM number

Note: The ROM cannot be processed if the type No. written to the EPROM does not match the type No.

in the check sheet.

The ASCII code for the type No. can be written to EPROM addresses 00000

to 0000F

by specifying the

pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.

The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet
for submission to Mitsubishi.
For the M30220MA-XXXRP, submit the 144PFB mark specification sheet. For the M30220MA-XXXGP,
submit the 144P6Q mark specification sheet.

2. Mark specification

3. Usage Conditions

For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.

(1) Which kind of X

-X

OUT

oscillation circuit is used?

Ceramic resonator

Quartz-crystal oscillator

External clock input

Other ( )

What frequency do you use?

f(X

) =

EPROM type

27C201

Code entered in
source program

.SECTION ASCIICODE, ROM DATA
.ORG 0C0000H
.BYTE ' M30220MA- '

27C401

.SECTION ASCIICODE, ROM DATA
.ORG 080000H
.BYTE ' M30220MA- '

Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on
the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that
there is any discrepancy between the contents of these mask files and the ROM data to be burned into
products we produce. Check thoroughly the contents of the mask files you give in.
Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk.

In the case of floppy disks

File code :

(hex)

Microcomputer type No. :

M30220MA-XXXGP

Mask file name :

.MSK (alpha-numeric 8-digit)

M30220MA-XXXRP

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

170

GZZ SH56 83B <97B0>

MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT

MICROCOMPUTER M30220MA-XXXGP/RP

MASK ROM CONFIRMATION FORM

Mask ROM number

4. Special item (Indicate none if there is no specified item)

(2) Which kind of X

CIN

-X

COUT

oscillation circuit is used?

Ceramic resonator

Quartz-crystal oscillator

External clock input

Other ( )

What frequency do you use?

f(X

CIN

) =

(3) Which operating ambient temperature do you use?

10 °C to 75 °C

20 °C to 75 °C

40 °C to 75 °C

10 °C to 85 °C

20 °C to 85 °C

40 °C to 85 °C

(4) Which operating supply voltage do you use?

2.7V to 3.2V

3.2V to 3.7V

3.7V to 4.2V

4.2V to 4.7V

4.7V to 5.2V

5.2V to 5.5V

(5) Do you use I2C (Inter IC) bus function?

Not use

Use

(6) Do you use IE (Inter Equipment) bus function?

Not use

Use

Thank you cooperation.

Description (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

171

Table 1.22.1. Outline performance of the M30220 (flash memory version)

Outline Performance

Table 1.22.1 shows the outline performance of the M30220 (flash memory version).

Item

Flash memory operation mode

Erase block
division

Program method

Erase method

Program/erase control method

Number of commands

Program/erase count

ROM code protect

Performance

Three modes (parallel I/O, standard serial I/O, CPU rewrite)

See Figure 1.22.1

No division (8 K bytes) (Note 3)

In units of words

Collective erase/block erase

Program/erase control by software command

6 commands

100 times

Parallel I/O and standard serial I/O modes are supported.

Note 1: Use a 4.5 - 5.5 V power supply voltage when program/erase.
Note 2: Use a 3.0 - 3.6 V power supply voltage when program/erase.
Note 3: The boot ROM area contains a standard serial I/O mode control program which is stored in it when

shipped from the factory. This area can be erased and programmed in only parallel I/O mode.

User ROM area

Boot ROM area

Power supply voltage

=2.7V to 5.5 V (Note 1)

=2.7V to 3.6 V (Note 2)

Program/erase voltage

=5.0V ± 10%

Description (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

172

Flash Memory

The M30220 (flash memory version) has an internal new DINOR (DIvided bit line NOR) flash memory that

can be rewritten with a single power source when V

is 4.5 to 5.5 V, and 2 power sources when V

is 2.7

to 4.5V.

For this flash memory, three flash memory modes are available in which to read, program, and erase:

parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a program-

mer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit

(CPU). Each mode is detailed in the pages to follow.

The flash memory is divided into several blocks as shown in Figure 1.22.1, so that memory can be erased

one block at a time.

In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash

memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and

standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored

in it when shipped from the factory. However, the user can write a rewrite control program in this area that

suits the user's application system. This boot ROM area can be rewritten in only parallel I/O mode.

Figure 1.22.1. Block diagram of flash memory version

Note 1: The boot ROM area can be rewritten in only parallel input/

output mode. (Access to any other areas is inhibited.)

Note 2: To specify a block, use the optional even address in the

block.

Flash memory

size

Flash memory

start address

128K

byte

0E0000

0F0000

Block 1 : 32K byte

0F8000

Block 0 : 32K byte

User ROM area

8K byte

0DE000

0FFFFF

0DFFFF

Boot ROM area

Block 3 : 32K byte

Block 2 : 32K byte

0E8000

CPU Rewrite Mode (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

173

CPU Rewrite Mode

In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control

of the Central Processing Unit (CPU).

In CPU rewrite mode, only the user ROM area shown in Figure 1.22.1 can be rewritten; the boot ROM area

cannot be rewritten. Make sure the program and block erase commands are issued for only the user ROM

area and each block area.

The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU

rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must

be transferred to any area other than the internal flash memory before it can be executed.

Microcomputer Mode and Boot Mode

The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in

parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard

serial I/O mode becomes unusable.)

See Figure 1.22.1 for details about the boot ROM area.

Normal microcomputer mode is entered when the microcomputer is reset with pulling CNV

pin low. In

this case, the CPU starts operating using the control program in the user ROM area.

_____

When the microcomputer is reset by pulling the P7

(CE) pin high, the CNV

pin high, the CPU starts

operating using the control program in the boot ROM area (program start address is DE000

fixation).

This mode is called the "boot" mode.

Block Address

Block addresses refer to the optional even address of each block. These addresses are used in the block

erase command.

CPU Rewrite Mode (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

174

Outline Performance (CPU Rewrite Mode)

In the CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by

software commands. This rewrite control program must be transferred to internal RAM before it can be

excuted.

The CPU rewrite mode is accessed by applying 5V

10% to the CNV

pin and writing "1" for the CPU

rewrite mode select bit (bit 1 in address 03B4

). Software commands are accepted once the mode is

accessed.

In the CPU rewrite mode, write to and read from software commands and data into even-numbered ad-

dress ("0" for byte address A0) in 16-bit units. Always write 8-bit software commands into even-numbered

address. Commands are ignored with odd-numbered addresses.

Use software commands to control program and erase operations. Whether a program or erase operation

has terminated normally or in error can be verified by reading the status register.

Figure 1.23.1 shows the flash memory control register.

_____

Bit 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During

programming and erase operations, it is "0". Otherwise, it is "1".

Bit 1 is the CPU rewrite mode select bit. When this bit is set to "1" and 5V

10% are applied to the CNV

pin, the M30220 accesses the CPU rewrite mode. Software commands are accepted once the mode is

accessed. In CPU rewrite mode, the CPU becomes unable to access the internal flash memory directly.

Therefore, use the control program in RAM for write to bit 1. To set this bit to "1", it is necessary to write "0"

and then write "1" in succession. The bit can be set to "0" by only writing a "0" .

Bit 2 is the CPU rewrite mode entry flag. This bit can be read to check whether the CPU rewrite mode has

been entered or not.

Bit 3 is the flash memory reset bit used to reset the control circuit of the internal flash memory. This bit is

used when exiting CPU rewrite mode and when flash memory access has failed. When the CPU rewrite

mode select bit is "1", writing "1" for this bit resets the control circuit. To release the reset, it is necessary to

set this bit to "0". If the control circuit is reset while erasing is in progress, a 5 ms wait is needed so that the

flash memory can restore normal operation. Figure 1.23.2 shows a flowchart for setting/releasing the CPU

rewrite mode.

CPU Rewrite Mode (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

175

Flash memory control register

Symbol

Address

When reset

FMCR

03B4

XXXX0001

b2 b1

FMCR0

Bit symbol

Bit name

Function

R W

0: Busy (being written or erased)
1: Ready

CPU rewrite mode
select bit (Note 1)

0: Normal mode
(Software commands invalid)
1: CPU rewrite mode

FMCR1

CPU rewrite mode
entry flag

Flash memory reset bit
(Note 2)

0: Normal operation
1: Reset

Nothing is assigned.
When write, set "0". When read, values are indeterminate.

FMCR2

FMCR3

Note 1: For this bit to be set to "1", the user needs to write a "0" and then a "1" to it in

succession. When it is not this procedure, it is not enacted in "1". This is necessary to
ensure that no interrupt or DMA transfer will be executed during the interval. Use the
control program in the RAM for write to this bit.

Note 2: Effective only when the CPU rewrite mode select bit = 1. Set this bit to 0 subsequently

after setting it to 1 (reset).

RY/BY status flag

0: Normal mode
(Software commands invalid)
1: CPU rewrite mode
(Software commands acceptable)

Figure 1.23.1. Flash memory control registers

CPU Rewrite Mode (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

176

End

Start

Execute read array command or reset flash
memory by setting flash memory reset bit (by
writing "1" and then "0" in succession) (Note 4)

Single-chip mode, or boot mode (Note 1)

Set processor mode register (Note 2)

Using software command execute erase,
program, or other operation

Jump to transferred control program in RAM

(Subsequent operations are executed by control

program in this RAM)

Transfer CPU rewrite mode control

program to internal RAM

Note 1: Apply 5V ± 10 % to CNV

pin by confirmation of CPU rewrite mode entry flag when started operation

with single-chip mode.

Note 2: During CPU rewrite mode, set the main clock frequency as shown below using the main clock divide ratio

select bit (bit 6 at address 0006

and bits 6 and 7 at address 0007

5.0 MHz or less when wait bit (bit 7 at address 0005

) = "0" (without internal access wait state)

10.0 MHz or less when wait bit (bit 7 at address 0005

) = "1" (with internal access wait state)

Note 3: For CPU rewrite mode select bit to be set to "1", the user needs to write a "0" and then a "1" to it in

succession. When it is not this procedure, it is not enacted in "1". This is necessary to ensure that no
interrupt or DMA transfer will be executed during the interval.

Note 4: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to

execute a read array command or reset the flash memory.

Write "0" to CPU rewrite mode select bit

Set CPU rewrite mode select bit to "1" (by
writing "0" and then "1" in succession)(Note 3)

Check the CPU rewrite mode entry flag

Program in ROM

Program in RAM

Figure 1.23.2. CPU rewrite mode set/reset flowchart

CPU Rewrite Mode (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

177

Precautions on CPU Rewrite Mode

Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite

mode.

(1) Operation speed

During CPU rewrite mode, set the main clock frequency as shown below using the main clock divide

ratio select bit (bit 6 at address 0006

and bits 6 and 7 at address 0007

5.0 MHz or less when wait bit (bit 7 at address 0005

) = 0 (without internal access wait state)

10.0 MHz or less when wait bit (bit 7 at address 0005

) = 1 (with internal access wait state)

(2) Instructions inhibited against use

The instructions listed below cannot be used during CPU rewrite mode because they refer to the

internal data of the flash memory:

UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction

(3) Interrupts inhibited against use

_______

The NMI, address match, and watchdog timer interrupts cannot be used during CPU rewrite mode

because they refer to the internal data of the flash memory. If interrupts have their vector in the vari-

able vector table, they can be used by transferring the vector into the RAM area.

(4) Reset

If the control circuit is reset while erasing is in progress, a 5 ms wait is needed so that the flash

memory can restore normal operation. Set a 5 ms wait to release the reset operation.

Also, when the reset has been released, the program execute start address is automatically set to

0DE000

, therefore program so that the execute start address of the boot ROM is 0DE000

(5) Writing in the user ROM area

If power is lost while rewriting blocks that contain the flash rewrite program with the CPU rewrite mode,

those blocks may not be correctly rewritten and it is possible that the flash memory can no longer be

rewritten after that. Therefore, it is recommended to use the standard serial I/O mode or parallel I/O

mode to rewrite these blocks.

CPU Rewrite Mode (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

178

Command

Program

Clear status register

Read array

Read status register

(Note 3)

First bus cycle

Second bus cycle

Write

SRD

Read

Write

Erase all block

Write

(Note 2)

(Note 3)

Block erase

Write

(Note 4)

Mode

Address

Mode

Address

Data

to D

)

Data

to D

)

(Note 5)

Note 1: When a software command is input, the high-order byte of data (D

to D

) is ignored.

Note 2: SRD = Status Register Data
Note 3: WA = Write Address, WD = Write Data
Note 4: BA = Block Address (Enter the optional address of each block that is an even address.)
Note 5: X denotes a given address in the user ROM area (that is an even address).

Cycle number

Software Commands

Table 1.23.1 lists the software commands available with the M30220 (flash memory version).

After setting the CPU rewrite mode select bit to 1, write a software command to specify an erase or

program operation. Note that when entering a software command, the upper byte (D

to D

) is ignored.

The content of each software command is explained below.

Table 1.23.1. List of software commands (CPU rewrite mode)

Read Array Command (FF

)

The read array mode is entered by writing the command code "FF

" in the first bus cycle. When an

even address to be read is input in one of the bus cycles that follow, the content of the specified

address is read out at the data bus (D

), 16 bits at a time.

The read array mode is retained intact until another command is written.

Read Status Register Command (70

)

When the command code "70

" is written in the first bus cycle, the content of the status register is

read out at the data bus (D

) by a read in the second bus cycle.

The status register is explained in the next section.

Clear Status Register Command (50

)

This command is used to clear the bits SR4 to SR5 of the status register after they have been set.

These bits indicate that operation has ended in an error. To use this command, write the command

code "50

" in the first bus cycle.

CPU Rewrite Mode (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

179

Start

Write

Status register

read

Program

completed

YES

Write address
Write data

SR4=0?

Program

error

YES

SR7=1?

RY/BY=1?

Write

Figure 1.23.3. Program flowchart

Program Command (40

)

Program operation starts when the command code "40

" is written in the first bus cycle. Then, if the

address and data to program are written in the 2nd bus cycle, program operation (data programming

and verification) will start.

Whether the write operation is completed can be confirmed by reading the status register or the RY/

_____

BY status flag. When the program starts, the read status register mode is accessed automatically and

the content of the status register is read into the data bus (D0 - D7). The status register bit 7 (SR7) is

set to 0 at the same time the write operation starts and is returned to 1 upon completion of the write

operation. In this case, the read status register mode remains active until the Read Array command

(FF

) is written.

____

The RY/BY status flag is 0 during write operation and 1 when the write operation is completed as is

the status register bit 7.

At program end, program results can be checked by reading the status register.

Erase All Blocks Command (20

/20

)

By writing the command code "20

" in the first bus cycle and the confirmation command code "20

in the second bus cycle that follows, the system starts erase all blocks( erase and erase verify).

Whether the erase all blocks command is terminated can be confirmed by reading the status register

____

or the RY/BY status flag. When the erase all blocks operation starts, the read status register mode is

accessed automatically and the content of the status register can be read out. The status register bit

7 (SR7) is set to 0 at the same time the erase operation starts and is returned to 1 upon completion of

the erase operation. In this case, the read status register mode remains active until the Read Array

command (FF

) is written.

CPU Rewrite Mode (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

180

Write 20

/D0

Block address

Erase completed

YES

Start

Write

SR5=0?

Erase error

YES

:Erase all blocks

:Block erase

SR7=1?

RY/BY=1?

Status register

read

Figure 1.23.4. Erase flowchart

Block Erase Command (20

/D0

)

By writing the command code "20

" in the first bus cycle and the confirmation command code "D0

in the second bus cycle that follows to the block address of a flash memory block, the system initiates

a block erase (erase and erase verify) operation.

Whether the block erase operation is completed can be confirmed by reading the status register or

____

the RY/BY status flag. At the same time the block erase operation starts, the read status register

mode is automatically entered, so the content of the status register can be read out. The status

upon completion of the block erase operation. In this case, the read status register mode remains

active until the Read Array command (FF

____

The RY/BY status flag is 0 during block erase operation and 1 when the block erase operation is

completed as is the status register bit 7.

After the block erase operation is completed, the status register can be read out to know the result of

the block erase operation. For details, refer to the section where the status register is detailed.

____

The RY/BY status flag is 0 during erase operation and 1 when the erase operation is completed as is

the status register bit 7.

At erase all blocks end, erase results can be checked by reading the status register. For details, refer

to the section where the status register is detailed.

CPU Rewrite Mode (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

181

Status Register

The status register shows the operating state of the flash memory and whether erase operations and

programs ended successfully or in error. It can be read in the following ways.

(1) By reading an arbitrary address from the user ROM area after writing the read status register

command (70

)

(2) By reading an arbitrary address from the user ROM area in the period from when the program starts

or erase operation starts to when the read array command (FF

) is input

Table 1.23.2 shows the status register.

Also, the status register can be cleared in the following way.

(1) By writing the clear status register command (50

)

After a reset, the status register is set to "80

Each bit in this register is explained below.

Sequencer status (SR7)

After power-on, the sequencer status is set to 1(ready).

The sequencer status indicates the operating status of the device. This status bit is set to 0 (busy)

during write or erase operation and is set to 1 upon completion of these operations.

Erase status (SR5)

The erase status informs the operating status of erase operation to the CPU. When an erase error

occurs, it is set to 1.

The erase status is reset to 0 when cleared.

Program status (SR4)

The program status informs the operating status of write operation to the CPU. When a write error

occurs, it is set to 1.

The program status is reset to 0 when cleared.

If "1" is written for any of the SR5 or SR4 bits, the program, erase all blocks, and block erase com-

mands are not accepted. Before executing these commands, execute the clear status register com-

mand (50

) and clear the status register.

Also, any commands are not correct, both SR5 and SR4 are set to 1.

CPU Rewrite Mode (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

182

Read status register

SR4=1 and SR5

=1 ?

Command sequence

error (Note 1)

YES

SR5=0?

YES

Block erase error

SR4=0?

YES

Program error

End (block erase, program)

Execute the clear status register command (50

)

to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.

Should a block erase error occur, the block in error
cannot be used.

Note 1: Either SR5 or SR4 may become "0". Take care about it during program debugging.
Note 2: When one of SR5 to SR4 is set to 1, none of the program, erase all blocks, and block

erase commands is accepted. Execute the clear status register command (50

)

before executing these commands.

Should a program error occur, the block in error
cannot be used.

Full Status Check

By performing full status check, it is possible to know the execution results of erase and program

operations. Figure 1.23.5 shows a full status check flowchart and the action to be taken when each

error occurs.

Figure 1.23.5. Full status check flowchart and remedial procedure for errors

Each bit of

SRD

SR4 (bit4)

SR5 (bit5)

SR7 (bit7)

SR6 (bit6)

Status name

Definition

SR1 (bit1)

SR2 (bit2)

SR3 (bit3)

SR0 (bit0)

"1"

"0"

Program status

Erase status

Sequencer status

Reserved

Ready

Busy

Terminated in error

Terminated normally

Reserved

Table 1.23.2. Definition of each bit in status register

Functions To Inhibit Rewriting Flash Memory Version (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

183

Symbol

Address

When reset

ROMCP

0FFFFF

ROM code protect level
2 set bit (Note 1, 2)

00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled

ROM code protect control address

Bit name

Function

Bit symbol

00: Protect removed
01: Protect set bit effective
10: Protect set bit effective
11: Protect set bit effective

00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled

ROM code protect reset
bit (Note 3)

ROM code protect level
1 set bit (Note 1)

ROMCP2

ROMCR

ROMCP1

b3 b2

b5 b4

b7 b6

Note 1: When ROM code protect is turned on, the on-chip flash memory is protected against

readout or modification in parallel input/output mode.

Note 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment

inspection LSI tester, etc. also is inhibited.

Note 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and

ROM code protect level 2. However, since these bits cannot be changed in parallel input/
output mode, they need to be rewritten in serial input/output or some other mode.

Reserved bit

Always set this bit to 1.

1 1

Functions To Inhibit Rewriting Flash Memory Version

To prevent the contents of the flash memory version from being read out or rewritten easily, the device

incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for

use in standard serial I/O mode.

ROM code protect function

The ROM code protect function is used to prohibit reading out or modifying the contents of the flash

memory during parallel I/O mode and is set by using the ROM code protect control address register

(0FFFFF

). Figure 1.23.6 shows the ROM code protect control address (0FFFFF

). (This address ex-

ists in the user ROM area.)

If one of the pair of ROM code protect bits is set to 0, ROM code protect is turned on, so that the contents

of the flash memory version are protected against readout and modification. ROM code protect is imple-

mented in two levels. If level 2 is selected, the flash memory is protected even against readout by a

shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is

selected by default.

If both of the two ROM code protect reset bits are set to "00," ROM code protect is turned off, so that the

contents of the flash memory version can be read out or modified. Once ROM code protect is turned on,

the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/

O or some other mode to rewrite the contents of the ROM code protect reset bits.

Figure 1.23.6. ROM code protect control address

Functions To Inhibit Rewriting Flash Memory Version (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

184

ID Code Check Function

Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID

code sent from the peripheral unit is compared with the ID code written in the flash memory to see if they

match. If the ID codes do not match, the commands sent from the peripheral unit are not accepted. The ID

code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFDF

, 0FFFE3

0FFFEB

, 0FFFEF

, 0FFFF3

, 0FFFF7

, and 0FFFFB

. Write a program which has had the ID code

preset at these addresses to the flash memory.

Figure 1.23.7. ID code store addresses

Reset vector

Watchdog timer vector

Single step vector

Address match vector

BRK instruction vector

Overflow vector

Undefined instruction vector

ID7

ID6

ID5

ID4

ID3

ID2

ID1

DBC vector

NMI vector

0FFFFC

to 0FFFFF

0FFFF8

to 0FFFFB

0FFFF4

to 0FFFF7

0FFFF0

to 0FFFF3

0FFFEC

to 0FFFEF

0FFFE8

to 0FFFEB

0FFFE4

to 0FFFE7

0FFFE0

to 0FFFE3

0FFFDC

to 0FFFDF

4 bytes

Address

Appendix Parallel I/O Mode (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

185

Parallel I/O Mode

The parallel I/O mode inputs and outputs the software commands, addresses and data needed to operate

(read, program, erase, etc.) the internal flash memory. This I/O is parallel.

Use an exclusive programer supporting M30220 (flash memory version).

Refer to the instruction manual of each programer maker for the details of use.

User ROM and Boot ROM Areas

In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 1.22.1 can be rewritten. Both

areas of flash memory can be operated on in the same way.

Program and block erase operations can be performed in the user ROM area. The user ROM area and its

blocks are shown in Figure 1.22.1.

The boot ROM area is 8 Kbytes in size. In parallel I/O mode, it is located at addresses 0DE000

through

0DFFFF

. Make sure program and block erase operations are always performed within this address

range. (Access to any location outside this address range is prohibited.)

In the boot ROM area, an erase block operation is applied to only one 8 Kbyte block. The boot ROM area

has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory.

Therefore, using the device in standard serial input/output mode, you do not need to write to the boot

ROM area.

Appendix Standard Serial I/O Mode (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

186

Pin Description

Apply a 3.0 - 3.6 V (Note 2) or 4.5 - 5.5 V (Note 3) voltage on the Vcc
pin, and 0 V voltage on the Vss pin.

CNV

Connect to V

when V

= 4.5V to 5.5 V.

Connect to Vpp (=4.5 V to 5.5 V) when V

= 3.0V to 3.6 V.

RESET

Reset input pin. While reset is "L" level, a 20 cycle or longer clock
must be input to X

pin.

Connect a ceramic resonator or crystal oscillator between X

and

OUT

pins. To input an externally generated clock, input it to X

and open X

OUT

pin.

OUT

, AV

REF

Connect AV

to V

and AV

to V

, respectively.

Enter the reference voltage for AD from this pin.

to P0

Input "H" or "L" level signal or open.

to P1

Input "H" or "L" level signal or open.

to P2

Input "H" or "L" level signal or open.

to P3

Input "H" or "L" level signal or open.

to P4

Input "H" or "L" level signal or open.

to P7

Input "H" or "L" level signal or open.

Input "H" level signal.

to P6

Input "H" or "L" level signal or open.

Standard serial mode 1: BUSY signal output pin
Standard serial mode 2: Monitors the program operation check

Serial data input pin

Serial data output pin

to P8

Input "H" or "L" level signal or open.

to P9

Input "H" or "L" level signal or open.

P10

to P10

Input "H" or "L" level signal or open.

Name

Power input

CNV

Reset input

Clock input

Clock output

Analog power supply input

Reference voltage input

Input port P0

Input port P1

Input port P2

Input port P3

Input port P4

Input port P7

CE input

NMI input

Input port P6

BUSY output

SCLK input

RxD input

TxD output

Input port P8

Input port P9

Input port P10

I/O

Standard serial mode 1: Serial clock input pin
Standard serial mode 2: Input "L".

Connect a ceramic resonator or crystal oscillator between X

and

OUT

pins. To input an externally generated clock, input it to X

and open X

OUT

pin.

OUT

Clock input

Clock output

CIN

Connect a crystal oscillator between X

CIN

and X

COUT

pins. To input

an externally generated clock, input it to X

CIN

pin and open X

COUT

pin.

COUT

Sub-clock input

Sub-clock output

to P5

Input "H" or "L" level signal or open.

Input port P5

Connect this pin to Vcc.

P11

to P11

Input "H" or "L" level signal or open.

Input port P11

P12

to P12

Input "H" or "L" level signal or open.

Input port P12

P13

to P13

Input "H" or "L" level signal or open.

Input port P13

SEG

to SEG

Open when not used LCD control circuit.

Segment output

COM

to COM

Open when not used LCD control circuit.

Common output

to V

Input LCD power source. However, do not input the power when the
power supply voltages for V

and LCD are different.

Power supply input for LCD

to C

Charge-pump capacitor
pin

Connect a condenser between C

and C

when used LCD charge-

pump.

Note 1: About the unused pins, see the example of processing for unused pins in the single-chip mode.
Note 2: The power supply voltage is V

=2.7 - 3.6 V in the single-chip mode.

Note 3: The power supply voltage is V

=2.7 - 5.5 V in the single-chip mode.

Pin functions (Flash memory standard serial I/O mode) (Note 1)

Appendix Standard Serial I/O Mode (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

187

Figure 1.25.1. Pin connections for serial I/O mode (1)

Note 1: Connect oscillator circuit.
Note 2: Connect to V

when V

= 4.5V to 5.5 V.

Connect to Vpp (=4.5V to 5.5 V) when V

= 3.0V to 3.6 V.

SET

/IN

/TA3

OUT

/INT4

/TA2

/TA1

/TA2

OUT

/
SEG

SEG

REF

Vss

SEG

CNV

COM

/IN

110

113

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

109

111

112

144

108

107

106

105

104

103

102

100

101

SEG

/IN

/TA0

/TA1

OUT

/TA0

OUT

/RxD

x
D

SEG

SEG8

/AN

P10

/SEG

P10

/SEG

P10

/SEG

SEG

/CLK

/TB3

/TB0

/TB1

/TB2

/TB5

/TB4

/INT3

/CK

OUT

/TA3

/INT4

P13

/DA

P13

/AD

TRG

/DA

P13

/DA

/KI

/CTS

/RTS

M30220 flash memory version

(144P6Q-A, 144PFB-A)

BUSY

RxD

SCLK

TxD

RESET

Note 1

Note 2

Mode setup method

Signal
CNVss
RESET
CE

Value

4.5 to 5.5V
Vss Vcc
Vcc

Appendix Standard Serial I/O Mode (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

188

Standard serial I/O mode

The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to

operate (read, program, erase, etc.) the internal flash memory. This I/O is serial. There are actually two

standard serial I/O modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. Both

modes require a purpose-specific peripheral unit.

The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory

rewrite (uses the CPU's rewrite mode), rewrite data input and so forth. The standard serial I/O mode is

_____

started by connecting "H" to the P7

(CE) pin and "H" to the CNV

pin (when V

= 4.5 V to 5.5 V, connect

to V

; when V

= 2.7 V to 4.5 V, supply 4.5 V to 5.5 V to Vpp from an external source), and releasing the

reset operation. (In the ordinary command mode, set CNVss pin to "L" level.)

This control program is written in the boot ROM area when the product is shipped from Mitsubishi. Accord-

ingly, make note of the fact that the standard serial I/O mode cannot be used if the boot ROM area is

rewritten in the parallel I/O mode. Figure 1.25.1 shows the pin connections for the standard serial I/O mode.

Serial data I/O uses UART0 and transfers the data serially in 8-bit units. Standard serial I/O switches

between mode 1 (clock synchronized) and mode 2 (clock asynchronized) according to the level of CLK

when the reset is released.

To use standard serial I/O mode 1 (clock synchronized), set the CLK

pin to "H" level and release the reset.

The operation uses the four UART0 pins CLK

, RxD

, TxD

and RTS

(BUSY). The CLK

pin is the transfer

clock input pin through which an external transfer clock is input. The TxD

pin is for CMOS output. The

RTS

(BUSY) pin outputs an "L" level when ready for reception and an "H" level when reception starts.

To use standard serial I/O mode 2 (clock asynchronized), set the CLK

pin to "L" level and release the

reset. The operation uses the two UART0 pins RxD

and TxD

In the standard serial I/O mode, only the user ROM area indicated in Figure 1.22.1 can be rewritten. The

boot ROM cannot.

In the standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, com-

mands sent from the peripheral unit (programmer) are not accepted unless the ID code matches.

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

189

Overview of standard serial I/O mode 1 (clock synchronized)

In standard serial I/O mode 1, software commands, addresses and data are input and output between the

MCU and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial I/O (UART0).

Standard serial I/O mode 1 is engaged by releasing the reset with the P6

(CLK

) pin "H" level.

In reception, software commands, addresses and program data are synchronized with the rise of the

transfer clock that is input to the CLK

pin, and are then input to the MCU via the RxD

pin. In transmis-

sion, the read data and status are synchronized with the fall of the transfer clock, and output from the

TxD

pin.

The TxD

pin is for CMOS output. Transfer is in 8-bit units with LSB first.

When busy, such as during transmission, reception, erasing or program execution, the RTS

(BUSY) pin

is "H" level. Accordingly, always start the next transfer after the RTS

(BUSY) pin is "L" level.

Also, data and status registers in memory can be read after inputting software commands. Status, such

as the operating state of the flash memory or whether a program or erase operation ended successfully or

not, can be checked by reading the status register. Here following are explained software commands,

status registers, etc.

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

190

Software Commands

Table 1.25.1 lists software commands. In the standard serial I/O mode 1, erase operations, programs and

reading are controlled by transferring software commands via the RxD

pin. Software commands are

explained here below.

Table 1.25.1. Software commands (Standard serial I/O mode 1)

Control command

2nd byte 3rd byte 4th byte 5th byte 6th byte

Page read

Page program

Block erase

Erase all blocks

Read status register

Clear status register

ID check function

Download function

Version data output function

Boot ROM area output
function

Read check data

Address
(middle)

SRD

output

Address

(low)

Size (low)

Version

data

output

Address
(middle)

Check

data (low)

Address

(high)

Address

(high)

Address

(high)

SRD1

output

Address
(middle)

Size

(high)

Version

data

output

Address

(high)

Check

data

(high)

Data

output

Data

input

Address

(high)

Check-

sum

Version

data

output

Data

output

Data

output

Data

input

ID size

Data

input

Version

data

output

Data

output

Data

output

Data

input

ID1

required

number

of times

Version

data

output

Data

output

Data

output to

259th byte

Data input

to 259th

byte

To ID7

Version

data

output to

9th byte

Data

output to

259th

byte

When ID is
not verified

Not

acceptable

Not

acceptable

Not

acceptable

Not

acceptable

Acceptable

Not

acceptable

Acceptable

Not

acceptable

Acceptable

Not

acceptable

Not

acceptable

1st byte

transfer

Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is trans-

ferred from the peripheral unit to the flash memory microcomputer.

Note 2: SRD refers to status register data. SRD1 refers to status register 1 data.

Note 3: All commands can be accepted when the flash memory is totally blank.

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

191

Page Read Command

This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a

time. Execute the page read command as explained here following.

(1) Transfer the "FF

" command code with the 1st byte.

(2) Transfer addresses A

to A

and A

to A

with the 2nd and 3rd bytes respectively.

(3) From the 4th byte onward, data (D

) for the page (256 bytes) specified with addresses A

will be output sequentially from the smallest address first in sync with the fall of the clock.

Figure 1.25.2. Timing for page read

Read Status Register Command

This command reads status information. When the "70

" command code is sent with the 1st byte, the

contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1

(SRD1) specified with the 3rd byte are read.

Figure 1.25.3. Timing for reading the status register

data0

data255

CLK0

RxD0

TxD0

RTS0(BUSY)

(M16C reception data)

(M16C transmit data)

SRD

output

SRD1

output

CLK0

RxD0

TxD0

RTS0(BUSY)

(M16C reception data)

(M16C transmit data)

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

192

Clear Status Register Command

This command clears the bits (SR4SR5) which are set when the status register operation ends in

error. When the "50

" command code is sent with the 1st byte, the aforementioned bits are cleared.

When the clear status register operation ends, the RTS

(BUSY) signal changes from the "H" to the

"L" level.

Figure 1.25.4. Timing for clearing the status register

Page Program Command

This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a

time. Execute the page program command as explained here following.

(1) Transfer the "41

" command code with the 1st byte.

(2) Transfer addresses A

to A

and A

to A

with the 2nd and 3rd bytes respectively.

(3) From the 4th byte onward, as write data (D

) for the page (256 bytes) specified with addresses

to A

is input sequentially from the smallest address first, that page is automatically written.

When reception setup for the next 256 bytes ends, the RTS

(BUSY) signal changes from the "H" to

the "L" level. The result of the page program can be known by reading the status register. For more

information, see the section on the status register.

CLK0

RxD0

TxD0

RTS0(BUSY)

(M16C reception data)

(M16C transmit data)

CLK0

RxD0

TxD0

RTS0(BUSY)

data0

data255

(M16C reception data)

(M16C transmit data)

Figure 1.25.5. Timing for the page program

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

193

Block Erase Command

This command erases the data in the specified block. Execute the block erase command as explained

here following.

(1) Transfer the "20

" command code with the 1st byte.

(2) Transfer addresses A

to A

and A

to A

with the 2nd and 3rd bytes respectively.

(3) Transfer the verify command code "D0

" with the 4th byte. With the verify command code, the

erase operation will start for the specified block in the flash memory. Write the optional even

address of the specified block for addresses A

to A

When block erasing ends, the RTS

(BUSY) signal changes from the "H" to the "L" level. After block

erase ends, the result of the block erase operation can be known by reading the status register. For

more information, see the section on the status register.

CLK0

RxD0

TxD0

RTS0(BUSY)

(M16C reception data)

(M16C transmit data)

Figure 1.25.6. Timing for block erasing

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

194

Erase All Blocks Command

This command erases the content of all blocks. Execute the erase all blocks command as explained

here following.

(1) Transfer the "A7

" command code with the 1st byte.

(2) Transfer the verify command code "D0

" with the 2nd byte. With the verify command code, the

erase operation will start and continue for all blocks in the flash memory.

When block erasing ends, the RTS

(BUSY) signal changes from the "H" to the "L" level. The result of the

erase operation can be known by reading the status register.

CLK0

RxD0

TxD0

RTS0(BUSY)

(M16C reception data)

(M16C transmit data)

Figure 1.25.7. Timing for erasing all blocks

Download Command

This command downloads a program to the RAM for execution. Execute the download command as

explained here following.

(1) Transfer the "FA

" command code with the 1st byte.

(2) Transfer the program size with the 2nd and 3rd bytes.

(3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th

byte onward.

(4) The program to execute is sent with the 5th byte onward.

When all data has been transmitted, if the check sum matches, the downloaded program is executed.

The size of the program will vary according to the internal RAM.

Program

data

Program

data

Data size (high)

Data size (low)

Check
sum

CLK0

RxD0

TxD0

RTS0(BUSY)

(M16C reception data)

(M16C transmit data)

Figure 1.25.8. Timing for download

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

195

Version Information Output Command

This command outputs the version information of the control program stored in the boot area. Execute

the version information output command as explained here following.

(1) Transfer the "FB

" command code with the 1st byte.

(2) The version information will be output from the 2nd byte onward. This data is composed of 8

ASCII code characters.

Figure 1.25.9. Timing for version information output

Boot ROM Area Output Command

This command outputs the control program stored in the boot ROM area in one page blocks (256

bytes). Execute the boot ROM area output command as explained here following.

(1) Transfer the "FC

" command code with the 1st byte.

(2) Transfer addresses A

to A

and A

to A

with the 2nd and 3rd bytes respectively.

(3) From the 4th byte onward, data (D

) for the page (256 bytes) specified with addresses A

will be output sequentially from the smallest address first, in sync with the fall of the clock.

Figure 1.25.10. Timing for boot ROM area output

'X'

'V'

'E'

'R'

CLK0

RxD0

TxD0

RTS0(BUSY)

(M16C reception data)

(M16C transmit data)

data0

data255

CLK0

RxD0

TxD0

RTS0(BUSY)

(M16C reception data)

(M16C transmit data)

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

196

ID Check

This command checks the ID code. Execute the boot ID check command as explained here following.

(1) Transfer the "F5

" command code with the 1st byte.

(2) Transfer addresses A

to A

, A

to A

and A

to A

of the 1st byte of the ID code with the 2nd,

3rd and 4th bytes respectively.

(3) Transfer the number of data sets of the ID code with the 5th byte.

(4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code.

Figure 1.25.11. Timing for the ID check

ID Code

When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written

in the flash memory are compared to see if they match. If the codes do not match, the command sent

from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte,

addresses 0FFFDF

, 0FFFE3

, 0FFFEB

, 0FFFEF

, 0FFFF3

, 0FFFF7

and 0FFFFB

. Write

a program into the flash memory, which already has the ID code set for these addresses.

Figure 1.25.12. ID code storage addresses

ID size

ID1

ID7

CLK0

RxD0

TxD0

RTS0(BUSY)

(M16C reception

data)

(M16C transmit

data)

Reset vector

Watchdog timer vector

Single step vector

Address match vector

BRK instruction vector

Overflow vector

Undefined instruction vector

ID7

ID6

ID5

ID4

ID3

ID2

ID1

DBC vector

NMI vector

0FFFFC

to 0FFFFF

0FFFF8

to 0FFFFB

0FFFF4

to 0FFFF7

0FFFF0

to 0FFFF3

0FFFEC

to 0FFFEF

0FFFE8

to 0FFFEB

0FFFE4

to 0FFFE7

0FFFE0

to 0FFFE3

0FFFDC

to 0FFFDF

4 bytes

Address

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

197

Read Check Data

This command reads the check data that confirms that the write data, which was sent with the page

program command, was successfully received.

(1) Transfer the "FD

" command code with the 1st byte.

(2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd.

To use this read check data command, first execute the command and then initialize the check data.

Next, execute the page program command the required number of times. After that, when the read

check command is executed again, the check data for all of the read data that was sent with the page

program command during this time is read. Check data adds write data in 1 byte units and obtains the

two's-compliment of the insignificant 2 bytes of the accumulated data.

Figure 1.25.13. Timing for the read check data

Check data (low)

CLK0

RxD0

TxD0

RTS0(BUSY)

(M16C reception data)

(M16C transmit data)

Check data (high)

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

198

Status Register (SRD)

The status register indicates operating status of the flash memory and status such as whether an erase

operation or a program ended successfully or in error. It can be read by writing the read status register

command (70

). Also, the status register is cleared by writing the clear status register command (50

Table 1.25.2 gives the definition of each status register bit. After clearing the reset, the status register

outputs "80

Table 1.25.2. Status register (SRD)

Sequencer status (SR7)

After power-on, the sequencer status is set to 1(ready).

The sequencer status indicates the operating status of the device. This status bit is set to 0 (busy)

during write or erase operation and is set to 1 upon completion of these operations.

Erase Status (SR5)

The erase status reports the operating status of the auto erase operation. If an erase error occurs, it is

set to "1". When the erase status is cleared, it is set to "0".

Program Status (SR4)

The program status reports the operating status of the auto write operation. If a write error occurs, it is

set to "1". When the program status is cleared, it is set to "0".

SRD0 bits

SR7 (bit7)

SR6 (bit6)

SR5 (bit5)

SR4 (bit4)

SR3 (bit3)

SR2 (bit2)

SR1 (bit1)

SR0 (bit0)

Status name

Sequencer status

Reserved

Erase status

Program status

Reserved

Definition

"1" "0"

Ready

Terminated in error

Busy

Terminated normally

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

199

Status Register 1 (SRD1)

Status register 1 indicates the status of serial communications, results from ID checks and results from

check sum comparisons. It can be read after the SRD by writing the read status register command (70

Also, status register 1 is cleared by writing the clear status register command (50

Table 1.25.3 gives the definition of each status register 1 bit. "00

" is output when power is turned ON

and the flag status is maintained even after the reset.

Table 1.25.3. Status register 1 (SRD1)

Boot Update Completed Bit (SR15)

This flag indicates whether the control program was downloaded to the RAM or not, using the down-

load function.

Check Sum Match Bit (SR12)

This flag indicates whether the check sum matches or not when a program, is downloaded for execu-

tion using the download function.

ID Check Completed Bits (SR11 and SR10)

These flags indicate the result of ID checks. Some commands cannot be accepted without an ID

check.

Data Receive Time Out (SR9)

This flag indicates when a time out error is generated during data reception. If this flag is attached

during data reception, the received data is discarded and the microcomputer returns to the command

wait state.

SRD1 bits

SR15 (bit7)

SR14 (bit6)

SR13 (bit5)

SR12 (bit4)

SR11 (bit3)

SR10 (bit2)

SR9 (bit1)

SR8 (bit0)

Status name

Boot update completed bit

Reserved

Check sum match bit

ID check completed bits

Data receive time out

Reserved

Definition

"1" "0"

Update co

mpleted

Match

00
01
10
11

Not update

Mismatch

Normal operation

Not verified
Verification mismatch
Reserved
Verified

Time out

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

200

Full Status Check

Results from executed erase and program operations can be known by running a full status check. Figure

1.25.14 shows a flowchart of the full status check and explains how to remedy errors which occur.

Read status register

SR4=1 and SR5

=1 ?

Command sequence

error (Note 1)

YES

SR5=0?

YES

Block erase error

SR4=0?

YES

Program error

End (block erase, program)

Execute the clear status register command (50

)

to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.

Should a block erase error occur, the block in error
cannot be used.

Note 1: Either SR5 or SR4 may become "0". Take care about it during program debugging.
Note 2: When one of SR5 to SR4 is set to 1, none of the program, erase all blocks, and block

erase commands is accepted. Execute the clear status register command (50

)

before executing these commands.

Should a program error occur, the block in error
cannot be used.

Figure 1.25.14. Full status check flowchart and remedial procedure for errors

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

201

Example Circuit Application for The Standard Serial I/O Mode 1

The below figure shows a circuit application for the standard serial I/O mode 1. Control pins will vary

according to programmer, therefore see the peripheral unit manual for more information.

Figure 1.25.15. Example circuit application for the standard serial I/O mode 1

RTS

(BUSY)

CLK

CNVss

Clock input

BUSY output

Data input

Data output

M30220 flash

(1) Control pins and external circuitry will vary according to peripheral unit. For more information,
see the peripheral unit manual.
(2) In this example, the Vpp power supply is supplied from an external source (writer). To use the
user's power source, connect to 4.5V to 5.5 V.

VPP power
source input

NMI

(CE)

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

202

Overview of standard serial I/O mode 2 (clock asynchronized)

In standard serial I/O mode 2, software commands, addresses and data are input and output between the

MCU and peripheral units (serial programer, etc.) using 2-wire clock-asynchronized serial I/O (UART0).

Standard serial I/O mode 2 is engaged by releasing the reset with the P6

(CLK

) pin "L" level.

The TxD

pin is for CMOS output. Data transfer is in 8-bit units with LSB first, 1 stop bit and parity OFF.

After the reset is released, connections can be established at 9,600 bps when initial communications (Fig-

ure 1.25.16) are made with a peripheral unit. However, this requires a main clock with a minimum 2 MHz

input oscillation frequency. Baud rate can also be changed from 9,600 bps to 19,200, 38,400 or 57,600 bps

by executing software commands. However, communication errors may occur because of the oscillation

frequency of the main clock. If errors occur, change the main clock's oscillation frequency and the baud

rate.

After executing commands from a peripheral unit that requires time to erase and write data, as with erase

and program commands, allow a sufficient time interval or execute the read status command and check

how processing ended, before executing the next command.

Data and status registers in memory can be read after transmitting software commands. Status, such as

the operating state of the flash memory or whether a program or erase operation ended successfully or not,

can be checked by reading the status register. Here following are explained initial communications with

peripheral units, how frequency is identified and software commands.

Initial communications with peripheral units

After the reset is released, the bit rate generator is adjusted to 9,600 bps to match the oscillation fre-

quency of the main clock, by sending the code as prescribed by the protocol for initial communications

with peripheral units (Figure 1.25.16).

(1) Transmit "B0

" from a peripheral unit. If the oscillation frequency input by the main clock is 10 MHz,

the MCU with internal flash memory outputs the "B0

" check code. If the oscillation frequency is

anything other than 10 MHz, the MCU does not output anything.

(2) Transmit "00

" from a peripheral unit 16 times. (The MCU with internal flash memory sets the bit

rate generator so that "00

" can be successfully received.)

(3) The MCU with internal flash memory outputs the "B0

" check code and initial communications end

successfully *

. Initial communications must be transmitted at a speed of 9,600 bps and a transfer

interval of a minimum 15 ms. Also, the baud rate at the end of initial communications is 9,600 bps.

*1. If the peripheral unit cannot receive "B0

" successfully, change the oscillation frequency of the main clock.

Figure 1.25.16. Peripheral unit and initial communication

MCU with internal

flash memory

Peripheral unit

(1) Transfer "B0

If the oscillation frequency input
by the main clock is 10 MHz, the
MCU outputs "B0

". If other than

10 MHz, the MCU does not
output anything.

(2) Transfer "00

" 16 times

At least 15ms
transfer interval

1st

2nd

15 th

16th

(3) Transfer check code "B0

"B0

"00

"B0

"00

Reset

The bit rate generator setting completes (9600bps)

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

203

How frequency is identified

When "00

" data is received 16 times from a peripheral unit at a baud rate of 9,600 bps, the value of the

bit rate generator is set to match the operating frequency (2 - 10 MHz). The highest speed is taken from

the first 8 transmissions and the lowest from the last 8. These values are then used to calculate the bit

rate generator value for a baud rate of 9,600 bps.

Baud rate cannot be attained with some operating frequencies. Table 1.25.4 gives the operation fre-

quency and the baud rate that can be attained for.

Table 1.25.4 Operation frequency and the baud rate

Operation frequency

(MH

)

Baud rate

9,600bps

Baud rate

19,200bps

Baud rate

38,400bps

Baud rate

57,600bps

10MH

8MH

7.3728MH

6MH

5MH

4.5MH

4.194304MH

4MH

3.58MH

3MH

2MH

: Communications possible

: Communications not possible

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

204

Software Commands

Table 1.25.5 lists software commands. In the standard serial I/O mode 2, erase operations, programs and

reading are controlled by transferring software commands via the RxD

pin. Standard serial I/O mode 2

adds four transmission speed commands - 9,600, 19,200, 38,400 and 57,600 bps - to the software com-

mands of standard serial I/O mode 1. Software commands are explained here below.

Table 1.25.5. Software commands (Standard serial I/O mode 2)

Control command

2nd byte 3rd byte 4th byte 5th byte 6th byte

Page read

Page program

Block erase

Erase all unlocked blocks

Read status register

Clear status register

ID check function

Download function

Version data output function

Boot ROM area output

function

Read check data

Baud rate 9600

Baud rate 19200

Baud rate 38400

Baud rate 57600

Address
(middle)

SRD

output

Address

(low)

Size (low)

Version

data

output

Address
(middle)

Check

data (low)

Address

(high)

Address

(high)

Address

(high)

SRD1

output

Address
(middle)

Size

(high)

Version

data

output

Address

(high)

Check

data

(high)

Data

output

Data

input

Address

(high)

Check-

sum

Version

data

output

Data

output

Data

output

Data

input

ID size

Data

input

Version

data

output

Data

output

Data

output

Data

input

ID1

required

number

of times

Version

data

output

Data

output

Data

output to

259th byte

Data input

to 259th

byte

To ID7

Version

data

output to

9th byte

Data

output to

259th byte

When ID is
not verified

Not

acceptable

Not

acceptable

Not

acceptable

Not

acceptable

Acceptable

Not

acceptable

Acceptable

Not

acceptable

Acceptable

Not

acceptable

Not

acceptable

Acceptable

1st byte

transfer

Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is trans-

ferred from the peripheral unit to the flash memory microcomputer.

Note 2: SRD refers to status register data. SRD1 refers to status register 1 data.

Note 3: All commands can be accepted when the flash memory is totally blank.

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

205

Page Read Command

This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a

time. Execute the page read command as explained here following.

(1) Transfer the "FF

" command code with the 1st byte.

(2) Transfer addresses A

to A

and A

to A

with the 2nd and 3rd bytes respectively.

(3) From the 4th byte onward, data (D

) for the page (256 bytes) specified with addresses A

will be output sequentially from the smallest address first.

Figure 1.25.17. Timing for page read

Read Status Register Command

This command reads status information. When the "70

" command code is sent with the 1st byte, the

contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1

(SRD1) specified with the 3rd byte are read.

Figure 1.25.18. Timing for reading the status register

data0

data255

RxD0

TxD0

(M16C reception data)

(M16C transmit data)

SRD

output

SRD1

output

RxD0

TxD0

(M16C reception data)

(M16C transmit data)

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

206

Clear Status Register Command

This command clears the bits (SR4SR5) which are set when the status register operation ends in

error. When the "50

" command code is sent with the 1st byte, the aforementioned bits are cleared.

Figure 1.25.19. Timing for clearing the status register

Page Program Command

This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a

time. Execute the page program command as explained here following.

(1) Transfer the "41

" command code with the 1st byte.

(2) Transfer addresses A

to A

and A

to A

with the 2nd and 3rd bytes respectively.

(3) From the 4th byte onward, as write data (D

) for the page (256 bytes) specified with addresses

to A

is input sequentially from the smallest address first, that page is automatically written.

The result of the page program can be known by reading the status register. For more information,

see the section on the status register.

RxD0

TxD0

(M16C reception data)

(M16C transmit data)

RxD0

TxD0

data0

data255

(M16C reception data)

(M16C transmit data)

Figure 1.25.20. Timing for the page program

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

207

Erase All Blocks Command

This command erases the content of all blocks. Execute the erase all blocks command as explained

here following.

(1) Transfer the "A7

" command code with the 1st byte.

(2) Transfer the verify command code "D0

" with the 2nd byte. With the verify command code, the

erase operation will start and continue for all blocks in the flash memory.

The result of the erase operation can be known by reading the status register.

RxD0

TxD0

(M16C reception data)

(M16C transmit data)

Block Erase Command

This command erases the data in the specified block. Execute the block erase command as explained

here following.

(1) Transfer the "20

" command code with the 1st byte.

(2) Transfer addresses A

to A

and A

to A

with the 2nd and 3rd bytes respectively.

(3) Transfer the verify command code "D0

" with the 4th byte. With the verify command code, the

erase operation will start for the specified block in the flash memory. Write the optional even

address of the specified block for addresses A

to A

After block erase ends, the result of the block erase operation can be known by reading the status

RxD0

TxD0

(M16C reception data)

(M16C transmit data)

Figure 1.25.21. Timing for block erasing

Figure 1.25.22. Timing for erasing all blocks

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

208

Download Command

This command downloads a program to the RAM for execution. Execute the download command as

explained here following.

(1) Transfer the "FA

" command code with the 1st byte.

(2) Transfer the program size with the 2nd and 3rd bytes.

(3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th

byte onward.

(4) The program to execute is sent with the 5th byte onward.

When all data has been transmitted, if the check sum matches, the downloaded program is executed.
The size of the program will vary according to the internal RAM.

Program

data

Program

data

Data size (high)

Data size (low)

Check
sum

RxD0

TxD0

(M16C reception data)

(M16C transmit data)

Figure 1.25.23. Timing for download

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

209

Version Information Output Command

This command outputs the version information of the control program stored in the boot area. Execute

the version information output command as explained here following.

(1) Transfer the "FB

" command code with the 1st byte.

(2) The version information will be output from the 2nd byte onward. This data is composed of 8

ASCII code characters.

Figure 1.25.24. Timing for version information output

Boot ROM Area Output Command

This command outputs the control program stored in the boot ROM area in one page blocks (256

bytes). Execute the boot ROM area output command as explained here following.

(1) Transfer the "FC

" command code with the 1st byte.

(2) Transfer addresses A

to A

and A

to A

with the 2nd and 3rd bytes respectively.

(3) From the 4th byte onward, data (D

) for the page (256 bytes) specified with addresses A

will be output sequentially from the smallest address first.

Figure 1.25.25. Timing for boot ROM area output

'X'

'V'

'E'

'R'

RxD0

TxD0

(M16C reception data)

(M16C transmit data)

data0

data255

RxD0

TxD0

(M16C reception data)

(M16C transmit data)

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

210

ID Check

This command checks the ID code. Execute the boot ID check command as explained here following.

(1) Transfer the "F5

" command code with the 1st byte.

(2) Transfer addresses A

to A

, A

to A

and A

to A

of the 1st byte of the ID code with the 2nd,

3rd and 4th bytes respectively.

(3) Transfer the number of data sets of the ID code with the 5th byte.

(4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code.

Figure 1.25.26. Timing for the ID check

ID Code

When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written

in the flash memory are compared to see if they match. If the codes do not match, the command sent

from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte,

addresses 0FFFDF

, 0FFFE3

, 0FFFEB

, 0FFFEF

, 0FFFF3

, 0FFFF7

and 0FFFFB

. Write

a program into the flash memory, which already has the ID code set for these addresses.

Figure 1.25.27. ID code storage addresses

ID size

ID1

ID7

RxD0

TxD0

(M16C reception

data)

(M16C transmit

data)

Reset vector

Watchdog timer vector

Single step vector

Address match vector

BRK instruction vector

Overflow vector

Undefined instruction vector

ID7

ID6

ID5

ID4

ID3

ID2

ID1

DBC vector

NMI vector

0FFFFC

to 0FFFFF

0FFFF8

to 0FFFFB

0FFFF4

to 0FFFF7

0FFFF0

to 0FFFF3

0FFFEC

to 0FFFEF

0FFFE8

to 0FFFEB

0FFFE4

to 0FFFE7

0FFFE0

to 0FFFE3

0FFFDC

to 0FFFDF

4 bytes

Address

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

211

Read Check Data

This command reads the check data that confirms that the write data, which was sent with the page

program command, was successfully received.

(1) Transfer the "FD

" command code with the 1st byte.

(2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd.

To use this read check data command, first execute the command and then initialize the check data.

Next, execute the page program command the required number of times. After that, when the read

check command is executed again, the check data for all of the read data that was sent with the page

program command during this time is read. Check data adds write data in 1 byte units and obtains the

two's-compliment of the insignificant 2 bytes of the accumulated data.

Figure 1.25.28. Timing for the read check data

Check data (low)

RxD0

TxD0

(M16C reception data)

(M16C transmit data)

Check data (high)

Baud Rate 9600

This command changes baud rate to 9,600 bps. Execute it as follows.

(1) Transfer the "B0

" command code with the 1st byte.

(2) After the "B0

" check code is output with the 2nd byte, change the baud rate to 9,600 bps.

Figure 1.25.29. Timing of baud rate 9600

RxD0

TxD0

(M16C reception data)

(M16C transmit data)

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

212

Baud Rate 19200

This command changes baud rate to 19,200 bps. Execute it as follows.

(1) Transfer the "B1

" command code with the 1st byte.

(2) After the "B1

" check code is output with the 2nd byte, change the baud rate to 19,200 bps.

Figure 1.25.30. Timing of baud rate 19200

Baud Rate 38400

This command changes baud rate to 38,400 bps. Execute it as follows.

(1) Transfer the "B2

" command code with the 1st byte.

(2) After the "B2

" check code is output with the 2nd byte, change the baud rate to 38,400 bps.

Figure 1.25.31. Timing of baud rate 38400

Baud Rate 57600

This command changes baud rate to 57,600 bps. Execute it as follows.

(1) Transfer the "B3

" command code with the 1st byte.

(2) After the "B3

" check code is output with the 2nd byte, change the baud rate to 57,600 bps.

Figure 1.25.32. Timing of baud rate 57600

RxD0

TxD0

(M16C reception data)

(M16C transmit data)

RxD0

TxD0

(M16C reception data)

(M16C transmit data)

RxD0

TxD0

(M16C reception data)

(M16C transmit data)

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timing (Flash memory version)

214

Absolute maximum ratings

Operating ambient temperature (Note)

Parameter

Unit

Input
voltage

RESET,

Analog supply voltage

Supply voltage

Output
voltage

-0.3 to Vcc+0.3

- 0.3 to Vcc+0.3

Power dissipation

Storage temperature

Ta = 25

- 0.3 to 6.5

Rated value

- 0.3 to 6.5

Condition

AVcc

Vcc

stg

opr

Symbol

- 40 to 150

300

25±5

to P3

,P4

to P4

, P5

to P5

to P0

to P1

to P2

to P4

, P5

to P5

to P6

to P1

to P2

, P3

to P3

Vcc=AVcc

to P6

,P7

to P7

, P8

to P8

REF

, X

to P9

, P10

to P10

, P11

to P11

P12

to P12

, P13

to P13

- 0.3 to V

to V

to 6.5

, P7

, C

- 0.3 to 6.5

to P7

, P8

to P8

to P9

P13

to P13

OUT

to P0

P10

to P10

P11

to P11

P12

to P12

- 0.3 to Vcc

When output port

When segment otput

- 0.3 to V

- 0.3 to 6.5

(Mask ROM version CNVss)

(Flash memory version CNVss)

Note: It is a value in flash memory mode. Other parameter becomes same as a value in microcomputer mode.

°C

Mitsubishi microcomputers

M30220 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

216

LQFP144-P-2020-0.50

Weight(g)

1.23

JEDEC Code

EIAJ Package Code

Lead Material

Cu Alloy

144P6Q-A

Plastic 144pin 20

20mm body LQFP

0.125

0.2

Symbol

Min

Nom

Max

b
c

D
E

Dimension in Millimeters

0.225

0.95

20.4

0.1

1.0

0.65

0.5

0.35

22.2

22.0

21.8

22.2

22.0

21.8

0.5

20.1

20.0

19.9

20.1

20.0

19.9

0.175

0.125

0.105

0.27

0.22

0.17

1.4

0.05

1.7

108

109

144

0.45

0.6
0.25

0.75

0.08

Recommended Mount Pad

Detail F

MMP

TQFP144-P-1616-0.40

Weight(g)

0.62

JEDEC Code

EIAJ Package Code

Lead Material

Cu Alloy

144PFB-A

Plastic 144pin 16

16mm body TQFP

Symbol

Min

Nom

Max

b
c

D
E

Dimension in Millimeters

0.15

0.1

0.225

1.0

16.4

0.08

1.0

0.6

0.5

0.4

18.2

18.0

17.8

18.2

18.0

17.8

0.4

16.1

16.0

15.9

16.1

16.0

15.9

0.175

0.125

0.105

0.23

0.18

0.13

1.0

0.05

1.2

113

114

144

Detail F

0.45

0.6
0.25

0.75

0.07

Recommended Mount Pad

MMP

REVISION HISTORY

M30220 GROUP DATA SHEET

Rev.

Date

Description

Page

Summary

217

01/12/17

Features are partly revised.
Applications is partly added.
Page numbers of Table of Contents are partly revised.
Figure 1.1.1 is partly revised.
Table 1.1.1 is partly revised.
Figure 1.1.3 is partly revised.
Figure 1.1.4 is partly revised.
Pin description

is partly revised.

Figure 1.4.1 is partly revised.
Figure 1.6.1 is partly added.
Figure 1.6.3 is partly revised.
Figure 1.7.1 is partly revised. Note is added.
Figure 1.7.2 is partly revised. Note 2 is added.
Figure 1.7.3 is partly revised. Note is added.
Processor mode register 0 in Figure 1.8.1 is partly revised.
System clock control register in Figure 1.9.4 is partly revised. Note 8 is partly re-
vised.
Explanation of "Wait Mode" is partly revised.
Explanation of "Hardware Interrupts" is partly revised.
Table 1.10.2 is partly revised. Note 3 and note 4 are partly revised.
Explanation of "Saving Registers is" partly revised. Note is partly revised.
Figure 1.10.9 is partly revised.
Explanation of "Key Input Interrupt" is partly revised.
Figure 1.10.13 is partly revised.
Figure 1.10.14 and 1.10.15 are partly revised.

______

Explanation of "(3) The NMI interrupt" is partly revised.
Explanation of "Watchdog timer" is partly added.
Table 1.12.1 is partly revised.
Explanation of "(1) Interrupt factors" is partly revised.
Figure 1.13.3 is partly revised.
Timer Ai register in Figure 1.13.5 is partly revised.
Up/down flag 0 and Up/down flag 1 in Figure 1.13.6 is partly revised. Note is added.
Table 1.13.2 is partly revised.
Figure 1.13.10 is partly revised.
Table 1.13.3 is partly revised.
Figure 1.13.11 is partly revised.
Table 1.13.5 is partly revised.
Figure 1.13.14 and Figure 1.13.15 are partly revised.
Figure 1.14.2 and Figure 1.14.3 are partly revised.
UARTi transmit buffer register in Figure1.15.4 is partly revised. Note is added.
UARTi bit rate generator in Figure1.15.4 is partly revised. Note is added.
Explanation of "LCD Drive Control Circuit" is partly revised.
LCD mode register in Figure 1.16.2 is partly revised.
Explanation of "Voltage Multiplier" is partly revised.
Figure 1.16.3 is partly revised.
Table 1.17.1 is partly revised.
Explanation of "Sample and hold" is partly revised.
Port P13 direction register in Figure 1.19.6 is partly revised. Note is deleted.
Port P7 register in Figure 1.19.7 is partly revised. Note is added.
Port P13 register in Figure 1.19.7 is partly revised. Note is deleted.

1
1
1
2
4
5
5
6
8

12
13
15
16
17
18
23

25
32
34
42
44
47
47
48
50
53
56
63
67
68
69
73
73
74
75
77
78
86
91
91

123
125
126
126
130
139
147
148
148

REVISION HISTORY

M30220 GROUP DATA SHEET

Rev.

Date

Description

Page

Summary

218

Figure 1.19.8 is partly revised. Note is added.
Figure 1.19.9 and Figure 1.19.10 are partly revised.
Table 1.19.1 is partly revised.
Figure 1.19.8 is partly revised.
Explanation of "Serial I/O usage precaution" is added.
Explanation of "Stop Mode and Wait Mode usage precaution" is partly revised.

______

Explanation of "(3) The NMI interrupt" is partly revised.
Table 1.21.4 is partly revised.
Table 1.21.19 is partly revised.
Table 1.21.20 is partly revised.
MASK ROM CONFIRMATION FORM is added.
Table 1.22.1 is partly revised.
Explanation of "Flash Memory" is partly revised.
Figure 1.22.1 is partly revised.
Explanation of "Block Address" is partly revised.
Explanation of "Writing in the user ROM area" is partly revised.
Table 1.23.1 is partly revised. Note 4 is partly revised.
Figure 1.23.5 is partly revised.
Explanation of "ROM code protect function" is partly revised.
Pin description (Flash memory standard serial I/O mode)

is partly revised.

Figure 1.25.1 is partly revised.
Explanation of "Page Read Command" is partly revised.
Explanation of "Block Erase Command" is partly revised.
Explanation of "Boot ROM Area Output Command" is partly revised.
Figure 1.25.14 is partly revised.
Explanation of "Page Read Command" is partly revised.
Explanation of "Block Erase Command" is partly revised.
Explanation of "Boot ROM Area Output Command" is partly revised.
Timing (Flash memory version) is added.
Package is added.

149
150
151
151
153
153
154
158
163
164

168-170

171
172
172
173
177
178
182
183
186
187
191
193
195
200
205
207
209

214-215

216

01/12/17

Keep safety first in your circuit designs!

Notes regarding these materials

Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble may
occur with them. Trouble with semiconductors may lead to personal injury, fire or
property damage. Remember to give due consideration to safety when making your
circuit designs, with appropriate measures such as (i) placement of substitutive,
auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any
malfunction or mishap.

These materials are intended as a reference to assist our customers in the selection
of the Mitsubishi semiconductor product best suited to the customer's application;
they do not convey any license under any intellectual property rights, or any other
rights, belonging to Mitsubishi Electric Corporation or a third party.

Mitsubishi Electric Corporation assumes no responsibility for any damage, or
infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in
these materials.

All information contained in these materials, including product data, diagrams, charts,
programs and algorithms represents information on products at the time of publication
of these materials, and are subject to change by Mitsubishi Electric Corporation
without notice due to product improvements or other reasons. It is therefore
recommended that customers contact Mitsubishi Electric Corporation or an authorized
Mitsubishi Semiconductor product distributor for the latest product information before
purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical
errors. Mitsubishi Electric Corporation assumes no responsibility for any damage,
liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation
by various means, including the Mitsubishi Semiconductor home page (http://
www.mitsubishichips.com).

When using any or all of the information contained in these materials, including
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responsibility for any damage, liability or other loss resulting from the information
contained herein.

Mitsubishi Electric Corporation semiconductors are not designed or manufactured
for use in a device or system that is used under circumstances in which human life is
potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized
Mitsubishi Semiconductor product distributor when considering the use of a product
contained herein for any specific purposes, such as apparatus or systems for
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The prior written approval of Mitsubishi Electric Corporation is necessary to reprint
or reproduce in whole or in part these materials.

If these products or technologies are subject to the Japanese export control
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Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semicon
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tained therein.

Document Outline

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Document Outline

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