Document Outline

Cover
Preface
Contents
Section 1 Overview
- 1.1 Overview
- 1.2 Internal Block Diagram
- 1.3 Pin Arrangement and Functions
Section 2 CPU
- 2.1 Overview
- 2.2 Register Descriptions
- 2.3 Data Formats
- 2.4 Addressing Modes
- 2.5 Instruction Set
- 2.6 CPU States
- 2.7 Basic Operation Timing
- 2.8 Application Notes
Section 3 System Control
- 3.1 Overview
- 3.2 Exception Handling
- 3.3 System Modes
- 3.4 System Control Registers
Section 4 ROM
- 4.1 Overview
- 4.2 PROM Mode
- 4.3 Programming
Section 5 RAM
- 5.1 Overview
Section 6 Clock Pulse Generators
- 6.1 Overview
- 6.2 System Clock Generator
- 6.3 Subclock Generator
Section 7 I/O Ports
- 7.1 Overview
- 7.2 Port 0
- 7.3 Port 1
- 7.4 Port 4
- 7.5 Port 5
- 7.6 Port 6
- 7.7 Port 7
- 7.8 Port 9
Section 8 Timers
- 8.1 Overview
- 8.2 Timer A
- 8.3 Timer B
- 8.4 Timer C
- 8.5 Timer D
- 8.6 Timer E
- 8.7 Interrupts
Section 9 14-Bit PWM
- 9.1 Overview
- 9.2 Register Descriptions
- 9.3 Operation
Section 10 SCI1
- 10.1 Overview
- 10.2 Register Descriptions
- 10.3 Operation
Section 11 SCI2
- 11.1 Overview
- 11.2 Register Descriptions
- 11.3 Operation
- 11.4 Interrupts
- 11.5 Application Notes
Section 12 VFD Controller/Driver
- 12.1 Overview
- 12.2 Register Descriptions
- 12.3 Operation
- 12.4 Interrupts
- 12.5 Occurrence of Flicker when VFD Registers are Rewritten
Section 13 A/D Converter
- 13.1 Overview
- 13.2 Register Descriptions
- 13.3 Operation
- 13.4 Interrupts
- 13.5 Typical Use
- 13.6 Application Notes
Section 14 Electrical Specifications
- 14.1 Absolute Maximum Ratings
- 14.2 HD6473714 Electrical Characteristics
- 14.3 HD6433712, HD6433713 and HD6433714 Electrical Characteristics
- 14.4 Operational Timing
- 14.5 Differences in Electrical Characteristics between HD6473714 and HD6433712/HD6433713/HD6433714
Appendix A CPU Instruction Set
- A.1 Instruction Notation
- A.2 Operation Code Map
- A.3 Number of States Required for Execution
Appendix B On-Chip Registers
- B.1 On-Chip Registers (1)
- B.2 On-Chip Registers (2)
Appendix C I/O Port Block Diagrams
- C.1 Port 0 Block Diagram
- C.2 Port 1 Block Diagram
- C.3 Port 4 Block Diagram
- C.4 Port 5 Block Diagram
- C.5 Port 6 Block Diagram
- C.6 Port 7 Block Diagram
- C.7 Port 9 Block Diagram
Appendix D Port States in Each Processing State
Appendix E List of Mask Options
Appendix F Rise Time and Fall Time of High-Voltage Pins
Appendix G Package Dimensions

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Contents

Section 1

Overview

..........................................................................................................

1.1

Overview.........................................................................................................................

1.2

Internal Block Diagram ..................................................................................................

1.3

Pin Arrangement and Functions .....................................................................................

1.3.1

Pin Arrangement .................................................................................................

1.3.2

Pin Functions ......................................................................................................

Section 2

CPU

................................................................................................................... 15

2.1

Overview......................................................................................................................... 15
2.1.1

Features............................................................................................................... 15

2.1.2

Address Space..................................................................................................... 16

2.1.3

2.2

Register Descriptions...................................................................................................... 18
2.2.1

General Registers................................................................................................ 18

2.2.2

Control Registers ................................................................................................ 18

2.2.3

Initial Register Values......................................................................................... 20

2.3

Data Formats................................................................................................................... 20
2.3.1

Data Formats in General Registers ..................................................................... 21

2.3.2

Memory Data Formats ........................................................................................ 22

2.4

Addressing Modes .......................................................................................................... 23
2.4.1

Addressing Modes .............................................................................................. 23

2.4.2

Effective Address Calculation ............................................................................ 25

2.5

Instruction Set................................................................................................................. 29
2.5.1

Data Transfer Instructions .................................................................................. 31

2.5.2

Arithmetic Operations ........................................................................................ 33

2.5.3

Logic Operations ................................................................................................ 34

2.5.4

Shift Operations .................................................................................................. 34

2.5.5

Bit Manipulations ............................................................................................... 36

2.5.6

Branching Instructions........................................................................................ 40

2.5.7

System Control Instructions ............................................................................... 42

2.5.8

Block Data Transfer Instruction ......................................................................... 43

2.6

CPU States ...................................................................................................................... 45
2.6.1

Overview............................................................................................................. 45

2.6.2

Program Execution State .................................................................................... 46

2.6.3

Program Halt State.............................................................................................. 46

2.6.4

Exception-Handling State ................................................................................... 46

2.7

Basic Operation Timing.................................................................................................. 47
2.7.1

Access to On-Chip Memory (RAM, ROM) ....................................................... 47

2.7.2

Access to On-Chip Peripheral Modules ............................................................. 48

2.8

Application Notes ........................................................................................................... 49
2.8.1

Notes on Data Access ......................................................................................... 49

2.8.2

Notes on Bit Manipulation.................................................................................. 51

Section 3

System Control

.............................................................................................. 55

3.1

Overview......................................................................................................................... 55

3.2

Exception Handling ........................................................................................................ 55
3.2.1

Reset ................................................................................................................... 55

3.2.2

Interrupts............................................................................................................. 56

3.2.3

Interrupt Control Registers ................................................................................. 58

3.2.4

External Interrupts .............................................................................................. 66

3.2.5

Internal Interrupts ............................................................................................... 67

3.2.6

Interrupt Operations............................................................................................ 67

3.2.7

Return from an Interrupt ..................................................................................... 72

3.2.8

Interrupt Response Time..................................................................................... 72

3.2.9

Valid Interrupts in Each Mode ............................................................................ 73

3.2.10 Notes on Stack Area Use .................................................................................... 74

3.3

System Modes................................................................................................................. 75
3.3.1

Active Mode ....................................................................................................... 76

3.3.2

Low-Power Operation Mode .............................................................................. 76

3.3.3

Application Notes ............................................................................................... 82

3.4

System Control Registers ............................................................................................... 83
3.4.1

System Control Register 1 (SYSCR1)................................................................ 83

3.4.2

System Control Register 2 (SYSCR2)................................................................ 85

Section 4

ROM

.................................................................................................................. 87

4.1

Overview......................................................................................................................... 87
4.1.1

Block Diagram.................................................................................................... 87

4.2

PROM Mode................................................................................................................... 88
4.2.1

Selection to PROM Mode................................................................................... 88

4.2.2

Socket Adapter Pin Arrangement and Memory Map ......................................... 88

4.3

Programming .................................................................................................................. 91
4.3.1

Writing and Verifying ......................................................................................... 91

4.3.2

Programming Precautions................................................................................... 94

4.3.3

Reliability of Written Data ................................................................................. 96

Section 5

RAM

................................................................................................................. 97

5.1

Overview......................................................................................................................... 97
5.1.1

Block Diagram.................................................................................................... 97

5.1.2

Display RAM Area ............................................................................................. 97

Section 6

Clock Pulse Generators

............................................................................... 99

6.1

Overview......................................................................................................................... 99
6.1.1

Block Diagram.................................................................................................... 99

6.2

System Clock Generator ................................................................................................. 100

6.3

Subclock Generator ........................................................................................................ 103

Section 7

I/O Ports

........................................................................................................... 105

7.1

Overview......................................................................................................................... 105
7.1.1

Port Types and Mask Options............................................................................. 107

7.1.2

MOS Pull-Up ...................................................................................................... 108

7.1.3

MOS Pull-Down ................................................................................................. 110

7.2

Port 0 ............................................................................................................................ 111
7.2.1

Overview............................................................................................................. 111

7.2.2

7.2.3

Pin Functions ...................................................................................................... 112

7.2.4

Pin States ............................................................................................................ 112

7.3

Port 1 ............................................................................................................................ 113
7.3.1

Overview............................................................................................................. 113

7.3.2

7.3.3

Pin Functions ...................................................................................................... 118

7.3.4

Pin States ............................................................................................................ 119

7.4

Port 4 ............................................................................................................................ 120
7.4.1

Overview............................................................................................................. 120

7.4.2

7.4.3

Pin Functions ...................................................................................................... 121

7.4.4

Pin States ............................................................................................................ 121

7.5

Port 5 ............................................................................................................................ 122
7.5.1

Overview............................................................................................................. 122

7.5.2

7.5.3

Pin Functions ...................................................................................................... 123

7.5.4

Pin States ............................................................................................................ 123

7.6

Port 6 ............................................................................................................................ 124
7.6.1

Overview............................................................................................................. 124

7.6.2

7.6.3

Pin Functions ...................................................................................................... 125

7.6.4

Pin States ............................................................................................................ 125

7.7

Port 7 ............................................................................................................................ 126
7.7.1

Overview............................................................................................................. 126

7.7.2

7.7.3

Pin Functions ...................................................................................................... 127

7.7.4

Pin States ............................................................................................................ 127

7.8

Port 9 ............................................................................................................................ 128
7.8.1

Overview............................................................................................................. 128

7.8.2

7.8.3

Pin Functions ...................................................................................................... 132

7.8.4

Pin States ............................................................................................................ 134

Section 8

Timers

............................................................................................................... 135

8.1

Overview......................................................................................................................... 135
8.1.1

Prescaler Operation............................................................................................. 136

8.2

Timer A........................................................................................................................... 138
8.2.1

Overview............................................................................................................. 138

8.2.2

8.2.3

Timer Operation.................................................................................................. 141

8.3

Timer B ........................................................................................................................... 143
8.3.1

Overview............................................................................................................. 143

8.3.2

8.3.3

Timer Operation.................................................................................................. 146

8.4

Timer C ........................................................................................................................... 148
8.4.1

Overview............................................................................................................. 148

8.4.2

8.4.3

Timer Operation.................................................................................................. 152

8.5

Timer D........................................................................................................................... 154
8.5.1

Overview............................................................................................................. 154

8.5.2

8.5.3

Timer Operation.................................................................................................. 157

8.6

Timer E ........................................................................................................................... 158
8.6.1

Overview............................................................................................................. 158

8.6.2

8.6.3

Timer Operation.................................................................................................. 164

8.7

Interrupts......................................................................................................................... 167

8.8

Application Notes ........................................................................................................... 167

Section 9

14-Bit PWM

................................................................................................... 169

9.1

Overview......................................................................................................................... 169
9.1.1

Features............................................................................................................... 169

9.1.2

Block Diagram.................................................................................................... 169

9.1.3

Pin Configuration................................................................................................ 170

9.1.4

9.2

Register Descriptions...................................................................................................... 171
9.2.1

PWM Control Register (PWCR) ........................................................................ 171

9.2.2

PWM Data Registers U and L (PWDRU, PWDRL) .......................................... 172

9.3

Operation ........................................................................................................................ 173

Section 10 SCI1

.................................................................................................................. 175

10.1

Overview......................................................................................................................... 175
10.1.1 Features............................................................................................................... 175
10.1.2 Block Diagram.................................................................................................... 175
10.1.3 Pin Configuration................................................................................................ 176
10.1.4 Register Configuration........................................................................................ 176

10.2

Register Descriptions...................................................................................................... 177
10.2.1 Serial Mode Register 1 (SMR1) ......................................................................... 177
10.2.2 Serial Data Register U1 (SDRU1) ...................................................................... 178
10.2.3 Serial Data Register L1 (SDRL1)....................................................................... 179
10.2.4 Serial Port Register 1 (SPR1) ............................................................................. 179
10.2.5 Port Mode Register 2 (PMR2) ............................................................................ 180
10.2.6 Port Mode Register 3 (PMR3) ............................................................................ 181

10.3

Operation ........................................................................................................................ 182
10.3.1 Overview............................................................................................................. 182
10.3.2 Data Transfer Format.......................................................................................... 183
10.3.3 Clock................................................................................................................... 183
10.3.4 Data Transmit/Receive........................................................................................ 183
10.3.5 SCI1 State Transitions ........................................................................................ 186
10.3.6 Serial Clock Error Detection .............................................................................. 187
10.3.7 Interrupts............................................................................................................. 188

Section 11 SCI2

.................................................................................................................. 189

11.1

Overview......................................................................................................................... 189
11.1.1 Features............................................................................................................... 189
11.1.2 Block Diagram.................................................................................................... 189
11.1.3 Pin Configuration................................................................................................ 190
11.1.4 Register Configuration........................................................................................ 190

11.2

Register Descriptions...................................................................................................... 191
11.2.1 Start Address Register (STAR)........................................................................... 191
11.2.2 End Address Register (EDAR) ........................................................................... 191
11.2.3 Serial Control Register 2 (SCR2) ....................................................................... 192
11.2.4 Status Register (STSR) ....................................................................................... 193
11.2.5 Port Mode Register 3 (PMR3) ............................................................................ 195

11.3

Operation ........................................................................................................................ 197
11.3.1 Overview............................................................................................................. 197

11.3.2 Clock................................................................................................................... 198
11.3.3 Data Transfer Format.......................................................................................... 198
11.3.4 Data Transmit/Receive........................................................................................ 200

11.4

Interrupts......................................................................................................................... 202

11.5

Application Notes ........................................................................................................... 202

Section 12 VFD Controller/Driver

................................................................................ 203

12.1

Overview......................................................................................................................... 203
12.1.1 Features............................................................................................................... 203
12.1.2 Block Diagram.................................................................................................... 203
12.1.3 Pin Configuration................................................................................................ 204
12.1.4 Register Configuration........................................................................................ 204

12.2

Register Descriptions...................................................................................................... 205
12.2.1 VFD Digit Control Register (VFDR) ................................................................. 205
12.2.2 VFD Segment Control Register (VFSR) ............................................................ 208
12.2.3 Digit Beginning Register (DBR) ........................................................................ 210

12.3

Operation ........................................................................................................................ 212
12.3.1 Overview............................................................................................................. 212
12.3.2 Control Section ................................................................................................... 212
12.3.3 RAM Bit Correspondence to Digits/Segments................................................... 212
12.3.4 Procedure for Starting Operation........................................................................ 214

12.4

Interrupts......................................................................................................................... 214

12.5

Occurrence of Flicker when VFD Registers are Rewritten ............................................ 214

Section 13 A/D Converter

................................................................................................ 215

13.1

Overview......................................................................................................................... 215
13.1.1 Features............................................................................................................... 215
13.1.2 Block Diagram.................................................................................................... 216
13.1.3 Pin Configuration................................................................................................ 217
13.1.4 Register Configuration........................................................................................ 217

13.2

Register Descriptions...................................................................................................... 218
13.2.1 A/D Result Register (ADRR) ............................................................................. 218
13.2.2 A/D Mode Register (AMR) ................................................................................ 218
13.2.3 A/D Start Register (ADSR) ................................................................................ 221
13.2.4 Port Mode Register 0 (PMR0) ............................................................................ 222

13.3

Operation ........................................................................................................................ 222

13.4

Interrupts......................................................................................................................... 222

13.5

Typical Use ..................................................................................................................... 223

13.6

Application Notes ........................................................................................................... 227

Section 14 Electrical Specifications

.............................................................................. 229

14.1

Absolute Maximum Ratings ........................................................................................... 229

14.2

HD6473714 Electrical Characteristics ........................................................................... 230
14.2.1 HD6473714 DC Characteristics ......................................................................... 230
14.2.2 HD6473714 AC Characteristics ......................................................................... 236
14.2.3 HD6473714 A/D Converter Characteristics ....................................................... 239

14.3

HD6433712, HD6433713 and HD6433714 Electrical Characteristics .......................... 240
14.3.1 HD6433712, HD6433713 and HD6433714 DC Characteristics ........................ 240
14.3.2 HD6433712, HD6433713 and HD6433714 AC Characteristics ........................ 246
14.3.3 HD6433712, HD6433713 and HD6433714 A/D Converter Characteristics...... 249

14.4

Operational Timing......................................................................................................... 250

14.5

Differences in Electrical Characteristics between HD6473714 and
HD6433712/HD6433713/HD6433714........................................................................... 253

Appendix A CPU Instruction Set

................................................................................... 255

A.1

Instruction Notation ........................................................................................................ 255

A.2

Operation Code Map....................................................................................................... 256

A.3

Number of States Required for Execution...................................................................... 258

Appendix B On-Chip Registers

...................................................................................... 265

B.1

On-Chip Registers (1)..................................................................................................... 265

B.2

On-Chip Registers (2)..................................................................................................... 268

Appendix C I/O Port Block Diagrams

......................................................................... 295

C.1

Port 0 Block Diagram ..................................................................................................... 295

C.2

Port 1 Block Diagram ..................................................................................................... 296

C.3

Port 4 Block Diagram ..................................................................................................... 299

C.4

Port 5 Block Diagram ..................................................................................................... 300

C.5

Port 6 Block Diagram ..................................................................................................... 301

C.6

Port 7 Block Diagram ..................................................................................................... 302

C.7

Port 9 Block Diagram ..................................................................................................... 303

Appendix D Port States in Each Processing State

.................................................... 309

Appendix E List of Mask Options

................................................................................. 311

Appendix F Rise Time and Fall Time of High-Voltage Pins

................................. 312

Appendix G Package Dimensions

................................................................................. 313

Section 1 Overview

1.1 Overview

The H8/300L Series is a series of single-chip microcontrollers (MCU: microcomputer unit) built
around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip.

Within the H8/300L Series, the H8/3714 Series microcontrollers are equipped with high-voltage
pins. On-chip peripheral functions include a vacuum fluorescent display (VFD) controller/driver,
timers, a 14-bit pulse width modulator (digital-to-analog converter), two serial communication
interface channels, and an analog-to-digital converter. Together, these functions make the
H8/3714 Series ideally suited for embedded control of systems requiring a vacuum fluorescent
display. On-chip memory is 16 kbytes of ROM and 384 bytes of RAM in the H8/3712, 24 kbytes
of ROM and 384 bytes of RAM in the H8/3713, or 32 kbytes of ROM and 512 bytes of RAM in
the H8/3714, providing a choice for systems of different sizes. The ZTATTM* versions of the
H8/3714 come with user-programmable PROM.

Table 1 summarizes the features of the H8/3714 Series.

Note: * ZTAT (zero turn-around time) is a trademark of Hitachi, Ltd.

Table 1-1 Features (cont)

Item

Description

Timers

� Timer A: 8-bit interval timer

Count-up timer with selection of eight internal clock signals divided from
the system clock (

)

and four clock signals divided from the subclock

(

SUB

)

� Timer B: 8-bit reload timer

Count-up timer with selection of seven internal clock signals or event input
from pin P1

/IRQ

� Timer C: 8-bit reload timer

Count-up/count-down timer with selection of seven internal clock signals
or event input from pin P1

/IRQ

� Timer D: 8-bit event counter

Up-counter for counting input from pin P1

EVENT

� Timer E: 8-bit reloadable timer

Count-up timer with selection of eight internal clock signals. Square-wave
(50% duty cycle) output with a fixed frequency or variable frequency
controlled by timer E overflow can be selected by pin P1

/IRQ

/TMOE

settings.

Note:

indicates a clock frequency that is divided in half from the original

oscillator frequency

14-bit PWM

� Pulse-division PWM designed for less ripple

� Can be used as a 14-bit D/A converter by connecting to an external low-

pass filter

VFD

� Up to 24 segment pins and up to 16 digit pins (of which 8 are for both

driver/controller

uses)

� Brightness adjustable in 8 steps (dimmer function)

� Digit and segment pins can be switched to use as general-purpose high-

voltage pins

� Key scan interval can be enabled or disabled

� Interrupt can be requested when key scan interval starts

� 2-channel synchronous SCI1 and SCI2

� Choice of 8-bit or 16-bit data transfer (SCI1)

� Automatic transfer of 32-byte data (SCI2)

� Overrun error detection possible

� Interrupt can be requested when transfer is complete

Serial communica-
tion interface

Table 1-1 Features (cont)

Item

Description

A/D converter

� Successive approximations using a resistance ladder

� Resolution: 8 bits

� 8-channel analog input port

� Conversion time: 31/

or 62/

per channel

� Interrupt can be requested at completion of A/D conversion

I/O ports

� High-voltage I/O pins: 32

� High-voltage input pin: 1

� Standard-voltage I/O pins: 12

� Standard-voltage input pins: 9

Interrupts

� Four external interrupt pins: IRQ

, IRQ

� Ten internal interrupt sources

� Sleep mode

� Standby mode

� Watch mode

� Subactive mode

Other

� Built-in pulse generators for system clock and subclock

� Timer A can run on the subclock for use as a time base

Product lineup

Product Code

Mask ROM Version

ZTAT

Version

Package

ROM/RAM Size

HD6433714H

HD6473714H

64 pin GFP

ROM: 32 kbytes

(FP-64A)

RAM: 512 bytes

HD6433714P

HD6473714P

64 pin SDIP
(DP-64S)

HD6433713H

64 pin QFP

ROM: 24 kbytes

(FP-64A)

RAM: 384 bytes

HD6433713P

64 pin SDIP
(DP-64S)

HD6433712H

64 pin QFP

ROM: 16 kbytes

(FP-64A)

RAM: 384 bytes

HD6433712P

64 pin SDIP
(DP-64S)

Low power operation
modes

1.2 Internal Block Diagram

Figure 1-1 is an internal block diagram of the H8/3714 Series.

Figure 1-1 Block Diagram

P6 /FD /FS
P6 /FD /FS
P6 /FD /FS
P6 /FD /FS
P6 /FD /FS
P6 /FD /FS
P6 /FD /FS
P6 /FD /FS

P9 /PWM

P9 /SCK

P9 /SI

P9 /SO

P9 /SCK

P9 /SI /CS

P9 /SO

P9 /UD

P5 /FS
P5 /FS
P5 /FS
P5 /FS
P5 /FS
P5 /FS

P5 /FS
P5 /FS

P4 /FS
P4 /FS
P4 /FS
P4 /FS
P4 /FS
P4 /FS
P4 /FS
P4 /FS

P1 /IRQ
P1 /IRQ
P1 /IRQ
P1 /IRQ
P1 /IRQ
P1 /IRQ /TMOE
P1 /EVENT
P1 /V

disp

P7 /FD
P7 /FD
P7 /FD
P7 /FD
P7 /FD
P7 /FD
P7 /FD
P7 /FD

P0 /AN

OSC

TEST

RES

CPU

H8/300L

Mask ROM (PROM)

Subclock

pulse

generator

System

clock pulse

generator

Port 5

Port 9

Port 4

Port 6

Port 1

Port 7

Data bus (lower)

RAM

Timer A

Timer B

Timer C

Timer D

Timer E

14-bit PWM

SCI1

SCI2

VFD

controller/driver

A/D converter

Port 0

Data bus (upper)

Address bus

1.3 Pin Arrangement and Functions

1.3.1 Pin Arrangement

The pin arrangements for the H8/3714 Series are shown in figure 1-2 (FP-64A) and figure 1-3
(DP-64S).

Figure 1-2 Pin Arrangement (FP-64A: Top View)

P0 /AN

TEST

OSC

P7 /FD

P6 /FD /FS

P1 /V

P5 /FS

disp

P9 /UD

P9 /SO

P9 /SI /CS

P9 /SCK

P9 /SO

P9 /SI

P9 /SCK

P9 /PWM

P7 /FD

RES

P1 /IRQ

P1 /IRQ /TMOE

P1 /EVENT

P4 /FS

P5 /FS

Figure 1-3 Pin Arrangement (DP-64S: Top View)

P4 /FS

P7 /FD

P6 /FD /FS

P1 /V

P5 /FS

disp

RES

P1 /IRQ

P1 /IRQ /TMOE

P1 /EVENT

P4 /FS

P9 /PWM

P9 /SCK

P9 /SI

P9 /SO

P9 /SCK

P9 /SI /CS

P9 /SO

P9 /UD

P0 /AN

TEST

OSC

1.3.2 Pin Functions

List of pin functions

Table 1-2 lists the pin functions of the LSI.

Table 1-2 List of Pin Functions

Pin No.

FP-64A

DP-64S

Name and Function

PROM Mode

/AN

(standard input port/analog input channel)

/AN

(standard input port/analog input channel)

/AN

(standard input port/analog input channel)

/AN

(standard input port/analog input channel)

(reference voltage for A/D converter)

TEST (test pin)

(subclock oscillator connection)

(ground)

OSC

(system clock oscillator connection)

OSC

(system clock oscillator connection)

RES

(reset input)

/IRQ

(standard I/O port/external interrupt or

timer B event input)

/IRQ

(standard I/O port/external interrupt or

timer C event input)

/IRQ

(standard I/O port/external interrupt)

/IRQ

/TMOE (standard I/O port/external

interrupt/warning tone output)

EVENT

(standard input port/timer D event input)

/FS

(high-voltage I/O port/VFD segment output)

/FS

(high-voltage I/O port/VFD segment output)

/FS

(high-voltage I/O port/VFD segment output)

/FS

(high-voltage I/O port/VFD segment output)

/FS

(high-voltage I/O port/VFD segment output)

/FS

(high-voltage I/O port/VFD segment output)

/FS

(high-voltage I/O port/VFD segment output)

Table 1-2 List of Pin Functions (cont)

Pin No.

FP-64A

DP-64S

Name and Function

PROM Mode

/FS

(high-voltage I/O port/VFD segment output)

/FS

(high-voltage I/O port/VFD segment output)

/FS

(high-voltage I/O port/VFD segment output)

/FS

(high-voltage I/O port/VFD segment output)

/FS

(high-voltage I/O port/VFD segment output)

/FS

(high-voltage I/O port/VFD segment output)

/FS

(high-voltage I/O port/VFD segment output)

/FS

(high-voltage I/O port/VFD segment output)

/FS

(high-voltage I/O port/VFD segment output)

disp

(high-voltage input port/VFD power source)

/FD

/FS

(high-voltage I/O port/VFD digit-segment

output)

/FD

/FS

(high-voltage I/O port/VFD digit-segment

output)

/FD

/FS

(high-voltage I/O port/VFD digit-segment

output)

/FD

/FS

(high-voltage I/O port/VFD digit-segment

output)

/FD

/FS

(high-voltage I/O port/VFD digit-segment

output)

/FD

/FS

(high-voltage I/O port/VFD digit-segment

output)

/FD

/FS

(high-voltage I/O port/VFD digit-segment

output)

/FD

/FS

(high-voltage I/O port/VFD digit-segment

output)

/FD

(high-voltage I/O port/VFD digit output)

/FD

(high-voltage I/O port/VFD digit output)

/FD

(high-voltage I/O port/VFD digit output)

Table 1-2 List of Pin Functions (cont)

Pin No.

FP-64A

DP-64S

Name and Function

PROM Mode

/FD

(high-voltage I/O port/VFD digit output)

/FD

(high-voltage I/O port/VFD digit output)

/FD

(high-voltage I/O port/VFD digit output)

/FD

(high-voltage I/O port/VFD digit output)

/FD

(high-voltage I/O port/VFD digit output)

(system power source)

/PWM (standard I/O port/PWM output)

/SCK

(standard I/O port/clock output)

/SI

(standard I/O port/data input)

/SO

(standard I/O port/data output)

/SCK

(standard I/O port/clock I/O)

/SI

(standard I/O port/data input/chip

select output)

/SO

(standard I/O port/data output)

/UD (standard I/O port/timer C up-down control)

(reference power source for A/D converter)

/AN

(standard input port/analog input channel)

/AN

(standard input port/analog input channel)

/AN

(standard input port/analog input channel)

/AN

(standard input port/analog input channel)

Notes: 1. NC pins should be left unconnected.

2. Details on PROM mode are given in 4.2, PROM Mode.

Pin functions

Table 1-3 explains the functions of each pin in more detail.

Table 1-3 Pin Functions

Pin No.

Type

Symbol FP-64A DP-64S

I/O

Name and Functions

Power V

Input

Power source: Connects to a power

supply pins

supply (+5 V)

All V

pins should be connected to the

system power supply (+5 V).

Input

Ground: Connects to a power supply
(0 V).

All V

pins should be connected to the

system power supply (0 V).

Input

Analog power supply: This is the
reference power supply pin for the A/D
converter. When the A/D converter is not
used, connect this pin to the system
power supply (+5 V).

Input

Analog ground: This is the A/D
converter ground pin.
It should be connected to the system
power supply (0 V).

disp

Input

VFD power supply: This pin should be
connected to a VFD driver power supply.

Clock pins

OSC

Input

This pin connects to a crystal or ceramic
oscillator, or can be used to input an
external clock.

See section 6, Clock Pulse Generators,
for a typical connection diagram.

OSC

Output This pin connects to a crystal or ceramic

oscillator.

Input

This pin connects to a 32.768 kHz crystal
oscillator.

For a typical connection diagram,
see section 6, Clock Pulse Generators.

Output This pin connects to a 32.768 kHz crystal

oscillator.

Table 1-3 Pin Functions (cont)

Pin No.

Type

Symbol FP-64A DP-64S

I/O

Name and Functions

System control

RES

Input

Reset: When this pin goes to low level,
the chip is reset.

TEST

Input

Test: This pin is not for use in
application systems. It should be
connected to V

Interrupt pins

IRQ

Input

External interrupt request 0: This is an
input pin for external interrupts for which
there is a choice between rising and
falling edge sensing. It can be used to
exit low-power mode.

This pin can be used as the event input
pin for timer B. A noise cancel function is
also provided.

IRQ

Input

External interrupt request 1: This is an
input pin for external interrupts for which
there is a choice between rising and
falling edge sensing. It can be used to
exit low-power mode.

This pin can be used as the event input
pin for timer C.

IRQ

Input

External interrupt request 4: This is an
input pin for external interrupts for which
there is a choice between rising and
falling edge sensing.

IRQ

Input

External interrupt request 5: This is an
input pin for external interrupts that are
detected at the falling edge.

Table 1-3 Pin Functions (cont)

Pin No.

Type

Symbol FP-64A DP-64S

I/O

Name and Functions

Timer pins

IRQ

Input

Timer B event counter input: This is
an event input pin for input to the timer B
counter.

IRQ

Input

Timer C event counter input: This is
an event input pin for input to the timer C
counter.

Input

Timer C up/down select: This pin
selects whether the timer C counter is
used for up- or down-counting. At high
level it selects down-counting, and at low
level up-counting.

Input to this pin is valid only when bit
TMC6 in timer mode register C (TMC) is
set to 1.

EVENT

Input

Timer D event counter input: This is
an event input pin for input to the timer D
counter.

TMOE

Output Timer E output: This is an output pin for

waveforms generated by the timer E
output circuit.

14-bit PWM pin

PWM

Output 14-bit PWM output: This is an output

pin for waveforms generated by the
14-bit PWM.

Output Serial transmit data output (channels 1

and 2): These are SCI data output pins.

Input

Serial receive data input (channels 1

and 2): These are SCI data input pins.

SCK

I/O

Serial clock I/O (channels 1 and 2):

SCK

These are SCI clock I/O pins.

Output Chip select output: When SCI2 is in

transmit mode and the serial clock is an
internal clock, this pin goes low.

This function is valid when bit SI2 in port
mode register 2 (PMR2) is 1 and the CS
bit in PMR3 is 1.

Serial
communication
interface (SCI)
pins

Table 1-3 Pin Functions (cont)

Pin No.

Type

Symbol FP-64A DP-64S I/O

Name and Functions

I/O ports

9 to 2

18 to 11 Input

Port 0: This is an 8-bit input port.

Input

Port 1 (bit 7): This is a 1-bit high-
voltage input pin.

Input

Port 1 (bit 6): This is a 1-bit input pin.

, P1

, 21 to 18 30 to 27 I/O

Port 1: This is a 4-bit group of I/O pins.

, P1

Input or output can be designated for
each bit by means of port control
register 1 (PCR1).

23 to 30 32 to 39 I/O

Port 4: This is an 8-bit high-voltage I/O

port.

38 to 31 47 to 40 I/O

Port 5: This is an 8-bit high-voltage I/O

port.

47 to 40 56 to 49 I/O

Port 6: This is an 8-bit high-voltage I/O

port.

55 to 48 64 to 57 I/O

Port 7: This is an 8-bit high-voltage I/O

port.

64 to 57 9 to 2

I/O

Port 9: This is an 8-bit I/O port. Input or

output can be designated for each bit by
means of PCR9.

A/D converter

9 to 2

18 to 11 Input

Analog input channels 7 to 0: These

are analog data input channels to the
A/D converter.

VFD controller/

55 to 40 64 to 49 Output VFD digit output: These are digit output

driver

pins from the VFD controller/driver.

23 to 38 32 to 47 I/O

VFD segment output: These are

40 to 47 49 to 56

segment output pins from the VFD
controller/driver. When a key scan
interval is set during display operations,
these pins can be used by the CPU
during this interval as general-purpose
I/O ports.

Section 2 CPU

2.1 Overview

The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit
registers. Its concise, optimized instruction set is designed for high-speed operation.

2.1.1 Features

The main features of the H8/300L CPU are listed below.

�

General-register architecture
-- Sixteen 8-bit general registers, also usable as eight 16-bit general registers

�

Instruction set with 55 basic instructions, including:
-- Multiply and divide instructions
-- Powerful bit-manipulation instructions

�

Eight addressing modes
-- Register direct

-- Register indirect

@Rn

-- Register indirect with displacement

@(d:16, Rn)

-- Register indirect with post-increment or pre-decrement

@Rn+ or @�Rn

-- Absolute address

@aa:8 or @aa:16

-- Immediate

#xx:8 or #xx:16

-- Program-counter relative

@(d:8, PC)

-- Memory indirect

@@aa:8

�

64-kbyte address space

�

High-speed operation
-- All frequently used instructions are executed in two to four states
-- High-speed arithmetic and logic operations
-- 8- or 16-bit register-register add or subtract: 0.5 �s*
-- 8

�

8-bit multiply:

3.5 �s*

-- 16 � 8-bit divide:

3.5 �s*

�

Low-power operation modes
-- SLEEP instruction for transfer to low-power operation

Note: * These values are at

= 4 MHz.

2.2 Register Descriptions

2.2.1 General Registers

All the general registers can be used as both data registers and address registers.

When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes
(R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers.

When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7).

R7 also functions as the stack pointer (SP), used implicitly by hardware in exception processing
and subroutine calls. When it functions as the stack pointer, as indicated in figure 2-3, SP (R7)
points to the top of the stack.

Figure 2-3 Stack Pointer

2.2.2 Control Registers

The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code
register (CCR).

Program Counter (PC): This 16-bit register indicates the address of the next instruction the
CPU will execute. All instructions are fetched 16 bits (1 word) at a time, so the least
significant bit of the PC is ignored (always regarded as 0).

Condition Code Register (CCR): This 8-bit register contains internal status information,
including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V),
and carry (C) flags.

Lower address side [H'0000]

Upper address side [H'FFFF]

Unused area

Stack area

SP (R7)

Bit 7--Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1
automatically at the start of exception handling. The interrupt mask bit may be read and written
by software. For further details, see 3.2.2, Interrupts.

Bit 6--User Bit (U): Can be written and read by software (using the LDC, STC, ANDC, ORC,
and XORC instructions).

Bit 5--Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0
otherwise.

The H flag is used implicitly by the DAA and DAS instructions.

When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 11, and is cleared to 0 otherwise.

Bit 4--User Bit (U): Can be written and read by software (using the LDC, STC, ANDC, ORC,
and XORC instructions).

Bit 3--Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an
instruction.

Bit 2--Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.

Bit 1--Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.

Bit 0--Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:

�

Add instructions, to indicate a carry

�

Subtract instructions, to indicate a borrow

�

Shift and rotate instructions, to store the value shifted out of the end bit

The carry flag is also used as a bit accumulator by bit manipulation instructions.

Some instructions leave some or all of the flag bits unchanged. The LDC, STC, ANDC, ORC, and
XORC instructions enable the CPU to load and store the CCR, and to set or clear selected bits by
logic operations. The N, Z, V, and C flags are used as branching conditions for conditional
branching (Bcc) instructions.

Refer to the H8/300L Series Programming Manual for the action of each instruction on the flag
bits.

2.2.3 Initial Register Values

When the CPU is reset, the program counter (PC) is initialized to the value stored at address
H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general
registers are not initialized. In particular, the stack pointer (R7) is not initialized. To prevent
program crashes the stack pointer should be initialized by software, by the first instruction
executed after a reset.

2.3 Data Formats

The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word)
data.

�

Bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand
(n = 0, 1, 2, ..., 7).

�

All arithmetic and logic instructions except ADDS and SUBS can operate on byte data.

�

The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits

�

8 bits), and

DIVXU (16 bits � 8 bits) instructions operate on word data.

�

The DAA and DAS instructions perform decimal arithmetic adjustments on byte data in
packed BCD form. Each nibble of the byte is treated as a decimal digit.

2.3.2 Memory Data Formats

Figure 2-5 indicates the data formats in memory. For access by the H8/300L CPU, word data
stored in memory must always begin at an even address. In word access the least significant bit of
the address is regarded as 0. If an odd address is specified, the access is performed at the
preceding even address. This rule affects the MOV.W instruction, and also applies to instruction
fetching.

Word access is possible to the ROM and RAM areas. For details, see 2.8.1, Notes on Data Access.

Figure 2-5 Memory Data Formats

When the stack is accessed using R7 as an address register, word access should always be
performed. For further details, see 3.2.10, Notes on Stack Area Use. When the CCR is pushed on
the stack, two identical copies of the CCR are pushed to make a complete word. When they are
restored, the lower byte is ignored.

Data Format

Address

Data Type

Address n

MSB

LSB

MSB

LSB

Upper 8 bits

Lower 8 bits

MSB

LSB

CCR

MSB

LSB

MSB

LSB

Address n

Even address

Odd address

Even address

Odd address

Even address

Odd address

1-bit data

Byte data

Word data

Byte data (CCR) on stack

Word data on stack

Note:

Ignored on return

Notation:
CCR: Condition code register

2.4 Addressing Modes

2.4.1 Addressing Modes

The H8/300L CPU supports the eight addressing modes listed in table 2-1. Each instruction uses a
subset of these addressing modes.

Table 2-1 Addressing Modes

No.

Address Modes

Symbol

@Rn

@(d:16, Rn)

@Rn+

@�Rn

Absolute address

@aa:8 or @aa:16

Immediate

#xx:8 or #xx:16

Program-counter relative

@(d:8, PC)

Memory indirect

@@aa:8

Register Direct--Rn: The register field of the instruction specifies an 8- or 16-bit general
register containing the operand.

Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits

�

8 bits), and

DIVXU (16 bits � 8 bits) instructions have 16-bit operands.

Register Indirect--@Rn: The register field of the instruction specifies a 16-bit general
register containing the address of the operand.

Register Indirect with Displacement--@(d:16, Rn): The instruction has a second word
(bytes 3 and 4) containing a displacement which is added to the contents of the specified
general register to obtain the operand address.

This mode is used only in MOV instructions. For the MOV.W instruction, the resulting
address must be even.

Register Indirect with Post-Increment or Pre-Decrement--@Rn+ or @�Rn:

�

The @Rn+ mode is used with MOV instructions that load registers from memory.

The register field of the instruction specifies a 16-bit general register containing the
address of the operand. After the operand is accessed, the register is incremented by 1 for
MOV.B or 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register
must be even.

�

The @�Rn mode is used with MOV instructions that store register contents to memory.

The register field of the instruction specifies a 16-bit general register which is decremented
by 1 or 2 to obtain the address of the operand in memory. The register retains the
decremented value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For
MOV.W, the original contents of the register must be even.

Absolute Address--@aa:8 or @aa:16: The instruction specifies the absolute address of the
operand in memory.

The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and
bit manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP,
and JSR instructions can use 16-bit absolute addresses.

For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range
is H'FF00 to H'FFFF (65280 to 65535).

Immediate--#xx:8 or #xx:16: The instruction contains an 8-bit operand (#xx:8) in its
second byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. Only MOV.W
instructions can contain 16-bit immediate values.

The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data.
Some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte
of the instruction, specifying a bit number.

Program-Counter Relative--@(d:8, PC): This mode is used in the Bcc and BSR
instructions. An 8-bit displacement in byte 2 of the instruction code is sign-extended to
16 bits and added to the program counter contents to generate a branch destination address.
The possible branching range is �126 to +128 bytes (�63 to +64 words) from the current
address. The displacement should be an even number.

Memory Indirect--@@aa:8: This mode can be used by the JMP and JSR instructions. The
second byte of the instruction code specifies an 8-bit absolute address. The word located at
this address contains the branch destination address.

The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is
from H'0000 to H'00FF (0 to 255). Note that with the H8/3714 Series, addresses H'0000 to
H'002B (0 to 43) are located in the vector table.

If an odd address is specified as a branch destination or as the operand address of a MOV.W
instruction, the least significant bit is regarded as 0, causing word access to be performed at
the address preceding the specified address. See 2.3.2, Memory Data Formats, for further
information.

2.4.2 Effective Address Calculation

Table 2-2 shows how effective addresses are calculated in each of the addressing modes.

Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX,
CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6).

Data transfer instructions can use all addressing modes except program-counter relative (7) and
memory indirect (8).

Bit manipulation instructions use register direct (1), register indirect (2), or absolute addressing (5)
to specify a byte operand, and 3-bit immediate addressing (6) to specify a bit position in that byte.
The BSET, BCLR, BNOT, and BTST instructions can also use register direct addressing (1) to
specify the bit position.

2.5 Instruction Set

The H8/300L CPU can use a total of 55 instructions, which are grouped by function in table 2-3.

Table 2-3 Instruction Set

Function

Instructions

Types

Data transfer

MOV, PUSH

, POP

Arithmetic operations

ADD, SUB, ADDX, SUBX, INC, DEC, ADDS,

SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG

Logic operations

AND, OR, XOR, NOT

Shift

SHAL, SHAR, SHLL, SHLR, ROTL, ROTR,

ROTXL, ROTXR

Bit manipulation

BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR,

BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST

Branch

Bcc

, JMP, BSR, JSR, RTS

System control

RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP

Block data transfer

EEPMOV

Total: 55

Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @�SP.

POP Rn is equivalent to MOV.W @SP+, Rn.

2. Bcc is the generic designation of a conditional branch instruction.

The following sections give a concise summary of the instructions in each category, and indicate
the bit patterns of their object code. The notation used is defined next.

2.5.2 Arithmetic Operations

Table 2-5 describes the arithmetic instructions. See figure 3-6 in section 3.5.4, Shift Operations
for their object codes.

Table 2-5 Arithmetic Instructions

Instruction

Size

Function

ADD

B/W

Rd � Rs

Rd, Rd + #IMM

SUB

Performs addition or subtraction on data in two general registers, or
addition on immediate data and data in a general register. Immediate
data cannot be subtracted from data in a general register. Word data
can be added or subtracted only when both words are in general
registers.

ADDX

Rd � Rs � C

Rd, Rd � #IMM � C

SUBX

Performs addition or subtraction with carry or borrow on byte data in
two general registers, or addition or subtraction on immediate data and
data in a general register.

INC

Rd � 1

DEC

Increments or decrements a general register.

ADDS

Rd � 1

Rd, Rd � 2

SUBS

Adds or subtracts immediate data to or from data in a general register.
The immediate data must be 1 or 2.

Rd decimal adjust

Decimal-adjusts (adjusts to packed BCD) an addition or subtraction
result in a general register by referring to the CCR.

MULXU

�

Performs 8-bit

�

8-bit unsigned multiplication on data in two general

registers, providing a 16-bit result.

DIVXU

Rd � Rs

Performs 16-bit � 8-bit unsigned division on data in two general
registers, providing an 8-bit quotient and 8-bit remainder.

CMP

B/W

Rd � Rs, Rd � #IMM
Compares data in a general register with data in another general
register or with immediate data, and sets the CCR according to the
result. Word data can be compared only between two general
registers.

NEG

0 � Rd

Obtains the two's complement (arithmetic complement) of data in a
general register.

Notes:

Size: Operand size
B:

Byte

Word

DAA
DAS

2.5.3 Logic Operations

Table 2-6 describes the four instructions that perform logic operations.

Table 2-6 Logic Operation Instructions

Instruction

Size

Function

AND

Rd, Rd

#IMM

Performs a logical AND operation on a general register and another
general register or immediate data.

Rd, Rd

#IMM

Performs a logical OR operation on a general register and another
general register or immediate data.

XOR

Rd, Rd

#IMM

Performs a logical exclusive OR operation on a general register and
another general register or immediate data.

NOT

~ Rd

Obtains the one's complement (logical complement) of general register
contents.

Notes:

Size: Operand size
B:

Byte

2.5.4 Shift Operations

Table 2-7 describes the eight shift instructions.

Table 2-7 Shift Instructions

Instruction

Size

Function

Rd shift

Performs an arithmetic shift operation on general register contents.

Rd shift

Performs a logical shift operation on general register contents.

Rd rotate

Rotates general register contents.

Rd rotate through carry

Rotates general register contents through the C (carry) bit.

Notes:

Size: Operand size
B:

Byte

SHAL
SHAR

SHLL
SHLR

ROTL
ROTR

ROTXL
ROTXR

2.5.5 Bit Manipulations

Table 2-8 describes the bit-manipulation instructions. Figure 2-8 shows their object code formats.

Table 2-8 Bit-Manipulation Instructions

Instruction

Size

Function

BSET

(<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.

BCLR

(<bit-No.> of <EAd>)

Clears a specified bit in a general register or memory to 0. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.

BNOT

~ (<bit-No.> of <EAd>)

(<bit-No.> of <EAd>)

Inverts a specified bit in a general register or memory. The bit number
is specified by 3-bit immediate data or the lower three bits of a general
register.

BTST

~ (<bit-No.> of <EAd>)

Tests a specified bit in a general register or memory and sets or clears
the zero flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.

BAND

(<bit-No.> of <EAd>)

ANDs the carry flag with a specified bit in a general register or memory
and stores the result in the carry flag.

BIAND

[~ (<bit-No.> of <EAd>)]

ANDs the carry flag with the inverse of a specified bit in a general
register or memory and stores the result in the carry flag.

The bit number is specified by 3-bit immediate data.

BOR

(<bit-No.> of <EAd>)

ORs the carry flag with a specified bit in a general register or memory
and stores the result in the carry flag.

BIOR

[~ (<bit-No.> of <EAd>)]

ORs the carry flag with the inverse of a specified bit in a general
register or memory and stores the result in the carry flag.

The bit number is specified by 3-bit immediate data.

Notes:

Size: Operand size
B:

Byte

Table 2-8 Bit-Manipulation Instructions (cont)

Instruction

Size

Function

BXOR

(<bit-No.> of <EAd>)

XORs the carry flag with a specified bit in a general register or memory
and stores the result in the carry flag.

BIXOR

~ [(<bit-No.> of <EAd>)]

XORs the carry flag with the inverse of a specified bit in a general
register or memory and stores the result in the carry flag.

The bit number is specified by 3-bit immediate data.

BLD

(<bit-No.> of <EAd>)

Copies a specified bit in a general register or memory to the carry flag.

BILD

~ (<bit-No.> of <EAd>)

Copies the inverse of a specified bit in a general register or memory to
the carry flag.

The bit number is specified by 3-bit immediate data.

BST

(<bit-No.> of <EAd>)

Copies the carry flag to a specified bit in a general register or memory.

BIST

~ C

(<bit-No.> of <EAd>)

Copies the inverse of the carry flag to a specified bit in a general
register or memory.

The bit number is specified by 3-bit immediate data.

Notes:

Size: Operand size
B:

Byte

Certain precautions are required in bit manipulation. See 2.8.2, Notes on Bit Manipulation, for
details.

Figure 2-8 Bit Manipulation Instruction Codes

IMM

Operand:
Bit No.:

Notation:
op:
rm, rn:
abs:
IMM:

Operation field
Register field
Absolute address
Immediate data

BSET, BCLR, BNOT, BTST

Operand:
Bit No.:

Operand:

Bit No.:

immediate (#xx:3)

IMM

Operand:

Bit No.:

Operand:

Bit No.:

absolute (@aa:8)

immediate (#xx:3)

abs

IMM

Operand:

Bit No.:

absolute (@aa:8)

abs

IMM

Operand:
Bit No.:

BAND, BOR, BXOR, BLD, BST

Operand:

Bit No.:

immediate (#xx:3)

IMM

Operand:

Bit No.:

absolute (@aa:8)

immediate (#xx:3)

abs

IMM

2.5.7 System Control Instructions

Table 2-10 describes the system control instructions. Figure 2-10 shows their object code formats.

Table 2-10 System Control Instructions

Instruction

Size

Function

RTE

Returns from an exception-handling routine.

SLEEP

Causes a transition from active mode to a power-down mode (sleep
mode, standby mode, or watch mode), or from subactive mode to watch
mode, or from subactive mode via watch mode to active mode. For
details, see 3.3, System Modes.

LDC

CCR, #IMM

CCR

Moves immediate data or general register contents to the condition code
register.

STC

CCR

Copies the condition code register to a specified general register.

ANDC

CCR

#IMM

CCR

Logically ANDs the condition code register with immediate data.

ORC

CCR

#IMM

CCR

Logically ORs the condition code register with immediate data.

XORC

CCR

#IMM

CCR

Logically exclusive-ORs the condition code register with immediate data.

NOP

PC + 2

Only increments the program counter.

Notes:

Size: Operand size
B:

Byte

Figure 2-13 State Transitions

2.6.2 Program Execution State

In the program execution state the CPU executes program instructions in sequence.

There are two modes in this state, active mode and subactive mode. Operation is synchronized
with the system clock in active mode, and with a subclock in subactive mode. For details on these
modes, see 3.3, System Modes.

2.6.3 Program Halt State

In the program halt state there are three modes: sleep mode, standby mode, and watch mode. For
details on these modes, see 3.3, System Modes.

2.6.4 Exception-Handling State

The exception-handling state is a transient state occurring when exception handling is started by a
reset or interrupt, and the CPU changes its normal processing flow. In exception handling caused
by an interrupt, SP (R7) is referenced and the PC and CCR values are saved on the stack.

For details on interrupt handling, see 3.2.2, Interrupts.

Reset state

Program halt state

Exception-handling state

Program execution state

Reset cleared

SLEEP instruction executed

Reset
occurs

Interrupt

Reset
occurs

Exception-
handling
request

Exception-
handling
ends

Note: On the transitions between modes, see 3.3, System Modes.

Reset occurs

2.7 Basic Operation Timing

CPU operation is synchronized by a clock (

is either the system clock (

) generated by the

system clock oscillator circuit, or the subclock (

SUB

) generated by the subclock oscillator circuit.

denotes

in active mode and

SUB

in subactive mode. For details, see section 6, Clock Pulse

Generators. The period from the rising edge of

to the next rising edge is called one state. A

memory cycle or bus cycle consists of two states; access to on-chip memory and to on-chip
peripheral modules always takes place in two states.

2.7.1 Access to On-Chip Memory (RAM, ROM)

Two-state access is employed for on-chip memory. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2-14 shows the on-chip memory access cycle.

Figure 2-14 On-Chip Memory Access Cycle

state

Bus cycle

state

Internal address bus

Internal read signal

Internal data bus
(read access)

Internal write signal

Read data

Address

Write data

Internal data bus
(write access)

2.8 Application Notes

The following points are to be observed in using the H8/300L CPU.

2.8.1 Notes on Data Access

The address space of the H8/300L CPU includes some empty areas in addition to the RAM,
registers, and ROM areas available to the user. If these empty areas are mistakenly accessed
by an application program, the following results will occur.

Transfer from CPU to empty area:

The transferred data will be lost. This action may also cause the CPU to misoperate.

Transfer from empty area to CPU:

Unpredictiable data is transferred.

Internal data transfer to or from on-chip modules other than ROM and RAM areas makes use
of an 8-bit data width. If word access is attempted to these areas, the following results will
occur.

Word access from CPU to I/O register area:

Upper byte: Will be written to I/O register.

Lower byte: Transferred data will be lost.

Word access from I/O register to CPU:

Upper byte: Will be written to upper part of CPU register.

Lower byte: Data written to lower part of CPU register cannot be guaranteed.

Byte size instructions should therefore be used when transferring data to or from I/O registers
outside the on-chip ROM and RAM areas. Figure 2-16 shows the data size in which access
can be made with on-chip peripheral modules.

2.8.2 Notes on Bit Manipulation

The H8/300L CPU executes bit manipulation instructions by a read-modify-write operation on
8-bit data. When bit manipulation instructions are executed in the cases illustrated below, care
must be taken since the operation may affect other bits besides those being manipulated.

Bit manipulation in two registers assigned to the same address (when the source and
destination are different)

Example 1: Timer load register and timer counter

In this example, a bit manipulation instruction is executed in the timer load register and timer
counter of a reloadable timer. Since the timer load register and timer counter share the same
address, the operations take place as follows.

Read: The timer counter value at the time is read.

Modify: The CPU modifies (sets or resets) the bit designated with the instruction. (Other bits
remain the same.)

Write: The modified data is written to the timer load register.

The timer counter is counting based on the system clock (

), so the value read is not necessarily

the same as the value in the timer load register. As a result, bits other than the intended bit in the
timer load register may be modified to the timer counter value.

Figure 2-17 shows the reloadable timer configuration.

Figure 2-17 Reloadable Timer Configuration

Example 2: Port data register (pin input and data register)

When a bit manipulation instruction is executed designating a port data register, it may cause
changes in pin I/O states or data register contents other than the intended bit.

R:
W:

Timer counter

Reload

Internal bus

Timer load register

Read
Write

As noted above, the H8/300L CPU executes bit manipulation instructions by a read-modify-write
operation on 8-bit data. Since the same address is used for the I/O port data register and reading
of pin input, a bit manipulation instruction designating a port functions as follows.

High-voltage pin: pin other than the modified bit

� When set as an input pin (data register = 0)

First the CPU reads the pin input level (read), then it sets or resets the designated bit
(modify; other bits remain the same), and writes that value to the data register (write). If
the input level is high (read data = 1), a value of 1 is written to the data register, changing
the input pin to an output pin (high-level output). If the input level is low, no change
occurs.

� When set as an output pin (data register = 1, high-level output)

If the output level is higher than the input high level (V

), there is no change.

If the output level is lower than the input low level (V

), a value of 0 is written to the data

If the output level is pulled down by the load to an intermediate level, the resulting state is
indeterminate.

Standard-voltage pin: pin other than the modified bit

�

When set as an input pin

The CPU reads the pin input level and writes that value to the data register, which may or
may not result in a change to the data register contents.

�

When set as an output pin

The data register is read, so no change occurs.

Bit manipulation in registers containing write-only bits

Example: PWM data registers, etc.

(Note that read and write characteristics can differ from bit to bit.)

Write-only bits cannot be read. Write-only bits other than the intended bit are set to 1.

Table 2-12 lists the registers that share the same address, while table 2-13 lists the registers that
contain write-only bits.

Table 2-12 Registers Assigned to the Same Address

Register Name

Abbreviation

Address

Timer load register B/timer counter B

TLB/TCB

H'FFC3

Timer load register C/timer counter C

TLC/TCC

H'FFC5

Timer load register E/timer counter E

TLE/TCE

H'FFC9

Port data register 1

PDR1

H'FFD1

Port data register 4

PDR4

H'FFD4

Port data register 5

PDR5

H'FFD5

Port data register 6

PDR6

H'FFD6

Port data register 7

PDR7

H'FFD7

Port data register 9

PDR9

H'FFD9

Note:

These port data registers are used also for pin input.

Table 2-13 Registers with Write-Only Bits

Register Name

Abbreviation

Address

Serial mode register 1

SMR1

H'FFB0

PWM control register

PWCR

H'FFCC

PWM data register U

PWDRU

H'FFCD

PWM data register L

PWDRL

H'FFCE

Port control register 1

PCR1

H'FFE1

Port control register 9

PCR9

H'FFE9

Port mode register 0

PMR0

H'FFEF

Timer mode register D

TMD

H'FFC6

System control register 2

SYSCR2

H'FFF1

Notes: 1. Only bit CRL (bit 7) is write-only.

2. Bit DTON (bit 3) is a write-only bit only in subactive mode. In active mode it cannot be

read or written.

Section 3 System Control

3.1 Overview

This section explains the reset state, exception handling, and system modes.

3.2 Exception Handling

Exception handling includes processing of reset exceptions and of interrupts. Table 3-1
summarizes the exception sources and their priorities. Reset exception handling has the highest
priority.

Table 3-1 Types of Exception Handling and Priorities

Priority

Exception Source

Timing for Start of Exception Handling

High

Reset

Reset exception handling starts as soon as RES pin changes
from low to high.

Interrupt

When interrupt request is made, interrupt exception handling

Low

starts after execution of present instruction is completed.

3.2.1 Reset

When the

RES pin goes low, all processing stops and the chip enters the reset state. The internal

state of the CPU and the registers of on-chip peripheral modules are initialized. The I bit of the
condition code register (CCR) is set, masking all interrupts.

As soon as the

RES pin goes from low to high, reset exception handling starts. The contents of

the reset vector address (H'0000 to H'0001) are read and loaded into the program counter (PC).
Then program execution starts from the address indicated in PC. Figure 3-1 shows the reset
sequence.

Notes: 1. To make sure a reset is carried out properly, when power is turned on the

RES pin

should be kept low for at least 20 ms after the rise of the power supply.

2. When resetting during operation, keep the

RES pin low for at least 10 system clock

cycles.

3. After a reset, if an interrupt were to be accepted before the stack pointer (SP: R7) was

initialized, PC and CCR would not be pushed onto the stack correctly, resulting in
program runaway. To prevent this, immediately after reset exception handling all
interrupts are masked. Programs should be coded to initialize the stack pointer before
clearing the interrupt mask. An even-numbered address must be set in SP. It is
recommended that programs start with an instruction initializing SP (e.g., MOV.W
#xx:16, SP).

Figure 3-1 Reset Sequence

3.2.2 Interrupts

The interrupt sources include external interrupts (IRQ

, IRQ

), and internal interrupts

requested from on-chip peripheral modules. Table 3-2 shows the interrupt sources, their priorities,
and their vector addresses. When more than one interrupt is requested, the interrupt with the
highest priority is processed.

The interrupts have the following features.

�

Both internal interrupts and external interrupts (IRQ

, IRQ

), can be masked by

the I bit of CCR. When this bit is set to 1, interrupt request flags are set but interrupts are not
accepted.

�

External interrupt pins IRQ

, IRQ

, and IRQ

can be set independently for rising-edge or

falling-edge sensing. For external interrupt pin IRQ

, the falling edge is sensed.

Vector fetch

Internal
address bus

Internal read
signal

Internal write
signal

Internal data
bus (16 bits)

RES

Internal

processing

Prefetch of
first instruction
of program

(1) Reset exception handling vector address (H'0000)
(2) Program starting address
(3) First instruction of program

(2)

(1)

(3)

(2)

Reset state

Reset exception handling and program execution

3.2.3 Interrupt Control Registers

Table 3-3 lists the registers that are used to control interrupts.

Table 3-3 Interrupt Control Registers

Register Name

Abbreviation

R/W

Initial Value

Address

Port mode register 1

PMR1

R/W

H'0C

H'FFEB

IRQ edge select register

IEGR

R/W

H'EC

H'FFF2

Interrupt enable register 1

IENR1

R/W

H'C0

H'FFF3

Interrupt enable register 2

IENR2

R/W

H'00

H'FFF4

Interrupt enable register 3

IENR3

R/W

H'3C

H'FFF5

Interrupt request register 1

IRR1

R/W

H'C0

H'FFF6

Interrupt request register 2

IRR2

R/W

H'00

H'FFF7

Interrupt request register 3

IRR3

R/W

H'3C

H'FFF8

Note:

Write is enabled only for writing of 0 to clear flag.

Port mode register 1 (PMR1)

PMR1 is an 8-bit read/write register that designates whether pins in port 1 are used for general-
purpose I/O or for external interrupt input. It is also used to turn the noise canceller function of
pin IRQ

on or off.

Note: Before switching a pin function by modifying bit IRQ5, IRQ4, IRQ1, or IRQ0 in PMR1,

first clear the interrupt enable flag to disable the interrupt. After the pin function has been
switched, issue any instruction, then clear the interrupt request flag to 0.

Program example:

MOV. B R0L, @IENR1

...................... Disable interrupt

MOV. B R0L, @PMR1

...................... Change pin function

NOP

...................... Issue any instruction

MOV. B R0L, @IRR1

...................... Clear interrupt request flag

MOV. B R1L, @IENR1

...................... Enable interrupt

Bit

Initial value

Read/Write

R/W

EVENT

R/W

IRQC5

R/W

IRQC4

R/W

IRQC0

R/W

IRQC1

R/W

NOISE

CANCEL

Bit 7: Noise cancel (NOISE CANCEL)

This bit enables or disables the noise canceller function of pin IRQ

Bit 7
NOISE CANCEL

Description

Disables the noise canceller function of pin IRQ

(initial value)

Enables the noise canceller function of pin IRQ

. Input is sampled at

intervals of 256 states. If two consecutive values do not match, the input is
regarded as noise.

Bit 6: P1

EVENT pin function switch (EVENT)

Bit 6
EVENT

Description

EVENT

pin functions as P1

pin.

(initial value)

EVENT

pin functions as

EVENT

pin.

Bit 5: P1

/IRQ

/TMOE pin function switch (IRQC5)

Bit 5
IRQC5

Description

/IRQ

/TMOE pin functions as P1

/TMOE pin.

(initial value)

/IRQ

/TMOE pin functions as IRQ

pin.

Note:

For the TMOE usage of this pin, see 7.3.2, Port Mode Register 4 .

Bit 4: P1

/IRQ

pin function switch (IRQC4)

Bit 4
IRQC4

Description

/IRQ

pin functions as P1

pin.

(initial value)

/IRQ

pin functions as IRQ

pin.

Bits 3 and 2: Reserved bits

Bits 3 and 2 are reserved; they always read 1, and cannot be modified.

Bit 1: P1

/IRQ

pin function switch (IRQC1)

Bit 1
IRQC1

Description

/IRQ

pin functions as P1

pin.

(initial value)

/IRQ

pin functions as IRQ

pin.

Bit 0: P1

/IRQ

pin function switch (IRQC0)

Bit 0
IRQC0

Description

/IRQ

pin functions as P1

pin.

(initial value)

/IRQ

pin functions as IRQ

pin.

IRQ edge select register (IEGR)

IEGR is an 8-bit read/write register, used to designate rising edge sensing or falling edge sensing
for pins IRQ

, IRQ

, and IRQ

Bits 7 to 5: Reserved bits

Bits 7 to 5 are reserved; they always read 1, and cannot be modified.

Bit 4: IRQ

pin input edge select (IEG4)

Bit 4
IEG4

Description

Falling edge of IRQ

pin input is detected.

(initial value)

Rising edge of IRQ

pin input is detected.

Bits 3 and 2: Reserved bits

Bits 3 and 2 are reserved; they always read 1, and cannot be modified.

Bit

Initial value

Read/Write

IEG4

R/W

IEG0

R/W

IEG1

R/W

Bit 1: IRQ

pin input edge select (IEG1)

Bit 1
IEG1

Description

Falling edge of IRQ

pin input is detected.

(initial value)

Rising edge of IRQ

pin input is detected.

Bit 0: IRQ

pin input edge select (IEG0)

Bit 0
IEG0

Description

Falling edge of IRQ

pin input is detected.

(initial value)

Rising edge of IRQ

pin input is detected.

Interrupt enable register 1 (IENR1)

IENR1 is an 8-bit read/write register that enables or disables external interrupts.

Bits 7 and 6: Reserved bits

Bits 7 and 6 are reserved; they always read 1, and cannot be modified.

Bits 5 and 4: IRQ

and IRQ

interrupt enable (IEN5 and IEN4)

Bits 5 and 4
IEN5, IEN4

Description

Disables interrupt requests by IRRI5 and IRRI4.

(initial value)

Enables interrupt requests by IRRI5 and IRRI4.

Bits 3 and 2: Reserved bits

Bits 3 and 2 are reserved, but they can be written and read.

Bits 1 and 0: IRQ

and IRQ

interrupt enable (IEN1 and IEN0)

Bits 1 and 0
IEN1, IEN0

Description

Disables interrupt requests by IRRI1 and IRRI0.

(initial value)

Enables interrupt requests by IRRI1 and IRRI0.

Bit

Initial value

Read/Write

IEN5

R/W

IEN4

R/W

IEN0

R/W

IEN1

R/W

Interrupt enable register 2 (IENR2)

IENR2 is an 8-bit read/write register that enables or disables direct transfer interrupts and timer A
to E overflow interrupts.

Bits 7 and 6: Reserved bits

Bits 7 and 6 are reserved, but they can be written and read.

Bit 5: Direct transfer interrupt enable (IENDT)

Bit 5
IENDT

Description

Disables direct transfer interrupt requests by IRRDT.

(initial value)

Enables interrupt requests by IRRDT.

Bits 4 to 0: Timer E to A interrupt enable (IENTE to IENTA)

Bits 4 to 0
IENTE to IENTA

Description

Disables interrupt requests by IRRTE to IRRTA.

(initial value)

Enables interrupt requests by IRRTE to IRRTA.

Interrupt enable register 3 (IENR3)

IENR3 is an 8-bit read/write register that enables or disables A/D converter, key scan, and serial
communication interface 1 and 2 interrupts.

Bit

Initial value

Read/Write

R/W

IENDT

R/W

IENTE

R/W

IENTD

R/W

IENTA

R/W

IENTC

R/W

IENTB

R/W

Bit

Initial value

Read/Write

IENAD

R/W

IENKS

R/W

IENS1

R/W

IENS2

R/W

Bit 7: A/D converter interrupt enable (IENAD)

Bit 7
IENAD

Description

Disables interrupt requests by IRRAD.

(initial value)

Enables interrupt requests by IRRAD.

Bit 6: Key scan interrupt enable (IENKS)

Bit 6
IENKS

Description

Disables interrupt requests by IRRKS.

(initial value)

Enables interrupt requests by IRRKS.

Bits 5 to 2: Reserved bits

Bits 5 to 2 are reserved; they always read 1, and cannot be modified.

Bits 1 and 0: Serial communication interface 2 and 1 interrupt enable (IENS2 and IENS1)

Bits 1 and 0
IENS2, IENS1

Description

Disables interrupt requests by IRRS2 and IRRS1.

(initial value)

Enables interrupt requests by IRRS2 and IRRS1.

Interrupt request register 1 (IRR1)

Note:

Only 0 can be written, to clear the flag.

IRR1 is an 8-bit read/write register with flags that are set to 1 when an external interrupt is
requested.

Bits 7 and 6: Reserved bits

Bits 7 and 6 are reserved; they always read 1, and cannot be modified.

Bit

Initial value

Read/Write

IRRI5

R/W

IRRI4

R/W

IRRI0

R/W

IRRI1

R/W

Bits 5 and 4: IRQ

and IRQ

interrupt request (IRRI5 and IRRI4)

Bits 5 and 4
IRRI5, IRRI4

Description

No interrupt request from the corresponding pin (IRQ

or IRQ

). (initial value)

Setting condition: Set when the corresponding pin (IRQ

or IRQ

) is

designated for interrupt input in PMR1 and the designated edge is input.

Clearing method: Cleared when software writes 0 in the flag. (The flag is not
automatically cleared when an interrupt is accepted.)

Bits 3 and 2: Reserved bits

Bits 3 and 2 are reserved; they always read 0, and cannot be modified.

Bits 1 and 0: IRQ

and IRQ

interrupt request (IRRI1 and IRRI0)

Bits 1 and 0
IRRI1, IRRI0

Description

No interrupt request from the corresponding pin (IRQ

or IRQ

). (initial value)

Setting condition: Set when the corresponding pin (IRQ

or IRQ

) is

designated for interrupt input in PMR1 and the designated edge is input.

Clearing method: Cleared when software writes 0 in the flag. (The flag is not
automatically cleared when an interrupt is accepted.)

Interrupt request register 2 (IRR2)

Note:

Only 0 can be written, to clear the flag.

IRR2 is an 8-bit read/write register with flags that are set to 1 when a direct transfer interrupt or
timer A to E overflow interrupt is requested.

Bits 7 and 6: Reserved bits

Bits 7 and 6 are reserved; they always read 0, and only 0 may be written.

Bit

Initial value

Read/Write

IRRDT

R/W

IRRTE

R/W

IRRTD

R/W

IRRTA

R/W

IRRTC

R/W

IRRTB

R/W

Bit 5: Direct transfer interrupt request (IRRDT)

Bits 5
IRRDT

Description

No direct transfer interrupt request.

(initial value)

Setting conditions: In subactive mode, when the system control register 2
(SYSCR2) DTON bit = 1, the system control register 1 (SYSCR1) LSON bit = 0,
and the interrupt enable register 2 (IENR2) IENDT bit = 1, execution of a SLEEP
instruction results in direct transfer to active mode via watch mode. During this
process a direct transfer interrupt is requested and the IRRDT flag is set to 1.

Clearing method: Cleared when software writes 0 in the flag. (The flag is not
automatically cleared when an interrupt is accepted.)

Bits 4 to 0: Timer E to A interrupt request (IRRTE to IRRTA)

Bits 4 to 0
IRRTE to IRRTA

Description

No overflow interrupt request from the corresponding timer

(initial value)

(E to A).

Setting conditions: When a timer E to A overflow interrupt is requested, the
corresponding flag (IRRTE to IRRTA ) is set to 1.

Clearing method: Cleared when software writes 0 in the flag. (The flag is
not automatically cleared when an interrupt is accepted.)

Interrupt request register 3 (IRR3)

Note:

Only 0 can be written, to clear the flag.

Bit 7: A/D conversion complete interrupt request (IRRAD)

Bit 7
IRRAD

Description

No A/D converter interrupt request.

(initial value)

Setting conditions: When the A/D converter completes A/D conversion, an interrupt
is requested and the IRRAD flag is set to 1.

Clearing method: Cleared when software writes 0 in the flag. (The flag is not
automatically cleared when an interrupt is accepted.)

Bit

Initial value

Read/Write

IRRAD

R/W

IRRKS

R/W

IRRS1

R/W

IRRS2

R/W

Bit 6: Key scan interrupt request (IRRKS)

Bit 6
IRRKS

Description

No key scan interrupt request.

(initial value)

Setting conditions: When the VFD controller/driver requests a key scan interrupt,
the IRRKS flag is set to 1.

Clearing method: Cleared when software writes 0 in the flag. (The flag is not
automatically cleared when an interrupt is accepted.)

Bits 5 to 2: Reserved bits

Bits 5 to 2 are reserved; they always read 1, and cannot be modified.

Bits 1 and 0: Serial communication interface 2 and 1 interrupt request (IRRS2, IRRS1)

Bits 1, 0
IRRS2, IRRS1

Description

No transfer complete or error interrupt request by the

(initial value)

corresponding serial communication interface.

Setting conditions: When an interrupt is requested due to transfer complete or
error on serial communication interface 2 or 1, the corresponding flag (IRRS2 or
IRRS1) is set to 1.

Clearing method: Cleared when software writes 0 in the flag. (The flag is not
automatically cleared when an interrupt is accepted.)

3.2.4 External Interrupts

There are four external interrupts, IRQ

, IRQ

, and IRQ

. These interrupts are requested by

means of input signals at pins IRQ

, IRQ

, and IRQ

Interrupts IRQ

, IRQ

, and IRQ

are detected by either rising edge sensing or falling edge

sensing, depending on the settings of bits IEG4, IEG1, and IEG0 in the IRQ edge select register
(IEGR). IRQ

is detected by falling edge sensing only. In order to enable external interrupt input,

it is first necessary to set the corresponding bit in port mode register 1 (PMR1) to 1.

When the designated edge is input at pins IRQ

, IRQ

, and IRQ

, the corresponding flag in

interrupt request register 1 (IRR1) is set to 1. After the interrupt is accepted, the flag that was set
is not automatically cleared, so the interrupt handling routine must be programmed to clear the
flag to 0. A given interrupt request can be disabled by clearing its interrupt enable bit to 0.

Interrupts IRQ

, IRQ

, and IRQ

are enabled by setting bits IEN5, IEN4, IEN1, and IEN0

to 1 in interrupt enable register 1. All interrupts can be masked by setting the I bit in CCR to 1.

When an IRQ

, IRQ

, or IRQ

interrupt request is accepted, the I bit is set to 1. The order

of priority is from IRQ

(high) to IRQ

(low). For details see table 3-2.

A noise canceller function can be selected for IRQ

interrupts, in which case a noise cancellation

circuit samples the IRQ

input every 256 states. If two consecutive sampling results do not match,

noise is assumed and the request is not accepted.

3.2.5 Internal Interrupts

There are ten internal interrupts that can be requested by the on-chip peripheral modules. These
interrupts can be masked (held pending) by setting the I bit in CCR to 1. When an internal
interrupt request is accepted and the interrupt exception handling sequence is executed, the I bit is
set to 1. For the order of priority of interrupts from on-chip peripheral modules, see table 3-2.

3.2.6 Interrupt Operations

Interrupts are controlled by an interrupt controller. Figure 3-2 shows a block diagram of the
interrupt controller, while figure 3-3 shows the flow up to interrupt acceptance.

Figure 3-2 Block Diagram of Interrupt Controller

Interrupt controller

Priority decision

Interrupt
request

CCR (CPU)

IRQ , IQR , IRQ , and
IRQ interrupt request
flags and internal
interrupt request flags

IRQ , IQR , IRQ , and
IRQ interrupt enable
bits and internal
interrupt enable bits

The following operations take place when an interrupt occurs.

When an interrupt is requested by external interrupt pin input or by a peripheral module, an
interrupt request signal is sent to the interrupt controller.

When the interrupt controller receives an interrupt request signal, it sets the interrupt request
flag.

From among the interrupts for which the corresponding interrupt enable bit is also set to 1,
the interrupt controller selects the interrupt request with the highest priority and holds the
others pending. (See table 3-2.)

The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request
is accepted; if the I bit is 1, the interrupt request is held pending.

If the interrupt is accepted, after processing of the current instruction is completed, both PC
and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3-4.
The PC value pushed onto the stack is the address of the first instruction to be executed upon
return from interrupt handling.

The I bit of CCR is set to 1, masking all further interrupts.

A vector address is generated for the accepted interrupt, and the contents of that address are
read and loaded into PC. Program execution then resumes from the address indicated in PC.

Note: No interrupt detection takes place immediately after completion of ORC, ANDC, XORC,

or LDC instructions.

3.2.7 Return from an Interrupt

After completion of interrupt handling, the handler routine ends by executing an RTE instruction,
to resume the original program from the point the interrupt. When RTE is executed, the values
saved on the stack are restored to CCR and PC as shown in figure 3-6. Instruction execution
resumes from the address indicated in PC.

Figure 3-6 Stack State When RTE Instruction is Executed

3.2.8 Interrupt Response Time

Table 3-4 shows the number of wait states after an interrupt request flag is set and until the first
instruction of the interrupt handler is executed.

Table 3-4 Interrupt Wait States

No.

Item

States

Waiting time for completion of current instruction

1 to 13

Saving of PC and CCR to stack

Vector fetch

Instruction fetch

Internal processing

Total

15 to 27

Note:

Not including EEPMOV instruction.

(Processing of RTE instruction)

(Stack state)

Memory contents of address

indicated in SP are sent to CCR.

SP value +2

Memory contents of address

indicated in SP are sent to PC.

SP value +2

CCR

SP (R7)

SP + 1

SP + 2

SP + 3

SP + 4

SP � 4

SP � 3

SP � 2

SP � 1

SP (R7)

CCR

Stack
area

CCR and PC
values restored

Before RTE instruction is executed

After RTE instruction is executed

Ignored on return from interrupt.

Note:

3.2.9 Valid Interrupts in Each Mode

Table 3-5 shows the valid interrupts in each mode. For details of the modes, see 3.3, System
Modes.

Table 3-5 Valid Interrupts in Each Mode

Mode

Interrupt

Active

Sleep

Standby

Watch

Subactive

IRQ

�

IRQ

�

IRQ

�

Key scan

�

Timer A overflow

�

Timer B overflow

�

Timer C overflow

�

Timer D overflow

�

Timer E overflow

�

Direct transfer

�

SCI1 transfer complete or error

�

SCI2 transfer complete or error

�

A/D conversion end

�

Note: The above table does not include interrupts occurring during a mode transition.

Notation:

: When an interrupt request flag is set, interrupt exception handling is started if the I bit = 0 in

CCR and the interrupt enable bit = 1 for that interrupt. In sleep mode, standby mode, and
watch mode, a mode transition takes place before interrupt exception handling starts.

: When a SLEEP instruction is executed while the DTON bit = 1 and the LSON bit = 0, first a

transition is made to watch mode and the interrupt request flag is set in synchronization with
the subclock. When the interrupt request flag is set, if the interrupt enable flag = 1 for that
interrupt and the I bit = 0 in CCR, a transition is made to active mode and interrupt exception
handling starts.

�

The interrupt request flag is not set, and no mode transition occurs.

3.2.10 Notes on Stack Area Use

When word data is accessed in the H8/300L Series, the least significant bit of the address is
regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7)
should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @�SP) or POP Rn (MOV.W
@SP+, Rn) to save or restore register values.

Setting an odd address in SP may cause a program to crash. An example is shown in figure 3-7.

Figure 3-7 CPU Operation When Odd Address is Set in SP

Word access is also performed when the condition code register (CCR) is saved and restored by
the interrupt exception-handling sequence and RTE instruction. When CCR is saved, the CCR
value is saved in both the upper and lower bytes of the word data. When CCR is restored, it is
loaded with the value at the even address. The value at the odd address is ignored.

SP set to H'FEFF

R1L

H'FEFD

H'FEFC

H'FEFF

Stack accessed beyond SP

BSR instruction

Contents of PC are lost

MOV.B R1L, @�R7

Notation:
PC

R1L:
SP:

Upper byte of program counter
Lower byte of program counter
General register R1L
Stack pointer

3.3.1 Active Mode

In active mode, the CPU executes instructions in synchronization with the system clock.

3.3.2 Low-Power Operation Mode

The H8/300L CPU supports four low-power operation modes: sleep mode, standby mode, watch
mode, and subactive mode. These modes are described below.

Sleep mode:

Sleep mode is entered by executing a SLEEP instruction while the SSBY bit
in system control register 1 (SYSCR1) is cleared to 0. As soon as the SLEEP
instruction has been executed, the CPU and on-chip peripheral modules halt
operation, except for timer A. The contents of the internal registers of the
CPU and on-chip peripheral modules, as well as the RAM contents, are
retained.

Standby mode:

Standby mode is entered by executing a SLEEP instruction while the SSBY
bit in system control register 1 (SYSCR1) is set to 1 and timer mode register
A (TMA) bit TMA3 = 0. In this mode, the CPU, system clock, and on-chip
peripheral modules halt all operations. Output from the on-chip peripheral
modules is reset; but as long as a minimum required voltage is applied, the
contents of the internal registers of the CPU and on-chip peripheral modules,
as well as the RAM contents, are retained. Standard I/O ports go to the high-
impedance state. In high-voltage ports, the PMOS buffer transistors are
switched off.

Watch mode:

Watch mode is entered by executing a SLEEP instruction while the SSBY bit
in system control register 1 (SYSCR1) is set to 1 and timer mode register A
(TMA) bit TMA3 = 1. In this mode, the CPU, system clock, and on-chip
peripheral modules halt, except for timer A. Output from the on-chip
peripheral modules is reset; but as long as a minimum required voltage is
applied, the contents of the internal registers of the CPU and on-chip
peripheral modules, as well as the RAM contents, are retained. Standard I/O
ports go to the high-impedance state. In high-voltage ports, the PMOS buffer
transistors are switched off.

Subactive mode:

Subactive mode is entered when a time base or IRQ

interrupt request is

accepted in watch mode while the LSON bit in system control register 1
(SYSCR1) is set to 1. In this mode the CPU operates in synchronization with
the subclock. On-chip peripheral modules halt operation, except for the time-
base function of timer A. Output from the on-chip peripheral modules is
reset; but as long as a minimum required voltage is applied, the contents of the
internal registers of the on-chip peripheral modules are retained. Standard I/O
ports go to the high-impedance state. In high-voltage ports, the PMOS buffer
transistors are switched off.

Table 3-6 shows the internal states in each mode.

Table 3-6 Internal States in Operation Modes

Function

Active

Sleep

Standby

Watch

Subactive

System clock

Functions

Functions Halted

Halted

Subclock

Functions

Functions Functions

Functions

CPU operation

Instructions

Functions

Halted

Functions

RAM

Functions

Retained

Functions

Registers

Functions

Retained

Functions

I/O

Functions

Retained

Functions

IRQ

Functions

Functions Functions

Functions

IRQ

Functions

Functions Functions

Retained

IRQ

, IRQ

Functions

Retained

Timer A

Functions

Functions Retained

Functions

Timer B

Functions

Retained

Timer C

Functions

Retained

Timer D

Functions

Retained

Timer E

Functions

Retained

SCI1, SCI2

Functions

Retained

VFD

Functions

Retained

(output is

reset)

PWM

Functions

Retained

(output is

reset)

A/D

Functions

Retained

Notes: 1. Register contents are retained; output goes to high-impedance state.

2. Input (read) functions.
3. Functions when the time base function is selected.

Peripheral module
interrupts

Sleep mode

Operation in sleep mode is described below.

�

Transition to sleep mode

The system goes from active mode to sleep mode when a SLEEP instruction is executed while
the SSBY bit in system control register 1 (SYSCR1) is cleared to 0. In this mode CPU
operation is halted but the register, RAM, and port contents are retained. The clock pulse
generator operates, as do external interrupts (IRQ

and IRQ

) and timer A.

�

Clearing sleep mode

Sleep mode is cleared by an interrupt (IRQ

, IRQ

, or timer A) or by input at the

RES pin.

-- Clearing by interrupt (IRQ

, IRQ

, or timer A)

When an IRQ

, IRQ

, or timer A interrupt is requested, sleep mode is cleared and interrupt

exception handling starts. Sleep mode is not cleared if the I bit in the condition code
register (CCR) is set to 1 or the particular interrupt is disabled in the interrupt enable
register.

Before transition to sleep mode, other interrupts should be disabled.

-- Clearing by

RES input

When the

RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.

Standby mode

Operation in standby mode is described below.

�

Transition to standby mode

The system goes from active mode to standby mode when a SLEEP instruction is executed
while the SSBY bit in system control register 1 (SYSCR1) is set to 1 and bit TMA3 in timer
mode register A (TMA) is cleared to 0. In standby mode the clock pulse generator stops, so
the CPU and on-chip peripheral modules stop functioning. As long as a minimum required
voltage is applied, the CPU register contents and data in the on-chip RAM will be retained.
Standard I/O ports go to the high-impedance state. In high-voltage ports, the PMOS buffer
transistors are switched off.

�

Clearing standby mode

Standby mode is cleared by an external interrupt (IRQ

, IRQ

) or by input at the

RES pin.

-- Clearing by interrupt (IRQ

, IRQ

)

When an IRQ

or IRQ

interrupt signal is input, the clock pulse generator starts. After the

time set in bits STS2 to STS0 in system control register 1 (SYSCR1) has elapsed, a stable
clock signal is supplied to the entire chip, standby mode is cleared, and interrupt exception
handling starts. Before the transition to standby mode, other interrupts should be disabled.
Standby mode is not cleared if the I bit in the condition code register (CCR) is set to 1 or
the particular interrupt is disabled in the interrupt enable register.

-- Clearing by

RES input

When the

RES pin goes low, the clock pulse generator starts and standby mode is cleared.

After the pulse generator output has stabilized, if the

RES pin is driven high, the CPU

starts reset exception handling.

Since clock signals are supplied to the entire chip as soon as the clock pulse generator
starts functioning, the

RES pin should be kept at the low level until the pulse generator

output stabilizes.

Watch mode

Operation in watch mode is described below.

�

Transition to watch mode

From active mode, watch mode is entered when a SLEEP instruction is executed while the
SSBY bit in system control register 1 (SYSCR1) is set to 1 and bit TMA3 in timer mode
register A (TMA) is set to 1. From subactive mode, watch mode is entered when a SLEEP
instruction is executed while the DTON bit in system control register 2 (SYSCR2) is cleared
to 0.

In watch mode, operation of the system clock pulse generator and of on-chip peripheral
modules is halted, except for the time-base function of timer A. Output from the on-chip
peripheral modules is reset; but as long as a minimum required voltage is applied, the contents
of the internal registers of the CPU and on-chip peripheral modules, and the on-chip RAM
contents, are retained.

�

Clearing watch mode

Watch mode is cleared by a time-base interrupt from timer A, by an IRQ

interrupt, or by

input at the

RES pin.

-- Clearing by timer A time-base interrupt or IRQ

interrupt

When timer A overflows or an IRQ

interrupt signal is input, if the LSON bit in system

control register 1 (SYSCR1) is cleared to 0, the clock pulse generator starts. After the time
set in bits STS2 to STS0 in system control register 1 (SYSCR1) has elapsed, a stable clock
signal is supplied to the entire chip, watch mode is cleared, and interrupt exception
handling starts. If LSON = 1, the system goes to subactive mode.

In watch mode, the subclock (

SUB

) is prescaled to generate a clock signal which is

supplied to timer A. Timer A operates as a time base.

Before the transition to watch mode, other external interrupts should be disabled. Watch
mode is not cleared if the I bit in the condition code register (CCR) is set to 1 or the
particular interrupt is disabled in the interrupt enable register.

-- Clearing by

RES input

When the

RES pin goes low, the clock pulse generator starts and watch mode is cleared.

After the pulse generator output has stabilized, if the

RES pin is driven high, the CPU

starts reset exception handling.

Since clock signals are supplied to the entire chip as soon as the clock pulse generator
starts functioning, the

RES pin should be kept at the low level until the pulse generator

output stabilizes.

Subactive mode

Operation in subactive mode is described below.

�

Transition to subactive mode

Subactive mode is entered from watch mode if the LSON bit in system control register 1
(SYSCR1) is set to 1 at the time of a timer A time-base interrupt or IRQ

interrupt request.

In subactive mode, the CPU operates in synchronization with the subclock (

SUB

). The on-

chip peripheral modules halt operation, except for the time base function of timer A. Output
from the on-chip peripheral modules is reset; but as long as a minimum required voltage is
applied, the contents of the internal registers of the on-chip peripheral modules are retained.
Standard I/O ports go to the high-impedance state. In high-voltage ports, the PMOS buffer
transistors are switched off.

�

Clearing subactive mode

Subactive mode is cleared by a SLEEP instruction or by input at the

RES pin.

-- Clearing by SLEEP instruction

When a SLEEP instruction is executed in subactive mode, subactive mode is cleared.
If the DTON bit of system control register 2 (SYSCR2) is cleared to 0 when the SLEEP
instruction is executed, the system goes to watch mode. If DTON = 1 and
LSON = 0, a direct transfer interrupt is requested and the clock pulse generator starts.
After the time set in bits STS2 to STS0 in system control register 1 (SYSCR1) has elapsed,
a stable clock signal is supplied to the entire chip, and the system goes to active mode.

Before the transition to active mode, other interrupts should be disabled. The direct
transfer from subactive mode to active mode does not take place if the I bit in the condition
code register (CCR) is set to 1 or the direct transfer interrupt is disabled in the interrupt
enable register.

-- Clearing by

RES input

When the

RES pin goes low, the clock pulse generator starts and subactive mode is

cleared. After the pulse generator output has stabilized, if the

RES pin is driven high, the

CPU starts reset exception handling.

Since clock signals are supplied to the entire chip as soon as the clock pulse generator
starts functioning, the

RES pin should be kept at the low level until the pulse generator

output stabilizes.

3.4 System Control Registers

Table 3-7 shows how the system control registers (SYSCR1 and SYSCR2) are configured.
These two registers are used to control the power-down modes.

Table 3-7 Register Configuration

Name

Abbreviation

R/W

Initial Value

Address

System control register 1

SYSCR1

R/W

H'00

H'FFF0

System control register 2

SYSCR2

R/W

H'F4

H'FFF1

3.4.1 System Control Register 1 (SYSCR1)

Note:

Write is enabled only in active mode.

SYSCR1 is an 8-bit read/write register for control of power-down modes.

Bit 7: Standby (SSBY)

This bit designates transition to standby mode.

When standby mode is cleared by an external interrupt and the system goes to active mode, this
bit remains set to 1. It must be cleared by writing a 0. Writing is possible only in active mode.

Bit 7
SSBY

Explanation

When a SLEEP instruction is executed, a transition is made to sleep

(initial value)

mode.

When a SLEEP instruction is executed, a transition is made to standby mode or watch
mode.

Bit

Initial value

Read/Write

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

LSON

R/W

Bits 6 to 4: Standby timer select 2 to 0 (STS2 to STS0)

When a mode in which the system clock is stopped (standby, watch, or subactive mode) is cleared,
the system waits for stable clock operation for a time set in these bits. The designation should be
made according to the clock frequency so that the waiting time is at least 10 ms.

Bit 6

Bit 5

Bit 4

STS2

STS1

STS0

Explanation

Wait time = 8,192

states. (initial value)

Wait time = 16,384 states.

Wait time = 32,768 states.

Wait time = 65,536 states.

Wait time = 131,072 states.

Note:

Don't care.

Bit 3: Low speed on flag (LSON)

This bit chooses the system clock (

) or subclock (

SUB

) as the CPU operating clock when watch

mode is cleared. Since this relates to the transitions between operation modes, this bit functions in
combination with other control bits and interrupt input.

Bit 3
LSON

Explanation

The CPU operates on the system clock (

(initial value)

The CPU operates on the subclock (

SUB

Bit 2: Reserved bit

This bit is reserved, but it can be written and read.

Bits 1 and 0: Reserved bits

These bits are reserved; they always read 0, and cannot be modified.

3.4.2 System Control Register 2 (SYSCR2)

Note:

Write is enabled only in subactive mode.

SYSCR2 is an 8-bit read/write register for control of direct transfer from subactive mode to active
mode.

Bits 7 to 4: Reserved bits

These bits are reserved; they always read 1, and cannot be modified.

Bit 3: Direct transfer on flag (DTON)

This bit designates whether a transition is made to active mode or to watch mode when a SLEEP
instruction is executed in subactive mode. When transfer to active mode is designated, the
transition takes place via watch mode to allow time for the clock pulse generator to stabilize.

Bit 3
DTON

Explanation

When a SLEEP instruction is executed in subactive mode, a transition is

(initial value)

made to watch mode.

When a SLEEP instruction is executed in subactive mode while the LSON bit in system
control register 1 (SYSCR1) is cleared to 0, a direct transfer interrupt is requested, and
the system goes to active mode via watch mode.

Bit 2: Reserved bit

This bit is reserved; it always reads 1, and cannot be modified.

Bits 1 and 0: Reserved bits

These bits are reserved, but they can be written and read.

Bit

Initial value

Read/Write

DTON

R/W

Figure 4-2 Socket Adapter Pin Correspondence

H8/3714

EPROM Socket

FP-64A

56, 1

14, 10

DP-64S

1, 10

23, 19

20, 22

Pin

, AV

TEST, X1

OSC

Pin

HN27C256H

RES

Note: Pins not indicated above should be left open.

4.3 Programming

The write, verify, and other modes are selected as shown in table 4-3 in PROM mode.

Table 4-3 Mode Selection in PROM Mode

Pin

Mode

to EO

to EA

Write

Data input

Address input

Verify

Data output

Address input

Programming disabled

High impedance

Address input

Notation:
L:

Low level

High level

: V

level

: V

level

The specifications for writing and reading the on-chip PROM are identical to those for the
standard HN27C256H EPROM.

4.3.1 Writing and Verifying

An efficient, high-speed programming method is provided for writing and verifying the PROM
data. This method achieves high speed without voltage stress on the device and without lowering
the reliability of written data. H'FF data is written in unused address areas.

The basic flow of this high-speed programming method is shown in figure 4-4. Table 4-4 and
table 4-5 give the electrical characteristics in programming mode. Figure 4-5 shows a timing
diagram.

Table 4-4 DC Characteristics (preliminary)

(Conditions: V

= 6.0 V �0.25 V, V

= 12.5 V �0.3 V, V

= 0.0 V, T

= 25�C �5�C)

Test

Item

Symbol Min

Typ Max

Unit Conditions

Input high-

to EA

2.4

+ 0.3 V

level voltage

Input low-

to EA

�0.3

0.8

level voltage

Output high-

to EO

2.4

= �200 �A

level voltage

Output low-

to EO

0.45

= 1.6 mA

level voltage

Input leakage EO

to EO

, EA

to EA

, |I

�A

current

5.25 V/0.5 V

current

Table 4-5 AC Characteristics

(Conditions: V

= 6.0 V �0.25 V, V

= 12.5 V �0.3 V, V

= 0.0 V, T

= 25�C �5�C)

Item

Symbol

Min

Typ

Max

Unit

Test Conditions

Address setup time

�s

Figure 4-5

setup time

OES

�s

Data setup time

�s

Address hold time

�s

Data hold time

�s

Data output disable time

130

setup time

VPS

�s

Programming pulse width

0.95

1.0

1.05

pulse width for overwrite

OPW

2.85

78.75

programming

setup time

VCS

�s

Data output delay time

500

Notes:

Input pulse level: 0.8 to 2.2 V
Input rise time/fall time

20 ns

Timing reference levels Input:

1.0 V, 2.0 V

Output: 0.8 V, 2.0 V

Section 7 I/O Ports

7.1 Overview

The H8/3714 Series has five 8-bit I/O ports (of which four are high-voltage ports), one 6-bit I/O
port*, and one 8-bit input port. Table 7-1 indicates the functions of each port.

Ports 1 and 9 are standard input/output ports, consisting of a port control register (PCR) that
controls input and output, and a port data register (PDR) for storing output data. Input or output
can be assigned to individual bits.

Ports 4, 5, 6, and 7 are high-voltage ports, able to handle an applied voltage of V

� 40 V. Input

and output are controlled for individual bits by reading from and writing to PDR.

Note: * Pin P1

of port 1 is a high-voltage input-only pin, while pin P1

is a standard input-only

pin. Pins P1

and P1

are not present.

Reading a port gives the following results.

�

Reading a standard port

-- Reading a pin assigned to general-purpose input (PCR = 0) gives the pin level.

-- Reading a pin assigned to general-purpose output (PCR = 1) gives the value of the

corresponding PDR bit.

-- Reading a pin assigned to an on-chip peripheral function gives the pin level.

�

Reading a high-voltage port

-- Reading a pin assigned to general-purpose input/output gives the pin level.

-- Reading a pin assigned to digit output or segment output use gives the value of the

corresponding PDR bit.

105

Table 1 Port Functions

Function
Switching

Port

Description

Pins

Other Functions

Register

Port 0

8-bit standard input port

to P0

Analog data input channels

PMR0

to AN

7 to 0

Port 1

Pin P1

: 1-bit high-voltage

disp

Power supply for VFD driver

Mask

input port

option

Pin P1

: 1-bit standard input

EVENT

Timer D event input

PMR1

port

Pins P1

, P1

, and P1

/IRQ

External interrupt 5;

PMR1

4-bit standard I/O port

TMOE

Timer E output

PMR4

/IRQ

External interrupts 4, 1, and 0

PMR1

/IRQ

Port 4

8-bit high-voltage I/O port

to P4

VFD segment pins 23 to 16

VFSR

to FS

Port 5

8-bit high-voltage I/O port

to P5

VFD segment pins 15 to 8

VFSR

to FS

Port 6

8-bit high-voltage I/O port

to P6

VFD digit pins 7 to 0/segment

DBR

to FD

pins 0 to 7

VFSR

to FS

VFDR

Port 7

8-bit high-voltage I/O port

to P7

VFD digit pins 15 to 8

VFDR

to FD

Port 9

8-bit standard I/O port

/UD

Timer C count-up/down

PMR2

selection

PMR3

/SO

Serial communication interface
2 data output

/SI

Serial communication interface
2 data input/chip select output

/SCK

Serial communication interface
2 clock I/O

/SO

Serial communication interface
1 data output

/SI

Serial communication interface
1 data input

/SCK

Serial communication interface
1 clock I/O

/PWM

14-bit PWM waveform output pin

Note: Pins P1

and P1

, and ports P2, P3, and P8 are not included in these versions.

106

7.1.1 Port Types and Mask Options

The choice of I/O pin options and the resulting states are shown in table 7-2.

Upon reset, the PDR, PCR, and PMR registers are initialized, cancelling the choices of peripheral
functions. When the chip goes to a low-power mode, the on-chip peripheral function input gates
are always on, so unless input levels are fixed there will be an increase in dissipated current.

Table 7-2 Choice of I/O Port Options

For Standard I/O Pins

Class

Pins

With MOS Pull-Up (type B)

No MOS Pull-Up (type C)

I/O pins

, P1

With MOS pull-up

No MOS pull-up

, P1

to P9

Input-only pins

With MOS pull-up

No MOS pull-up

On-chip peripheral

SCK

, SCK

With MOS pull-up

No MOS pull-up

function I/O pins

(output mode)

On-chip peripheral

, SO

With MOS pull-up

No MOS pull-up

function output pins

PWM, TMOE

On-chip peripheral

SCK

, SCK

With MOS pull-up

No MOS pull-up

function input pins

(input mode)

, SI

IRQ

, IRQ

IRQ

, IRQ

UD,

EVENT

Note: If external clock input mode is selected when the serial communication interface is used,

pins SCK

and SCK

will be input-only pins.

For High-Voltage Pins

Class

Pins

No MOS Pull-Down (type D)

With MOS Pull-Down (type E)

I/O pins

to P4

No MOS pull-down

With MOS pull-down.

to P5

Source of pull-down transistor

to P6

connected to V

disp

power

to P7

supply.

Input-only pins

No MOS pull-down

Connected to V

disp

power

supply.

On-chip peripheral

to FS

, No MOS pull-down

With MOS pull-down.

function output pins FD

to FD

Source of pull-down transistor
connected to V

disp

power

supply.

107

Table 7-3 shows the mask options with mask ROM versions. A mask ROM version is compatible
with a ZTATTM version only when C and D options are selected for all pins.

Table 7-3 Correspondence between Mask ROM and ZTAT

Versions

Type

Mask ROM

Option

ZTAT

Fixed

Notes

1. When circuit type E, "with MOS pull-down," is chosen, the source of the MOS pull-down is

connected to the V

disp

power supply. Accordingly, the mask option making pin P1

disp

a V

disp

power supply pin must also be chosen.

2. Type C, "no MOS pull-up," is the only option available for port 0.

7.1.2 MOS Pull-Up

Ports 1* and 9, which are standard input/output ports, can be designated by mask options as
having or not having MOS pull-up transistors for their (CMOS) outputs. (This does not apply to
ZTATTM versions.)

Figure 7-1 shows the MOS pull-up circuit configuration.

When "with MOS pull-up" is selected by mask option, the MOS pull-up will normally be on,
regardless of the port data register (PDR) and port control register (PCR) settings.
(See table 7-4.)

Note: * Pin P1

disp

is a high-voltage pin, so the MOS pull-up option cannot be selected for

this pin.

108

Bit n
ANn

Explanation

Pin P0

/AN

is used for general input.

(initial value)

Pin P0

/AN

is an analog input channel.

(n = 0 to 7)

Port data register 0 (PDR0)

When the corresponding bit in PMR0 is 0, the pin state can be read from PDR0. If the
corresponding PMR0 bit is 1, PDR0 is read as 1.

7.2.3 Pin Functions

Table 7-6 gives the port 0 pin functions.

Table 7-6 Port 0 Pin Functions

Pin

Pin Functions and Selection Method

/AN

to P0

/AN

Functions are switched as follows by means of bits AN

to AN

in PMR0.

Pin function

input pin

7.2.4 Pin States

Table 7-7 shows the port 0 pin states in each operating mode.

Table 7-7 Port 0 Pin States

Pins

Reset

Sleep

Standby

Watch

Subactive

Active

/AN

High Previous

High High High Normal

/AN

impedance state

impedance

operation

retained

Bit

Initial value

Read/Write

PDR0

112

7.3 Port 1

7.3.1 Overview

Port 1 consists of four standard I/O pins, one standard input-only pin, and one high-voltage input-
only pin. Figure 7-4 shows the pin configuration.

Figure 7-4 Port 1 Pin Configuration

7.3.2 Register Configuration and Description

Table 7-8 shows the port 1 register configuration.

Table 7-8 Port 1 Registers

Name

Abbrev.

R/W

Initial Value

Address

Port mode register 1

PMR1

R/W

H'0C

H'FFEB

Port control register 1

PCR1

H'CC

H'FFE1

Port data register 1

PDR1

R/W

Not fixed

H'FFD1

Port mode register 4

PMR4

R/W

H'0F

H'FFEE

Port mode register 1 (PMR1)

P1 /V

P1 /EVENT

P1 /IRQ /TMOE

P1 /IRQ

disp

Port 1

(high-voltage input or power supply)

(input/input)

(IO/input/output)

(IO/input)

Note: IO indicates input/output.

Bit

Initial value

Read/Write

R/W

EVENT

R/W

IRQC5

R/W

IRQC4

R/W

IRQC0

R/W

IRQC1

R/W

NOISE

CANCEL

113

PMR1 is an 8-bit read/write register that controls the selection of pin functions for pins
P1

EVENT, P1

/IRQ

, P1

/IRQ

, P1

/IRQ

, and P1

/IRQ

, and turns the IRQ

noise

cancellation function on and off.

Upon reset, PMR1 is initialized to H'0C.

Note: Before switching pin functions using bits IRQ5 to IRQ0 in PMR1, first disable the

corresponding interrupts by clearing their interrupt enable bits. After the pin functions
have been switched, issue any instruction, then clear the interrupt request flags to 0. For
details see section 3.2.3 1, Port mode register (PMR1).

Bit 7: Noise cancel (NOISE CANCEL)

This bit turns the IRQ

noise canceller function on and off. In standby, watch, and subactive

modes the noise canceller function is off regardless of the setting of this bit.

Bit 7
NOISE CANCEL

Explanation

Noise canceller function is off.

(initial value)

Noise canceller function is on. Input is sampled at intervals of 256 states.
If two consecutive input values do not match, noise is assumed.

Bit 6: P1

EVENT pin function switch (EVENT)

This bit selects whether pin P1

EVENT is used as P1

or as

EVENT.

Bit 6
EVENT

Explanation

/EVENT pin functions as P1

(initial value)

/EVENT pin functions as EVENT (timer D event input).

Note:

Even when pin P1

/EVENT is used as P1

, the timer D counter may increment when pin

is read. If timer D is used the counter must be cleared by means of the CLR bit in

timer mode register D (TMD).

Bit 5: P1

/IRQ

/TMOE pin function switch (IRQC5)

This bit selects whether pin P1

/IRQ

/TMOE is used as P1

TMOE or as IRQ

Bit 5
IRQC5

Explanation

/IRQ

/TMOE pin functions as P1

/TMOE.

(initial value)

/IRQ

/TMOE pin functions for IRQ

input.

114

Bit 4: P1

/IRQ

pin function switch (IRQC4)

This bit selects whether pin P1

/IRQ

is used as P1

or as IRQ

Bit 4
IRQC4

Explanation

/IRQ

pin functions as P1

(initial value)

/IRQ

pin functions for IRQ

input.

Note:

Rising or falling edge sensing can be designated for pin IRQ

For details see 3.2.3 (2), IRQ edge select register (IEGR).

Bits 3 and 2: Reserved bits

Bits 3 and 2 are reserved; they always read 1, and cannot be modified.

Bit 1: P1

/IRQ

pin function switch (IRQC1)

This bit selects whether pin P1

/IRQ

is used as P1

or as IRQ

Bit 1
IRQC1

Explanation

/IRQ

pin functions as P1

(initial value)

/IRQ

pin functions for IRQ

input.

Note:

Rising or falling edge sensing can be designated for pin IRQ

For details see 3.2.3 (2), IRQ edge select register (IEGR).

Bit 0: P1

/IRQ

pin function switch (IRQC0)

This bit selects whether pin P1

/IRQ

is used as P1

or as IRQ

Bit 0
IRQC0

Explanation

/IRQ

pin functions as P1

(initial value)

/IRQ

pin functions for IRQ

input.

Note:

Rising or falling edge sensing can be designated for pin IRQ

For details see 3.2.3 (2), IRQ edge select register (IEGR).

115

Port control register 1 (PCR1)

PCR1 is an 8-bit register for controlling whether each of port 1 pins P1

, P1

, and P1

functions as an input pin or output pin. Setting a PCR1 bit to 1 makes the corresponding pin an
output pin, while clearing the bit to 0 makes the pin an input pin. Bits 7, 6, 3, and 2 are reserved
bits that cannot be modified and always read 1.

The settings in PCR1 and in PDR1 are valid when the affected pin is designated in PMR1 as a
general I/O pin.

Upon reset, PCR1 is initialized to H'CC.

Port data register 1 (PDR1)

Note:

Pins P1

and P1

are for input only; reading PDR1 always gives the level of these pins.

PDR1 is an 8-bit register that stores data for pins P1

, P1

, and P1

. If port 1 is read while

PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states. If
port 1 is read while PCR1 bits are cleared to 0, the pin states are read. Bits 3 and 2 are reserved
bits that cannot be modified and always read 1.

Bit

Initial value

Read/Write

PCR1

Bit

Initial value

Read/Write

PDR1

R/W

PDR1

R/W

PDR1

R/W

PDR1

R/W

116

Port mode register 4 (PMR4)

PMR4 is an 8-bit read/write register that switches the P1

/IRQ

/TMOE pin function and controls

TMOE pin waveform output. Bits 3 to 0 are reserved; they always read 1, and cannot be
modified.

Upon reset, PMR4 is initialized to H'0F.

Bit 7: Timer E output select (TEO)
Bit 6: Timer E output on/off (TEO ON)
Bit 5: Fixed frequency select (FREQ)
Bit 4: Variable frequency select (VRFR)

/IRQ

/TMOE pin functions are switched as follows, by means of bits 7 to 4 of PMR4 and bit

IRQC5 of PMR1.

PMR1

PMR4

Description

Bit 5

Bit 7

Bit 6

Bit 5

Bit 4

IRQC5 TEO

TEO ON FREQ

VRFR

Pin Function

Pin State

Standard I/O port (initial value)

Standard I/O port

TMOE output pin (off)

Low level output

TMOE output pin (on)

Fixed frequency output:
(

/2048)

1.95 kHz (

= 4 MHz)

0.98 kHz (

= 2 MHz)

TMOE output pin (on)

Fixed frequency output:
(

/1024)

3.9 kHz (

= 4 MHz)

1.95 kHz (

= 2 MHz)

TMOE output pin (on)

Variable frequency output:
toggled by timer E overflow

IRQ

input pin

External interrupt input

Note:

Don't care

Bit

Initial value

Read/Write

TEO

R/W

TEO ON

R/W

FREQ

R/W

VRFR

R/W

117

7.3.3 Pin Functions

Table 7-9 shows the port 1 pin functions.

Table 7-9 Port 1 Pin Functions

Pin

Pin Functions and Selection Method

disp

Selected by mask option

high-voltage input pin

Power supply for VFD driving (V

disp

)

EVENT

Function is switched as follows by EVENT bit in PMR1

EVENT

Pin function

input pin

EVENT

input pin

Note: Timer D event input

Function is switched as follows by bits IRQC5, IRQC4, IRQC1, and IRQC0

PMR1 and bit n in PCR1

PMR1

PCR1

Pin function

input pin P1

output pin

IRQ

input pin

Notes: 1. Before switching pin functions using bits IRQC5, IRQC4, IRQC1, and

IRQC0 in PMR1, first disable the corresponding interrupts by
clearing their interrupt enable bits. After the pin functions have been
switched, issue any instruction, then clear the interrupt request flags
to 0. For details see section 3.2.3 (1), Port mode register (PMR1).

2. Before entering power-down mode, pins set to external interrupt

input by bits IRQC5, IRQC4, IRQC1, and IRQC0 in PMR1, should be
kept from floating by external connection, or should be switched to
general I/O in PMR1 prior to the state transition.

3. For details on the TMOE function, refer to section 7.3.2 (4), Port

mode register 4 (PMR4). IRQ

, IRQ

, and IRQ

input can be set for

either rising edge or falling edge detection by register IEGR. For
details, refer to section 3.2.3 (2), IRQ edge select register (IEGR).
IRQ

and IRQ

can be used as event input pins for timer B and

timer C, respectively. For details, refer to section 8, Timers.

/IRQ

/TMOE,

/IRQ

118

7.4.3 Pin Functions

Table 7-12 shows the port 4 pin functions.

Table 7-12 Port 4 Pin Functions

Pin

Pin Functions and Selection Method

/FS

After designation of the segment pins to be used in bits SR4 to SR0 of the VFD

/FS

segment control register (VFSR), bit VFDE in the digit beginning register (DBR)
is set to 1 and VFD controller/driver operation is started. During key scan
intervals, pins designated for segment output can be used by the CPU as
general-purpose ports. Even while the VFD controller/driver is operating, it is
possible to switch segment pins to general-purpose ports by writing 0 in the
VFLAG bit of VFSR.

VFLAG

Pin function

Pins P4

to P4

are all

Pins designated by bits

general-purpose I/O pins.

SR4 to SR0 are segment
output pins.

Other pins

are for general I/O.

Note:

When a pin functioning as a segment output pin is read, the value of
the corresponding bit in PDR4 is read.

7.4.4 Pin States

Table 7-13 shows the port 4 pin states in each operating mode.

Table 7-13 Port 4 Pin States

Pins

Reset

Sleep

Standby

Watch

Subactive

Active

/FS

High Previous

High High High Normal

/FS

impedance or state

impedance or impedance or impedance or operation

pulled down retained

pulled down

121

7.5.3 Pin Functions

Table 7-15 shows the port 5 pin functions.

Table 7-15 Port 5 Pin Functions

Pin

Pin Functions and Selection Method

/FS

After designation of the segment pins to be used in bits SR4 to SR0 of the VFD

/FS

VFLAG

Pin function

Pins P5

to P5

are all

Pins designated by bits

general-purpose I/O pins.

SR4 to SR0 are segment
output pins.

Other pins

are for general I/O.

Note:

When a pin functioning as a segment output pin is read, the value of
the corresponding bit in PDR5 is read.

7.5.4 Pin States

Table 7-16 shows the port 5 pin states in each operating mode.

Table 7-16 Port 5 Pin States

Pins

Reset

Sleep

Standby

Watch

Subactive

Active

/FS

High Previous

High High High Normal

/FS

impedance or state

impedance or impedance or impedance or operation

pulled down retained

pulled down

123

7.6 Port 6

7.6.1 Overview

Port 6 is an 8-bit high-voltage I/O port. Figure 7-7 shows the pin configuration.

Figure 7-7 Port 6 Pin Configuration

7.6.2 Register Configuration and Description

Table 7-17 shows the port 6 register configuration.

Table 7-17 Port 6 Registers

Name

Abbrev.

R/W

Initial Value

Address

Port data register 6

PDR6

R/W

H'00

H'FFD6

Port data register 6 (PDR6)

PDR6 is an 8-bit register for storing the data of port 6 pins P6

to P6

Upon reset, PDR6 is initialized to H'00.

P6 /FD /FS

Port 6

(IO/output/output)

Note: IO indicates input/output.

Bit

Initial value

Read/Write

PDR6

R/W

PDR6

R/W

PDR6

R/W

PDR6

R/W

PDR6

R/W

PDR6

R/W

PDR6

R/W

PDR6

R/W

124

7.6.3 Pin Functions

Table 7-18 shows the port 6 pin functions.

Table 7-18 Port 6 Pin Functions

Pin

Pin Functions and Selection Method

/FD

/FS

After designation of the digit pins and segment pins to be used in bits DR3 to

/FD

/FS

DR0 of the VFD digit control register (VFDR), bits SR4 to SR0 of the VFD
segment control register (VFSR), and bits DBR3 to DBR0 of the digit beginning
register (DBR), bit VFDE in DBR is set to 1 and VFD controller/driver operation
is started. During key scan intervals, pins designated for digit or segment
output can be used by the CPU as general-purpose ports. Even while the VFD
controller/driver is operating, it is possible to switch digit pins or segment pins
to general-purpose ports by writing 0 in the VFLAG bit of VFSR.

VFLAG

Pin function

Pins P6

to P6

are all

Pins are designated as digit

general-purpose I/O pins.

output pins,

segment

output pins,

or general

I/O pins by bits DR3 to DR0,
SR4 to SR0, and DBR3 to
DBR0.

Note:

When a pin functioning as a digit output pin or segment output pin is
read, the value of the corresponding bit in PDR6 is read.

7.6.4 Pin States

Table 7-19 shows the port 6 pin states in each operating mode.

Table 7-19 Port 6 Pin States

Pins

Reset

Sleep

Standby

Watch

Subactive

Active

/FD

High Previous

High High High Normal

impedance or state

impedance or impedance or impedance or operation

/FD

pulled down retained

pulled down

125

7.7.3 Pin Functions

Table 7-21 shows the port 7 pin functions.

Table 7-21 Port 7 Pin Functions

Pin

Pin Functions and Selection Method

/FD

After designation of the digit pins to be used, in bits DR3 to DR0 of the VFD

/FD

digit control register (VFDR), bit VFDE in the digit beginning register (DBR) is
set to 1 and VFD controller/driver operation is started. Even while the VFD
controller/driver is operating, it is possible to switch digit pins to general-
purpose ports by writing 0 in the VFLAG bit of VFSR.

VFLAG

Pin function

Pins P7

to P7

are all

Pins designated by bits

general-purpose I/O pins.

DR3 to DR0 are digit output
pins.

Other pins are for

general I/O.

Note:

When a pin functioning as a digit output pin is read, the value of the
corresponding bit in PDR7 is read.

7.7.4 Pin States

Table 7-22 shows the port 7 pin states in each operating mode.

Table 7-22 Port 7 Pin States

Pins

Reset

Sleep

Standby

Watch

Subactive

Active

/FD

High Previous

High High High Normal

/FD

impedance or state

impedance or impedance or impedance or operation

pulled down retained

pulled down

127

7.8 Port 9

7.8.1 Overview

Port 9 is an 8-bit standard I/O port. Figure 7-9 shows the pin configuration.

Figure 7-9 Port 9 Pin Configuration

7.8.2 Register Configuration and Description

Table 7-23 shows the port 9 register configuration.

Table 7-23 Port 9 Registers

Name

Abbrev.

R/W

Initial Value

Address

Port mode register 2

PMR2

R/W

H'00

H'FFEC

Port control register 9

PCR9

H'00

H'FFE9

Port data register 9

PDR9

R/W

H'00

H'FFD9

Port mode register 2 (PMR2)

PMR2 is an 8-bit read/write register, controlling the selection of port 9 pin functions.

Upon reset, PMR2 is initialized to H'00.

P9 /UD

P9 /SO

P9 /SI /CS

P9 /SCK

P9 /SO

P9 /SI

P9 /SCK

P9 /PWM

Port 9

(IO/input)

(IO/output)

(IO/input/output)

(IO/IO)

(IO/output)

(IO/input)

(IO/IO)

(IO/output)

Note: IO indicates input/output.

Bit

Initial value

Read/Write

R/W

SO2

R/W

SI2

R/W

SCK2

R/W

SO1

R/W

PWM

R/W

SI1

R/W

SCK1

R/W

UP/

DOWN

128

Bit 7: P9

/UD pin function switch (UP/DOWN)

This bit selects whether pin P9

/UD is used for general-purpose I/O or for timer C up/down

control input. Up/down control input (UD) is valid only when bit TMC6 = 1 in timer mode
register C (TMC).

Bit 7
UP/DOWN

Description

/UD pin functions for P9

input/output.

(initial value)

/UD pin functions for UD input. If bit TMC6 in TMC is set to 1, then when the UD

input is high, timer C counts down, and when UD is low, timer C counts up.

Bit 6: P9

/SO

pin function switch (SO2)

This bit selects whether pin P9

/SO

functions as the P9

I/O pin or the SO

output pin.

Bit 6
SO2

Description

/SO

pin functions for P9

input/output.

(initial value)

/SO

pin functions for SO

output.

Bit 5: P9

/SI

CS pin function switch (SI2)

This bit selects whether pin P9

/SI

CS functions as the P9

I/O pin or the SI

input/

CS output

pin. For the switching between SI

input and

CS output see 11.2.5, Port Mode Register 3

(PMR3).

Bit 5
SI2

Description

/SI

/CS pin functions for P9

input/output.

(initial value)

/SI

/CS pin functions for SI

input or

output.

Bit 4: P9

/SCK

pin function switch (SCK2)

This bit selects whether pin P9

/SCK

functions as the P9

I/O pin or the SCK

I/O pin.

Bit 4
SCK2

Description

/SCK

pin functions for P9

input/output.

(initial value)

/SCK

pin functions for SCK

input/output. The clock input/output direction and

the divider ratio are set in serial mode register 2 (SMR2).

129

Bit 3: P9

/SO

pin function switch (SO1)

This bit selects whether pin P9

/SO

functions as the P9

I/O pin or the SO

output pin.

Bit 3
SO1

Description

/SO

pin functions for P9

input/output.

(initial value)

/SO

pin functions for SO

output.

Bit 2: P9

/SI

pin function switch (SI1)

This bit selects whether pin P9

/SI

functions as the P9

I/O pin or the SI

input pin.

Bit 2
SI1

Description

/SI

pin functions for P9

input/output.

(initial value)

/SI

pin functions for SI

input.

Bit 1: P9

/SCK

pin function switch (SCK1)

This bit selects whether pin P9

/SCK

functions as the P9

I/O pin or the SCK

I/O pin.

Bit 1
SCK1

Description

/SCK

pin functions for P9

input/output.

(initial value)

/SCK

pin functions for SCK

input/output. The clock input/output direction and

the divider ratio are set in serial mode register 1 (SMR1).

Bit 0: P9

/PWM pin function switch (PWM)

This bit selects whether pin P9

/PWM pin functions as the P9

I/O pin or the PWM output pin.

Bit 0
PWM

Description

/PWM pin functions for P9

input/output.

(initial value)

/PWM pin functions for PWM output.

130

Port control register 9 (PCR9)

PCR9 is an 8-bit register for controlling whether each of port 9 pins P9

to P9

functions as an

input or output pin. Setting a PCR9 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCR9 and PDR9 are valid when
the affected pin is designated in PMR2 as a general-purpose I/O pin. PCR9 is a write-only
register, which always reads as all 1.

Upon reset, PCR9 is initialized to H'00.

Port data register 9 (PDR9)

PDR9 is an 8-bit register that stores data for port 9 pins P9

to P9

. If port 9 is read while PCR9

bits are set to 1, the values stored in PDR9 are read, regardless of the actual pin states. If port 9 is
read while PCR9 bits are cleared to 0, the pin states are read.

Upon reset, PDR9 is initialized to H'00.

Bit

Initial value

Read/Write

PCR9

Bit

Initial value

Read/Write

PDR9

R/W

PDR9

R/W

PDR9

R/W

PDR9

R/W

PDR9

R/W

PDR9

R/W

PDR9

R/W

PDR9

R/W

131

7.8.3 Pin Functions

Table 7-24 shows the port 9 pin functions.

Table 7-24 Port 9 Pin Functions

Pin

Pin Functions and Selection Method

/UD

Functions are switched as follows by means of the UP/DOWN bit

in PMR2

and bit PCR9

in PCR9.

UP/DOWN

PCR9

Pin function

input pin P9

output pin

UD input pin

Note:

Before entering power-down mode, if this pin is set to UD input by the
UP/DOWN bit in PMR2, it should be kept from floating by external
connection or should be set to general I/O use by clearing the
UP/DOWN bit to 0 prior to the state transition.

/SO

Functions are switched as follows by means of bit SO2 in PMR2 and bit PCR9

in PCR9.

SO2

PCR9

Pin function

input pin P9

output pin

Note:

The PMOS buffer transistor of pin P9

/SO

can be enabled or

disabled by the SO2PMOS bit in PMR3. For details see 11.2.5, Port
Mode Register 3 (PMR3).

/SI

Functions are switched as follows by means of bit SI2 in PMR2,

bit CS in

PMR3, and bit PCR9

in PCR9.

SI2

PCR9

Pin function

input pin P9

output pin SI

input pin

output pin

Note:

Before entering power-down mode, if this pin is set to SI

input by bit

SI2 in PMR2, it should be kept from floating by external connection or
should be set to general I/O use by clearing bit SI2 to 0 prior to the
state transition.

132

Table 7-24 Port 9 Pin Functions (cont)

Pin

Pin Functions and Selection Method

/SCK

Functions are switched as follows by means of bit SCK2

in PMR2, bits PS1

and PS0

in serial control register 2 (SCR2), and bit PCR9

in PCR9.

SCK2

PS1, 0

Not 11

PCR9

Pin function

input pin P9

output pin SCK

input pin

Note:

Before entering power-down mode, if this pin is set to SCK

input by

bit SCK2 in PMR2 and bits PS1 and PS0 in SCR2, it should be kept
from floating by external connection, or else should be set to some
other use by changing bits SCK2 and bits PS1 and PS0 prior to the
state transition.

For the settings of bits PS1 and PS0 in SCR2, see 11.2.3, Serial Control
Register 2 (SCR2).

/SO

Functions are switched as follows by means of bit SO1 in PMR2 and bit PCR9

in PCR9.

SO1

PCR9

Pin function

input pin P9

output pin

Note:

The PMOS buffer transistor of pin P9

/SO

can be enabled or

disabled by the SO1PMOS bit in PMR3. For details see 10.2.6, Port
Mode Register 3 (PMR3).

/SI

Functions are switched as follows by means of bit SI1

in PMR2 and bit PCR9

in PCR9.

SI1

PCR9

Pin function

input pin P9

output pin

input pin

Note:

Before entering power-down mode, if this pin is set to SI

input by bit

SI1 in PMR2, it should be kept from floating by external connection or
should be set to general I/O use by clearing bit SI1 to 0 prior to the
state transition.

133

Table 7-24 Port 9 Pin Functions (cont)

Pin

Pin Functions and Selection Method

/SCK

Functions are switched as follows by means of bit SCK1 in PMR2,

bits

SMR13 to SMR10 in serial mode register 1 (SMR1)

, and bit PCR9

in PCR9.

SCK1

SMR13 to 10

Not 1111

1111

PCR9

Pin function

input pin P9

output pin SCK

input pin

Note:

Before entering power-down mode, if this pin is set to SCK

input by

bit SCK1 in PMR2 and bits SMR13 to SMR10 in SMR1, it should be
kept from floating by external connection, or else should be set to
some other use by changing the SCK1 bit or bits SMR13 to SMR10
prior to the state transition.

For the settings of bits SMR13 to SMR10 in SMR1, see 10.2.1, Serial Mode
Register 1 (SMR1).

/PWM

Functions are switched as follows by means of bit PWM in PMR2 and bit
PCR9

in PCR9.

PWM

PCR9

Pin function

input pin P9

output pin

PWM output pin

7.8.4 Pin States

Table 7-25 shows the port 9 pin states in each operating mode.

Table 7-25 Port 9 Pin States

Pins

Reset

Sleep

Standby

Watch

Subactive

Active

/UD,

High Previous

High High High Normal

/SO

impedance

state

impedance impedance impedance operation

/SI

/CS,

pulled up

retained

/SCK

/SO

/SI

/SCK

/PWM

134

Section 8 Timers

8.1 Overview

The H8/3714 Series provides on-chip two prescalers (prescaler S and prescaler W) with different
input clocks, and five timers (timers A through E).

Prescaler S is a 13-bit counter clocked by the system clock (

= f

OSC

/2). Its prescaled outputs are

used by timers A to C and timer E.

Prescaler W is a 5-bit counter clocked by the subclock (

SUB

= f

/8). Its prescaled output is used

for time-base operation by timer A.

Table 8-1 outlines the functions of timers A through E.

Table 8-1 Timer A to E Functions

Operating Clock

Event

Waveform

Name

Functions

(internal)

Input Pin

Output Pin

Remarks

Timer A

� 8-bit interval timer

/8 to

/8192 --

(choice of 8 sources)

� Time base

SUB

/32 --

(choice of 4 overflow
periods)

Timer B

� 8-bit reloadable timer

/IRQ

� Interval timer

� Event counter

Timer C � 8-bit reloadable timer

/IRQ

� Interval timer

� Event counter

� Choice of up- or

down-counting

Timer D � 8-bit event counter

EVENT

Timer E

� 8-bit reloadable timer

� Interval timer

Can output
square wave
with 50%
duty cycle

Counting
direction
can be
controlled by
software or
hardware.

/8 to

/8192

(choice of 7 sources)

/8 to

/8192

(choice of 8 sources)

/IRQ

TMOE

/8 to

/8192

(choice of 7 sources)

135

8.1.1 Prescaler Operation

Prescaler S (PSS)

Prescaler S is a 13-bit counter using the system clock (

= f

OSC

/2) as its input clock. Each

input clock cycle causes prescaler S to increment once.

Prescaler S is initialized to H'0000 by a reset, and starts counting upon return to active mode.

In standby mode, watch mode, and subactive mode, the system clock (

) pulse generator

stops, so prescaler S also stops functioning. Its value is reset to H'0000.

The CPU cannot read or write prescaler S data.

The output from prescaler S is shared by timers A to C and E as well as serial communication
interfaces 1 and 2. The frequency division ratio can be set separately for each on-chip
peripheral function.

Prescaler W (PSW)

Prescaler W is a 5-bit counter using the subclock (

SUB

= f

/8) as its input clock.

Prescaler W is initialized to H'00 by a reset, and starts counting upon return to active mode.

Even in standby mode, watch mode, or subactive mode, prescaler W continues functioning so
long as clock signals are supplied to pins X

and X

Prescaler W can be reset by setting bits TMA3 and TMA2 to 1 in timer mode register A
(TMA).

The output from prescaler W can be used as the clock source for timer A, in which case timer
A functions as a time base.

Figure 8-1 shows the clock signals supplied by prescalers S and W to peripheral modules.

136

8.2 Timer A

8.2.1 Overview

Timer A is an 8-bit interval timer. It can be connected to a 32.768 kHz crystal oscillator for use as
a real-time clock time base.

Features

Features of timer A are given below.

�

Choice of eight internal clock sources (

/8192,

/4096,

/2048,

/512,

/256,

/128,

/32,

/8).

�

Choice of four overflow periods (2 s, 1 s, 0.5 s, 125 ms) when timer A is used as a time
base (using a 32.768 kHz crystal oscillator).

�

An interrupt is requested when the counter overflows.

Block diagram

Figure 8-2 shows a block diagram of timer A.

Figure 8-2 Block Diagram of Timer A

1/8

Prescaler W

(PSW)

Prescaler S

(PSS)

TMA

TCA

Internal data bus

SUB

/32

SUB

/8192, /4096, /2048
/512, /256, /128,
/32, /8

�

128

�

256

IRRTA

32 kHz
crystal
oscillator

Notation:
TMA:
TCA:
IRRTA:

Timer mode register A
Timer counter A
Timer A overflow interrupt request flag (interrupt request register 2)

Can be selected only when the input clock to
TCA is the output from prescaler W ( /32).

SUB

Note:

Interval
timer
overflow

1/2

System
clock

138

Timer counter A (TCA)

TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock
source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A
(TMA). The TCA value can be read by the CPU at any time.

TCA is cleared by setting bits TMA3 and TMA2 of TMA to 1.

When TCA overflows, the IRRTA bit in interrupt request register 2 (IRR2) is set to 1.

Upon reset, TCA is initialized to H'00.

8.2.3 Timer Operation

Timer A is an 8-bit timer which can be used either as an interval timer or, if a 32.768 kHz crystal
oscillator is connected, as a real-time clock time base.

Interval timer operation

When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit
interval timer.

Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval
timing resume immediately after the reset. The clock input to timer A is selected by bits
TMA2 to TMA0 in TMA; any of eight internal clock signals output by prescaler S can be
selected.

After the count value in TCA reaches H'FF, the next clock signal input causes timer A to
overflow, setting bit IRRTA to 1 in interrupt request register 2 (IRR2). If IENTA = 1 in
interrupt enable register 2 (IENR2), a CPU interrupt is requested.*

At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A
functions as an interval timer that generates an overflow output at intervals of 256 input clock
pulses.

Note: * For details on interrupts, see 3.2.2, Interrupts.

Bit

Initial value

Read/Write

TCA7

TCA6

TCA5

TCA4

TCA3

TCA0

TCA2

TCA1

141

Pin configuration

Table 8-3 shows the timer B pin configuration.

Table 8-3 Pin Configuration

Name

Abbrev.

I/O

Function

Event input pin

/IRQ

Input

Timer B event input

Table 8-4 shows the register configuration of timer B.

Table 8-4 Timer B Registers

Name

Abbrev.

R/W

Initial Value

Address

Timer mode register B

TMB

R/W

H'78

H'FFC2

Timer counter B

TCB

H'00

H'FFC3

Timer load register B

TLB

H'00

H'FFC3

8.3.2 Register Descriptions

Timer mode register B (TMB)

TMB is an 8-bit read/write register for selecting the auto-reload function and input clock.

Upon reset, TMB is initialized to H'78.

Bit 7: Auto-reload function select (TMB7)

Bit 7 selects the auto-reload function of timer B.

Bit 7
TMB7

Description

Interval timer function selected.

(initial value)

Auto-reload function selected.

Bit

Initial value

Read/Write

TMB7

R/W

TMB0

R/W

TMB2

R/W

TMB1

R/W

144

Bits 6 to 3: Reserved bits

Bits 6 to 3 are reserved; they always read 1, and cannot be modified.

Bits 2 to 0: Clock select (TMB2 to TMB0)

Bits 2 to 0 select the clock input to TCB. For external clock counting, either the rising or falling
edge can be selected.

Bit 2

Bit 1

Bit 0

TMB2

TMB1

TMB0

Description

Internal clock:

/8192.

(initial value)

Internal clock:

/2048.

Internal clock:

/512.

Internal clock:

/256.

Internal clock:

/128.

Internal clock:

/32.

Internal clock:

/8.

External clock (P1

/IRQ

): rising or falling edge.

Note:

The edge of the external event signal is selected by bit IEG0 in the IRQ edge select
register (IEGR). For details see 3.2.3 (2), IRQ edge select register (IEGR).

Timer counter B (TCB)

TCB is an 8-bit read-only up-counter, which is incremented by internal or external clock input.
The clock source for input to this counter is selected by bits TMB2 to TMB0 in timer mode
register B (TMB). The TCB value can be read by the CPU at any time.

When TCB overflows from H'FF to H'00 or to the value set in TLB, the IRRTB bit in interrupt
request register 2 (IRR2) is set to 1.

TCB is allocated to the same address as timer load register B (TLB).

Upon reset, TCB is initialized to H'00.

Bit

Initial value

Read/Write

TCB7

TCB6

TCB5

TCB4

TCB3

TCB0

TCB2

TCB1

145

Timer load register B (TLB)

TLB is an 8-bit write-only register for setting the reload value of timer counter B (TCB).

When a reload value is set in TLB, the same value is loaded into timer counter B (TCB) as well,
and TCB starts counting up from that value. When TCB overflows during operation in auto-
reload mode, the TLB value is loaded in TCB. Accordingly, overflow periods can be set within
the range of 1 to 256 input clocks.

The same address is allocated to TLB as to TCB.

Upon reset, TLB is initialized to H'00.

8.3.3 Timer Operation

Timer B is an 8-bit multifunction timer. It can be used as an interval timer, an auto-reload timer,
or an event counter. (Event counting requires an input pin setting.)

Timer B operation modes

Timer B is an 8-bit up-counter which is incremented each time a clock pulse is input. The
two operation modes, interval and auto-reload, are explained below.

�

Interval timer operation

When bit TMB7 in timer mode register B (TMB) is cleared to 0, timer B functions as an 8-bit
interval timer.

Upon reset, TCB is cleared to H'00 and bit TMB7 is cleared to 0, so up-counting and interval
timing resume immediately after the reset. The clock input to timer B is selected from seven
internal clock signals output by prescaler S, or an external clock input at pin P1

/IRQ

. The

selection is made by bits TMB2 to TMB0 of TMB.

After the count value in TCB reaches H'FF, the next clock signal input causes timer B to
overflow, setting bit IRRTB to 1 in interrupt request register 2 (IRR2). If IENTB = 1 in
interrupt enable register 2 (IENR2), a CPU interrupt is requested.*

At overflow, TCB returns to H'00 and starts counting up again.

During interval timer operation (TMB7 = 0), when a value is set in timer load register B
(TLB), the same value is set in TCB.

Note: * For details on interrupts, see 3.2.2, Interrupts.

Bit

Initial value

Read/Write

TLB7

TLB6

TLB5

TLB4

TLB3

TLB0

TLB2

TLB1

146

�

Auto-reload timer operation

Setting bit TMB7 in TMB to 1 causes timer B to function as an 8-bit auto-reload timer.
When a reload value is set in TLB, the same value is loaded into TCB, becoming the value
from which TCB starts its count.

After the count value in TCB reaches H'FF, the next clock signal input causes timer B to
overflow. The TLB value is then loaded into TCB, and the count continues from that value.
The overflow period can be set within a range from 1 to 256 input clocks, depending on the
TLB value.

The clock sources and interrupts in auto-reload mode are the same as for interval mode.

In auto-reload mode (bit TMB7 = 1), setting a new TLB value also initializes TCB.

Operation on external clock

Timer B can operate on an external clock input as an event signal at pin P1

/IRQ

. External

clock operation is selected by setting bits TMB2 to TMB0 in timer mode register B to all 1's
(111). TCB can count either rising or falling edges of the input at pin P1

/IRQ

When timer B is used to count external event input, bit IRQC0 in port mode register 1
(PMR1) should be set to 1, and bit IEN0 in interrupt enable register 1 (IENR1) should be
cleared to 0 to disable IRQ

interrupt requests.

147

Bit 7: Auto-reload function select (TMC7)

Bit 7 selects the auto-reload function of timer C.

Bit 7
TMC7

Description

Interval timer function selected.

(initial value)

Auto-reload function selected.

Bit 6: Counter up/down control 1 (TMC6)

This bit selects whether the counting direction of timer counter C (TCC) is controlled by hardware
using pin P9

/UD, or by software using bit TMC5.

Bit 5: Counter up/down control 2 (TMC5)

This bit selects whether TCC is an up-counter or down-counter. The setting of this bit is valid
when bit TMC6 = 0.

Bits TMC6 and TMC5 operate as follows.

Bit 6

Bit 5

TMC6

TMC5

Description

TCC is an up-counter.

(initial value)

TCC is a down-counter.

TCC up/down control is by input at pin P9

/UD. TCC is a down-counter if

UD input is high, and an up-counter if UD input is low.

Note:

Don't care.

Bits 4 and 3: Reserved bits

Bits 4 and 3 are reserved; they always read 1, and cannot be modified.

Bits 2 to 0: Clock select (TMC2 to TMC0)

150

Bits 2 to 0 select the clock input to TCC. For external clock counting, either the rising or falling
edge can be selected.

Bit 2

Bit 1

Bit 0

TMC2

TMC1

TMC0

Description

Internal clock:

/8192.

(initial value)

Internal clock:

/2048.

Internal clock:

/512.

Internal clock:

/256.

Internal clock:

/128.

Internal clock:

/32.

Internal clock:

/8.

External clock (P1

/IRQ

): rising or falling edge.

Note:

The edge of the external clock is selected by bit IEG1 in the IRQ edge select register
(IEGR). For details see 3.2.3 2, IRQ edge select register (IEGR).

Timer counter C (TCC)

TCC is an 8-bit read-only up-/down-counter, which is incremented or decremented by internal or
external clock input. The clock source for input to this counter is selected by bits TMC2 to TMC0
in timer mode register C (TMC). The TCC value can be read by the CPU at any time.

When TCC overflows (from H'FF to H'00 or to the value set in TLC) or underflows (from H'00 to
H'FF or to the value set in TLC), the IRRTC bit in interrupt request register 2 (IRR2) is set to 1.

TCC is allocated to the same address as timer load register C (TLC).

Upon reset, TCC is initialized to H'00.

Bit

Initial value

Read/Write

TCC7

TCC6

TCC5

TCC4

TCC3

TCC0

TCC2

TCC1

151

Timer load register C (TLC)

TLC is an 8-bit write-only register for setting the reload value of TCC. When a reload value is set
in TLC, the same value is loaded into timer counter C (TCC) as well, and TCC starts counting up
or down from that value. When TCC overflows or underflows during operation in auto-reload
mode, the TLC value is loaded in TCC. Accordingly, overflow and underflow periods can be set
within the range of 1 to 256 input clocks.

The same address is allocated to TLC as to TCC.

Upon reset, TLC is initialized to H'00.

8.4.3 Timer Operation

Timer C is an 8-bit multifunction timer. It can be used as an interval timer, an auto-reload timer,
or an event counter. (Event counting requires an input pin setting.)

Timer C operation modes

Timer C is an 8-bit up-/down-counter which is incremented or decremented each time a clock
pulse is input. The two operation modes, interval and auto-reload, are explained below.

�

Interval timer operation

When bit TMC7 in timer mode register C (TMC) is cleared to 0, timer C functions as an
8-bit interval timer.

Upon reset, timer counter C (TCC) is initialized to H'00 and TMC to H'18, so up-counting
and interval timing resume immediately after the reset. The clock input to timer C is selected
from seven internal clock signals output by prescaler S, or an external clock input at pin
P1

/IRQ

. The selection is made by bits TMC2 to TMC0 in TMC.

Either software or hardware can control whether TCC counts up or down. The selection is
made by TMC bits TMC6 and TMC5.

Bit

Initial value

Read/Write

TLC7

TLC6

TLC5

TLC4

TLC3

TLC0

TLC2

TLC1

152

After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C
to overflow (underflow), setting bit IRRTC to 1 in interrupt request register 2 (IRR2). If bit
IENTC = 1 in interrupt enable register 2 (IENR2), a CPU interrupt is requested.*

At overflow or underflow, TCC returns to H'00 or H'FF and starts counting up or down again.

During interval timer operation (TMC7 = 0), when a value is set in timer load register C
(TLC), the same value is set in TCC.

Note: * For details on interrupts, see 3.2.2, Interrupts.

�

Auto-reload timer operation

Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When
a reload value is set in TLC, the same value is loaded into TCC, becoming the value from
which TCC starts its count.

After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C
to overflow (or underflow). The TLC value is then loaded into TCC, and the count continues
from that value. The overflow (underflow) period can be set within a range from 1 to 256
input clocks, depending on the TLC value.

The clock sources, up/down control, and interrupts in auto-reload mode are the same as for
interval mode.

In auto-reload mode (bit TMC7 = 1), setting a new TLC value also initializes TCC.

Operation on external clock

Timer C can operate on an external clock input as an event signal at pin P1

/IRQ

. External

clock operation is selected by setting bits TMC2 to TMC0 in timer mode register C to all 1's
(111). TCC can count either rising or falling edges of the input at pin P1

/IRQ

When timer C is used to count external event input, bit IRQC1 in port mode register 1
(PMR1) should be set to 1, and bit IEN1 in interrupt enable register 1 (IENR1) should be
cleared to 0 to disable IRQ

interrupt requests.

TCC up/down control by hardware

The counting direction of timer C can be controlled by input at pin P9

/UD. When bit TMC6

in TMC is set to 1, high-level input at the UD pin selects down-counting, while low-level
input selects up-counting.

When using input at pin UD for this control function, set the UP/DOWN bit in port mode
register 2 (PMR2) to 1.

153

Pin configuration

Table 8-7 shows the timer D pin configuration.

Table 8-7 Pin Configuration

Name

Abbrev.

I/O

Function

Event input pin

EVENT

Input

Timer D event input

Table 8-8 shows the register configuration of timer D.

Table 8-8 Timer D Registers

Name

Abbrev.

R/W

Initial Value

Address

Timer mode register D

TMD

R/W

H'7E

H'FFC6

Timer counter D

TCD

H'00

H'FFC7

Note:

Writing to bit 7 of TMD is possible only when writing 1 to clear the counter.

8.5.2 Register Descriptions

Timer mode register D (TMD)

TMD is an 8-bit read/write register for clearing timer counter D (TCD), and for selecting whether
input at the external event pin is sensed at the rising or falling edge.

Bit 7: Counter clear (CLR)

Bit 7 initializes TCD to H'00.

Bit 7
CLR

Description

After 1 is written to this bit to initialize TCD, it is cleared to 0 by

(initial value)

hardware.

Initializes TCD to H'00.

Bit

Initial value

Read/Write

CLR

EDG

R/W

155

Table 8-10 shows the register configuration of timer E.

Table 8-10 Timer E Registers

Name

Abbrev.

R/W

Initial Value

Address

Timer mode register E

TME

R/W

H'78

H'FFC8

Timer counter E

TCE

H'00

H'FFC9

Timer load register E

TLE

H'00

H'FFC9

Port mode register 4

PMR4

R/W

H'0F

H'FFEE

8.6.2 Register Descriptions

Timer mode register E (TME)

TME is an 8-bit read/write register for selecting the auto-reload function and input clock.

Upon reset, TME is initialized to H'78.

Bit 7: Auto-reload function select (TME7)

Bit 7 selects the auto-reload function of timer E.

Bit 7
TME7

Description

Interval timer function selected.

(initial value)

Auto-reload function selected.

Bits 6 to 3: Reserved bits

Bits 6 to 3 are reserved; they always read 1, and cannot be modified.

Bit

Initial value

Read/Write

TME7

R/W

TME0

R/W

TME2

R/W

TME1

R/W

160

Bits 2 to 0: Clock select (TME2 to TME0)

Bits 2 to 0 select the clock input to TCE.

Bit 2

Bit 1

Bit 0

TME2

TME1

TME0

Description

Internal clock:

/8192.

(initial value)

Internal clock:

/4096.

Internal clock:

/2048.

Internal clock:

/512.

Internal clock:

/256.

Internal clock:

/128.

Internal clock:

/32.

Internal clock:

/8.

Timer counter E (TCE)

TCE is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock
source for input to this counter is selected by bits TME2 to TME0 in timer mode register E
(TME). The TCE value can be read by the CPU at any time.

When TCE overflows from H'FF to H'00 or to the value set in TLE, the IRRTE bit in interrupt
request register 2 (IRR2) is set to 1.

TCE is allocated to the same address as timer load register E (TLE).

Upon reset, TCE is initialized to H'00.

Bit

Initial value

Read/Write

TCE7

TCE6

TCE5

TCE4

TCE3

TCE0

TCE2

TCE1

161

Timer load register E (TLE)

TLE is an 8-bit write-only register for setting the reload value of TCE.

When a reload value is set in TLE, the same value is loaded into timer counter E (TCE) as well,
and TCE starts counting up from that value. When TCE overflows during operation in auto-reload
mode, the TLE value is loaded in TCE. Accordingly, the overflow period can be set within the
range of 1 to 256 input clocks.

The same address is allocated to TLE as to TCE.

Upon reset, TLE is initialized to H'00.

Port mode register 4 (PMR4)

PMR4 is an 8-bit read/write register, for switching functions of pin P1

/IRQ

/TMOE and for

controlling waveform output from pin TMOE.

Upon reset, PMR4 is initialized to H'0F.

Bit

Initial value

Read/Write

TLE7

TLE6

TLE5

TLE4

TLE3

TLE0

TLE2

TLE1

Bit

Initial value

Read/Write

TEO

R/W

TEO ON

R/W

FREQ

R/W

VRFR

R/W

162

Bit 7: Timer E output select (TEO)

Bit 6: Timer E output on/off (TEO ON)

Bit 5: Fixed frequency select (FREQ)

Bit 4: Variable frequency select (VRFR)

/IRQ

/TMOE pin functions are switched as follows, by means of bits 7 to 4 of PMR4 and bit

IRQC5 of port mode register 1 (PMR1).

PMR1

PMR4

Description

Bit 5

Bit 7

Bit 6

Bit 5

Bit 4

IRQC5

TEO

TEO ON FREQ

VRFR

Pin Function

Pin State

Standard I/O port (initial value)

Standard I/O port

TMOE output pin Low-level output
(off)

TMOE output pin Fixed-frequency output:
(on)

(

/2048)

1.95 kHz (

= 4 MHz)

0.98 kHz (

= 2 MHz)

TMOE output pin Fixed-frequency output:
(on)

(

/1024)

3.9 kHz (

= 4 MHz)

1.95 kHz (

= 2 MHz)

TMOE output pin Variable-frequency output:
(on)

toggled by timer E overflow

IRQ

input pin

External interrupt input

Note:

Don't care.

Bits 3 to 0: Reserved bits

Bits 3 to 0 are reserved; they always read 1, and cannot be modified.

163

8.6.3 Timer Operation

Timer E is an 8-bit up-counter that is incremented each time a clock pulse is input. It functions as
an interval or auto-reload timer. It can also output a square wave having a 50% duty cycle. Each
of these operation modes is explained below.

Interval timer operation

When bit TME7 in timer mode register E (TME) is cleared to 0, timer E functions as an 8-bit
interval timer.

Upon reset, timer counter E (TCE) is reset to H'00 and bit TME7 is cleared to 0, so up-
counting and interval timing resume immediately after the reset. The clock input to timer E is
selected from eight internal clock signals output by prescaler S. The selection is made by bits
TME2 to TME0 in TME.

After the count value in TCE reaches H'FF, the next clock signal input causes timer E to
overflow, setting bit IRRTE to 1 in interrupt request register 2 (IRR2). If bit IENTE = 1 in
interrupt enable register 2 (IENR2), a CPU interrupt is requested.*

At overflow, TCE returns to H'00, and starts counting up again.

During interval timer operation (TME7 = 0), when a value is set in timer load register E
(TLE), the same value is set in TCE.

Note: * For details on interrupts, see 3.2.2, Interrupts.

Auto-reload timer operation

Setting bit TME7 in TME to 1 causes timer E to function as an 8-bit auto-reload timer. When
a reload value is set in TLE, the same value is loaded into TCE, becoming the value from
which TCE starts its count.

After the count value in TCE reaches H'FF, the next clock signal input causes timer E to
overflow. The TLE value is then loaded into TCE, and the count continues from that value.
The overflow period can be set within a range from 1 to 256 input clocks, depending on the
TLE value.

The clock sources and interrupts in auto-reload mode are the same as for interval mode.

In auto-reload mode (bit TME7 = 1), setting a new TLE value also initializes TCE.

164

Table 8-11 Frequencies of Output Waveforms Generated by Timer E Overflow

Output Waveform (

= 2 MHz)

1 Count (TLE = H'FF)

�

256 Counts (TLE = H'00)

�

Internal Clock

Count Time

Output Frequency

Count Time

Output Frequency

8 (250 kHz)

8 �s

125 kz

2024 �s

488.3 Hz

/32 (62.5 kHz)

32 �s

31.25 kHz

8192 �s

122.1 Hz

/128 (15.62 kHz)

128 �s

7.8125 kHz

32.768 ms

30.5 Hz

/256 (7.8125 kHz)

256 �s

3.9063 kHz

65.536 ms

15.3 Hz

/512 (3.9062 kHz)

512 �s

1.9531 kHz

131.072 ms

7.63 Hz

/2048 (976.5 Hz)

2.048 ms

488.3 Hz

524.288 ms

1.91 Hz

/4096 (488.2 Hz)

4.096 ms

244.1 Hz

1048.576 ms 0.95 Hz

/8192 (244.1 Hz)

8.192 ms

122.1 Hz

2097.152 ms 0.477 Hz

Output Waveform (

= 4 MHz)

1 Count (TLE = H'FF)

�

256 Counts (TLE = H'00)

�

Internal Clock

Count Time

Output Frequency

Count Time

Output Frequency

8 (500 kHz)

4 �s

250 kz

1024 �s

976.6 Hz

/32 (125 kHz)

16 �s

62.5 kHz

4096 �s

244.1 Hz

/128 (31.25 kHz)

64 �s

15.625 kHz

16.384 ms

61.0 Hz

/256 (15.625 kHz)

128 �s

7.8125 kHz

32.768 ms

30.5 Hz

/512 (7.8125 kHz)

256 �s

3.9063 kHz

65.536 ms

15.3 Hz

/2048 (1.963 Hz)

1.024 ms

976.6 Hz

262.144 ms

3.8 Hz

/4096 (976.52 Hz)

2.048 ms

488.3 Hz

524.288 ms

1.91 Hz

/8192 (488.2 Hz)

4.096 ms

244.1 Hz

1048.576 ms 0.95 Hz

166

8.7 Interrupts

Timer A to E interrupts are requested when a timer overflows or underflows. Each timer is
assigned its own vector address. The priority of interrupts is in the order of timer A (high) to
timer E (low). Further details are given in 3.2.2, Interrupts, table 3-2, Interrupt Sources.

When timers A to E overflow, the corresponding bit IRRTA to IRRTE in interrupt request register
2 (IRR2) is set to 1. These interrupt flags are not cleared even if the interrupt is accepted. They
must be cleared to 0 by software in the interrupt handler routine.

Interrupts may be enabled or disabled independently for each timer by means of bits IENTA to
IENTE in interrupt enable register 2 (IENR2).

For further details see 3.2.3, Interrupt Control Registers.

8.8 Application Notes

Even when the EVENT bit in port mode register 1 (PMR1) designates the P1

usage of pin

EVENT, reading the P1

pin may cause timer D to increment. When using timer D, be sure

to clear timer counter D (TCD) by means of the CLR bit in timer mode register D (TMD).

167

9.2.2 PWM Data Registers U and L (PWDRU, PWDRL)

PWDRU and PWDRL form a 14-bit write-only register, with the upper 6 bits assigned to PWDRU
and the lower 8 bits to PWDRL. The value written to PWDRU and PWDRL gives the total high-
level width of one PWM waveform cycle.

When 14-bit data is written to PWDRU and PWDRL, the register contents are latched in the
PWM waveform generator, updating the PWM waveform generation data. The 14-bit data should
always be written in the following sequence, first to PWDRL and then to PWDRU.

Write the lower 8 bits to PWDRL.

Write the upper 6 bits to PWDRU.

PWDRU and PWDRL are write-only registers. If they are read, all bits read 1.

Upon reset, PWDRU and PWDRL are initialized to H'C000.

Bit

Initial value

Read/Write

PWDRU5

PWDRU4

PWDRU3

PWDRU0

PWDRU2

PWDRU1

PWDRU

Bit

Initial value

Read/Write

PWDRL7

PWDRL6

PWDRL5

PWDRL4

PWDRL3

PWDRL0

PWDRL2

PWDRL1

PWDRL

172

9.3 Operation

When using the 14-bit PWM, set the registers in the following sequence.

Set bit PWM in port mode register 2 (PMR2) to 1 so that pin P9

/PWM is designated for

PWM output.

Set bit PWCR0 in the PWM control register (PWCR) to select a conversion period of either
32768/

(PWCR0 = 1) or 16384/

(PWCR0 = 0).

Set the output waveform data in PWM data registers U and L (PWDRU/L). Be sure to write
in the correct sequence, first PWDRL then PWDRU. When data is written to PWDRU, the
data in these registers will be latched in the PWM waveform generator, updating PWM
waveform generation in synchronization with internal signals.

One conversion period consists of 64 pulses, as shown in figure 9-2. The total of the high-
level pulse widths during this period (T

) corresponds to the data in PWDRU and PWDRL.

This relation can be represented as follows.

= (data value in PWDRU and PWDRL + 64)

�

where t

is the PWM input clock period, either 2/

(bit PWCR0 = 0) or 4/

(bit PWCR0 = 1).

If the data value in PWDRU and PWDRL is between H'3FC0 and H'3FFF, the PWM
output level will be high.

When the data value is H'0000, T

= 64

�

/2 = 32 t

Example: Settings in order to obtain a conversion period of 8,192 �s:

When bit PWCR0 = 0, the conversion period is 16384/

, so

must be 2 MHz. In

this case t

= 128 �s, with 1/

(resolution) = 0.5 �s.

When bit PWCR0 = 1, the conversion period is 32768/

, so

must be 4 MHz. In

this case t

= 128 �s, with 2/

(resolution) = 0.5 �s.

Accordingly, for a conversion period of 8,192 �s, the system clock frequency (

)

must be 2 MHz or 4 MHz.

173

10.2 Register Descriptions

10.2.1 Serial Mode Register 1 (SMR1)

SMR1 is an 8-bit write-only register, for selecting the operation mode and the prescaler divider
ratio. Another function is to initialize the internal state of the serial interface, which happens at
each write access to SMR1.

When SMR1 is written to, serial clock supply to serial data registers U1 and L1 (SDRU1, SDRL1)
and to the octal/hexadecimal counter is stopped, and the octal/hexadecimal counter is reset to
H'00. Accordingly, writing to the serial mode register while the serial interface is operating will
abort data transmission or reception, and the serial communication interface 1 interrupt request
flag (IRRS1) will be set.

Upon reset, SMR1 is initialized to H'80.

Bit 7: Reserved bit

Bit 7 is reserved; it always reads 1, and cannot be modified.

Bits 6 to 4: Operation mode select (SMR16 to SMR14)

Bits 6 to 4 select the SCI1 operation mode.

Bit 6

Bit 5

Bit 4

SMR16

SMR15

SMR14

Description

Continuous clock output mode

(initial value)

SMR15, SMR14 set to value other

8-bit transfer mode

than 00

Continuous clock output mode

SMR15, SMR14 set to value other

16-bit transfer mode

than 00

Bit

Initial value

Read/Write

SMR16

SMR15

SMR14

SMR13

SMR10

SMR12

SMR11

177

Bits 3 to 0: Clock select (SMR13 to SMR10)

Bits 3 to 0 select the clock supplied to SCI1.

Bit 3

Bit 2

Bit 1

Bit 0

Clock

Prescaler

SMR13 SMR12 SMR11

SMR10 Pin SCK

Source

Divider Ratio

SCK

output Prescaler S

/1024 256

512

(initial value)

SCK

output Prescaler S

/256

128

SCK

output Prescaler S

/64

SCK

output Prescaler S

/32

SCK

output Prescaler S

/16

SCK

output Prescaler S

SCK

output Prescaler S

SCK

output Prescaler S

Not used

�

SCK

input

External clock --

10.2.2 Serial Data Register U1 (SDRU1)

Note:

Not fixed

SDRU1 is an 8-bit read/write register. It is used as the data register for the upper 8 bits in 16-bit
transfer (SDRL1 is used for the lower 8 bits).

Data written to SDRU1 is output to SDRL1 starting from the least significant bit (LSB), in
synchronization with the falling edge of the serial clock. This data is than replaced by LSB-first
data input at pin SI1, synchronized with the rising edge of the serial clock. In this way data is
shifted in the direction from the most significant bit (MSB) toward the LSB.

SDRU1 must be written or read only after data transmission or reception is complete.
If this register is read or written while a data transfer is in progress, the data contents are not
guaranteed.

The SDRU1 value upon reset is not fixed.

Serial Clock Period (�s)

= 4 MHz

= 2 MHz

Bit

Initial value

Read/Write

SDRU17

R/W

SDRU16

R/W

SDRU15

R/W

SDRU14

R/W

SDRU13

R/W

SDRU10

R/W

SDRU12

R/W

SDRU11

R/W

178

10.2.3 Serial Data Register L1 (SDRL1)

Note:

Not fixed

SDRL1 is an 8-bit read/write register. It is used as the data register in 8-bit transfer, and as the
data register for the lower 8 bits in 16-bit transfer (SDRU1 is used for the upper 8 bits).

In 8-bit transfer, data written to SDRL1 is output from pin SO1 starting from the least significant
bit (LSB), in synchronization with the falling edge of the serial clock. This data is then replaced
by LSB-first data input at pin SI1, synchronized with the rising edge of the serial clock. In this
way data is shifted in the direction from the most significant bit (MSB) toward the LSB.

In 16-bit transfer, operation is the same as for 8-bit transfer, except that input data is fed in via
SDRU1.

SDRL1 must be written or read only after data transmission or reception is complete. If this
register is read or written while a data transfer is in progress, the data contents are not guaranteed.

The SDRL1 value upon reset is not fixed.

10.2.4 Serial Port Register 1 (SPR1)

Note:

Not fixed

SPR1 is an 8-bit read/write register, bit 7 of which is connected to the last output stage of
SDRL1.

Bit

Initial value

Read/Write

SDRL17

R/W

SDRL16

R/W

SDRL15

R/W

SDRL14

R/W

SDRL13

R/W

SDRL10

R/W

SDRL12

R/W

SDRL11

R/W

Bit

Initial value

Read/Write

R/W

SO1 LAST

BIT

179

Bit 7: Extended data bit (SO1 LAST BIT)

Bit 7 holds the last bit of transmitted data after transmission ends.

Output from pin SO1 can be altered by software by modifying this bit either before or after
transmission.

If this bit is written during data transmission, the data contents are not guaranteed.

Bit 7
SO1 LAST BIT

Description

Output from pin SO

is low.

(initial value)

Output from pin SO

is high.

Bits 6 to 0: Reserved bits

Bits 6 to 0 are reserved: they always read 1, and cannot be modified.

10.2.5 Port Mode Register 2 (PMR2)

PMR2 is an 8-bit read/write register, for switching the port 9 pin functions. Bits 3 to 1, in
combination with SMR1, set the SCI1 operation mode.

Upon reset, PMR2 is initialized to H'00.

Bits 3 to 1 are explained here. For bits 7 to 4 and bit 0, see 7.10.2 (1), Port Mode Register 2
(PMR2).

Bit 3: Pin P9

/SO

function switch (SO1)

Bit 3 selects whether pin P9

/SO

functions as a P9

input/output pin or as the SO

output pin.

Bit 3
SO1

Description

Pin P9

/SO

functions as P9

I/O pin.

(initial value)

Pin P9

/SO

functions as SO

output pin. Setting bit SCK1 to 1 and

clearing bit SI1 to 0 puts SCI1 in transmit mode.

Bit

Initial value

Read/Write

R/W

SO2

R/W

SI2

R/W

SCK2

R/W

SO1

R/W

PWM

R/W

SI1

R/W

SCK1

R/W

UP/

DOWN

180

Bit 2: Pin P9

/SI

function switch (SI1)

Bit 2 selects whether pin P9

/SI

functions as a P9

input/output pin or as the SI

output pin.

Bit 2
SI1

Description

Pin P9

/SI

functions as P9

I/O pin.

(initial value)

Pin P9

/SI

functions as SI

output pin. Setting bit SCK1 to 1 and

clearing bit SO1 to 0 puts SCI1 in receive mode.

Bit 1: Pin P9

/SCK

function switch (SCK1)

Bit 1 selects whether pin P9

/SCK

functions as a P9

input/output pin or as the SCK

input/output pin.

Bit 1
SCK1

Description

Pin P9

/SCK

functions as P9

I/O pin.

(initial value)

Pin P9

/SCK

functions as SCK

I/O pin. The direction of clock

I/O and the prescaler divider ratio are set in serial mode register 1 (SMR1).

10.2.6 Port Mode Register 3 (PMR3)

PMR3 is an 8-bit read/write register, for enabling the PMOS transistors of SCI1 and SCI2 data
output pins (pins SO

and SO

), and for controlling SCI2 chip select output (pin SI

CS).

Upon reset, PMR3 is initialized to H'97.

Bit 3 is explained here. For bits 6 and 5, see 11.2.5, Port Mode Register 3 (PMR3).

Bit 3: Pin SO

PMOS on/off (SO1PMOS)

Bit 3 enables or disables the PMOS buffer transistor of pin P9

/SO

Bit 3
S01PMOS

Description

The PMOS transistor of pin P9

/SO

is enabled: CMOS output.

(initial value)

The PMOS transistor of pin P9

/SO

is disabled: NMOS open-drain output.

Bit

Initial value

Read/Write

R/W

SO2

PMOS

SO1

PMOS

181

10.3 Operation

10.3.1 Overview

SCI1 sends and receives data in synchronization with clock pulses.

SCI1 operation modes are set by bits 6 to 4 of serial mode register 1 (SMR1) and bits 3 to 1 of
port mode register 2 (PMR2) in combination, as shown in table 10-3.

Table 10-3 SCI1 Operation Mode Setting

SMR1

PMR2

SMR16

SMR15

SMR14

PMR23

PMR22

PMR21

Operation Mode

Serial communication disabled

Continuous clock output mode

8-bit transmit mode

8-bit receive mode

8-bit transmit/receive mode

16-bit transmit mode

16-bit receive mode

16-bit transmit/receive mode

Note:

Don't care.

SCI1 consists of SMR1, serial data register U1 (SDRU1), serial data register L1 (SDRL1), serial
port register 1 (SPR1), an octal/hexadecimal counter, and a multiplexer. (See figure 10-1.)

Pin SCK

and the serial clock are controlled by writing data to SMR1.

SDRU1 and SDRL1 are used to write transmit data and to hold received data; these registers can
be written and read by software. Data in these registers is shifted in synchronization with the
serial clock, for input and output at pins SI

and SO

SCI1 operation starts with a dummy read of SMR1. The octal/hexadecimal counter is cleared to
H'0 by this dummy read, and starts counting anew from the falling edge of the serial clock (pin
SCK

), being incremented by 1 at each rising edge of the serial clock. If 8 or 16 serial clock

cycles are input and the counter overflows, or if data transmission or reception is aborted, the
octal/hexadecimal counter is cleared to H'0. At the same time bit IRRS1 in interrupt request
register 3 (IRR3) is set to 1.

For more details on interrupts, see 3.2.2, Interrupts.

SMR15, SMR14
set to value other
than 00

182

10.3.2 Data Transfer Format

Figure 10-2 shows the synchronous data transfer format. Data can be sent and received in lengths
of 8 bits or 16 bits. Data is sent and received starting from the least significant bit, in LSB-first
format. Transmit data is output from one falling edge of the serial clock until the next falling
edge. Receive data is latched at the rising edge of the serial clock.

Figure 10-2 Synchronous Data Transfer Format

10.3.3 Clock

Eight internal clock sources or an external clock may be selected as the serial clock. When an
internal clock is used, pin SCK

is the clock output pin.

10.3.4 Data Transmit/Receive

Initializing SCI1

Before data is sent or received, first SCI1 must be initialized by software. This is done by
writing the desired transfer conditions in serial mode register 1 (SMR1).

Transmitting

A transmit operation is carried out as follows.

�

Set bit SO1 in port mode register 2 (PMR2) to 1, making pin P9

/SO

the SO

output pin.

Also set bit SCK1 in PMR2 to 1, making pin P9

/SCK

the SCK

I/O pin. If necessary, set

the SO1PMOS bit in PMR3 for NMOS open-drain output at pin SO

Bit 0

Bit 1

Bit 2

Bit 3

Bit n � 1

Bit n

SCK

SI input data
latch timing

LSB

MSB

n = 7: 8-bit transfer mode
n = 15: 16-bit transfer mode

183

�

Set bit SMR16 in SMR1 to 1 or 0, and set bits SMR15 and SMR14 to a value other than 00,
designating 8- or 16-bit transfer mode. Select the serial clock with bits SMR13 to SMR10.
Writing data to SMR1 initializes the internal state of SCI1.

�

Write transmit data in serial data register L1 (SDRL1) and serial data register U1
(SDRU1), as follows.
8-bit transfer mode:

SDRL1

16-bit transfer mode: Upper byte in SDRU1, lower byte in SDRL1

�

Execute a dummy read of SMR1. SCI1 starts operating, and outputs the transmit data at pin
SO

�

After data transmission is complete, bit IRRS1 in interrupt request register 3 (IRR3) is
set to 1.

When an internal clock source is used, a serial clock is output from pin SCK

in synchronization

with the transmit data. After data transmission is complete, the serial clock is not output until the
next dummy read of SMR1. During this time, pin SO

continues to output the value of the last bit

transmitted.

When an external clock source is used, data is transmitted in synchronization with the serial clock
input at pin SCK

. After data transmission is complete, if the serial clock continues to be input,

transmission resumes.

Between transmissions, the output value of pin SO

can be changed by rewriting bit 7 (SO1 LAST

BIT) in serial port register 1 (SPR1).

Executing a dummy read of SMR1 during transmission will cause a transmit error, setting bit
IRRS1 in IRR3 to 1.

Receiving

A receive operation is carried out as follows.

�

Set bit SI1 in port mode register 2 (PMR2) to 1, making pin P9

/SI

the SI

input pin. Also

set bit SCK1 in PMR2 to 1, making pin P9

/SCK

the SCK

I/O pin.

�

Set bit SMR16 in serial mode register 1 (SMR1) to 1 or 0, and set bits SMR15 and SMR14 to
a value other than 00, designating 8- or 16-bit transfer mode. Select the serial clock with bits
SMR13 to SMR10. Writing data to SMR1 initializes the internal state of SCI1.

�

Execute a dummy read of SMR1. SCI1 starts operating, and receive data is input at pin SI

184

�

After data reception is complete, bit IRRS1 in interrupt request register 3 (IRR3) is set to 1.

�

Read the received data from SDRL1 and SDRU1, as follows.
8-bit transfer mode:

SDRL1

16-bit transfer mode: Upper byte in SDRU1, lower byte in SDRL1

When an internal clock source is used, a dummy read of SMR1 immediately starts a data receive
operation. The serial clock is output from pin SCK

When an external clock source is used, after the dummy read of SMR1, data is received in
synchronization with the serial clock input at pin SCK

. After data reception is complete, if the

serial clock continues to be input, reception resumes.

Executing a dummy read of SMR1 during reception will cause a receive error, setting bit IRRS1 in
IRR3 to 1.

Simultaneous transmit/receive

A simultaneous transmit/receive operation is carried out as follows.

�

Set bits SO1, SI1, and SCK1 in PMR2 to 1, designating the SO

output pin, SI

pin, and

SCK

pin functions. If necessary, set the SO1PMOS bit in PMR3 for NMOS open-drain

output at pin SO

�

Write transmit data in SDRL1 and SDRU1, as follows.
8-bit transfer mode:

SDRL1

16-bit transfer mode: Upper byte in SDRU1, lower byte in SDRL1

�

Execute a dummy read of SMR1. SCI1 starts operating: transmit data is output at pin SO

and receive data is input at pin SI

�

After data transmission and reception are complete, bit IRRS1 in IRR3 is set to 1.

�

Read the received data from SDRL1 and SDRU1.
8-bit transfer mode:

SDRL1

16-bit transfer mode: Upper byte in SDRU1, lower byte in SDRL1

185

In simultaneous data transmit/receive, the transmit operation and receive operation described in
10.3.4 sections 2 and 3 take place at the same time. See those sections for further details.

During a transmit/receive operation, a dummy read of SMR1 will result in a transmit/receive error,
setting bit IRRS1 in IRR3 to 1.

10.3.5 SCI1 State Transitions

SCI1 has three internal states, as shown in figure 10-3.

In the serial start pending state, the internal state of the serial communication interface is
initialized. In this state, the serial communication interface does not operate even if a serial clock
signal is input. Executing a dummy read of SMR1 changes this state to the serial clock pending
state.

In the serial clock pending state, when a serial clock signal is input the octal/hexadecimal counter
starts counting up and the serial data register starts shifting, entering the transfer state. If
continuous clock output mode has been selected, however, SCI1 outputs the clock signal
continuously and does not enter the transfer state.

In the transfer state, when 8 or 16 transfer clock cycles are input, or if an SMR1 dummy read is
executed, the octal/hexadecimal counter is reset to H'0, and SCI1 enters the serial clock pending
state. Writing to SMR1 in the transfer state will reset the octal/hexadecimal counter to H'0 and
change to the serial start pending state. In transitions from the transfer state to another state, the
resetting of the octal/hexadecimal counter to H'0 sets bit IRRS1 in IRR3 to 1.

If an internal clock source is selected, a dummy read of SMR1 starts output of the serial clock,
which stops after 8 or 16 clock output cycles.

After writing to SMR1 in the serial clock pending state or transfer state, it is necessary to write to
SMR1 again in order to initialize the initial state of the serial communication interface. Writing to
SMR1 changes the state to the serial start pending state.

186

Figure 10-3 SCI1 State Transitions

10.3.6 Serial Clock Error Detection

In the transfer state, if an extraneous pulse is superimposed on the normal serial clock signal due
to external noise, SCI1 may function incorrectly. Serial clock errors can be detected by means of
the procedure shown in figure 10-4.

In the transfer clock pending state, if more than the normal 8 or 16 serial clock cycles are
mistakenly input, SCI1 changes from the transfer state to the transfer clock pending state and then
back to the transfer state. After bit IRRS1 in interrupt request register 3 (IRR3) is cleared to 0,
writing a value in serial mode register 1 (SMR1) changes the state to serial start pending, and bit
IRRS1 is again set to 1.

Serial clock pending state

octal counter = 000 or

hexadecimal counter = 0000

Transfer state

octal counter / 000 or

hexadecimal counter / 0000

SMR1 write

SMR1 write
(IRRS1 1)

SMR1 dummy
read
(serial start)

8 or 16 serial
clock cycles
(internal clock)
(IRRS1 1)

Serial clock

SMR1 dummy read (serial start)
(IRRS1 1)
8 or 16 serial clock cycles
(external clock)

Serial start (SMR1 dummy read) pending state

octal counter = 000 or

hexadecimal counter = 0000

serial clock disabled.

187

11.1.3 Pin Configuration

Table 11-1 shows the SCI2 pin configuration.

Table 11-1 Pin Configuration

Name

Abbrev.

I/O

Function

SCI2 clock pin

SCK

I/O

SCI2 clock input/output

SCI2 data input pin

Input

SCI2 receive data input

SCI2 data output pin

Output

SCI2 transmit data output

SCI2 chip select output pin

Output

SCI2 chip select output

Note:

Functions of pins P9

/SCK

, P9

/SI

, and P9

/SO

are switched in port mode register 2

(PMR2) and port mode register 3 (PMR3). For PMR2, see 7.10.2 1, Port mode register 2
(PMR2).

11.1.4 Register Configuration

Table 11-2 shows the SCI2 register configuration.

Table 11-2 SCI2 Registers

Name

Abbrev.

R/W

Initial Value

Address

32-byte data buffer

R/W

Not fixed

H'FF80 to H'FF9F

Start address register

STAR

R/W

H'E0

H'FFA0

End address register

EDAR

R/W

H'E0

H'FFA1

Serial control register 2

SCR2

R/W

H'E0

H'FFA2

Status register

STSR

R/W

H'E0/H'E8

H'FFA3

Port mode register 2

PMR2

R/W

H'00

H'FFEC

Port mode register 3

PMR3

R/W

H'97

H'FFED

190

11.2 Register Descriptions

11.2.1 Start Address Register (STAR)

STAR is an 8-bit read/write register, for designating the transfer start address in the memory area
from H'FF80 to H'FF9F allocated to the 32-byte data buffer.

The 32 bytes from H'00 to H'1F designated by the lower 5 bits of STAR (bits STA4 to STA0)
correspond to addresses H'FF80 to H'FF9F.

Data is sent or received continuously using the area defined in STAR and in the end address
register (EDAR).

Bits 7 to 5 are reserved; they always read 1, and cannot be modified.

Upon reset, STAR is initialized to H'E0.

11.2.2 End Address Register (EDAR)

EDAR is an 8-bit read/write register, for designating the transfer end address in the memory area
from H'FF80 to H'FF9F allocated to the 32-byte data buffer.

The 32 bytes from H'00 to H'1F designated by the lower 5 bits of EDAR (bits EDA4 to EDA0)
correspond to addresses H'FF80 to H'FF9F.

Data is sent or received continuously using the area defined in STAR and EDAR. If the same
value is designated in both STAR and EDAR, only one byte of data is transferred.

Bits 7 to 5 are reserved; they always read 1, and cannot be modified.

Upon reset, EDAR is initialized to H'E0.

Bit

Initial value

Read/Write

STA4

R/W

STA3

R/W

STA0

R/W

STA2

R/W

STA1

R/W

Bit

Initial value

Read/Write

EDA4

R/W

EDA3

R/W

EDA0

R/W

EDA2

R/W

EDA1

R/W

191

11.2.3 Serial Control Register 2 (SCR2)

SCR2 is an 8-bit read/write register, for selecting whether SCI2 transmits or receives, for gap
insertion during continuous transfer, and for serial clock selection.

Upon reset, SCR2 is initialized to H'E0.

Bits 7 to 5: Reserved bits

Bits 7 to 5 are reserved; they always read 1, and cannot be modified.

Bit 4: Transmit/receive select (I/O)

Bit 4 selects SCI2 transmit or receive mode.

Bit 4
I/O

Description

SCI2 is in receive mode.

(initial value)

SCI2 is in transmit mode.

Bits 3 and 2: Gap select (GAP2 to GAP1)

When data is transmitted or received continuously, gaps can be inserted at data divisions by
holding the serial clock high for a length of time designated by bits 3 and 2. Bits 3 and 2 are valid
when an internal clock source is selected as the serial clock (PS1 and 0

11).

Data divisions may be placed every 8 bits or 16 bits; this is selected in bit GIT in the status
register (STSR).

Bit 3

Bit 2

GAP2

GAP1

Description

Serial clock keeps the same duty cycle even at data divisions.

(initial value)

Serial clock high level extended by one clock cycle at data divisions.

Serial clock high level extended by two clock cycles at data divisions.

Serial clock high level extended by eight clock cycles at data divisions.

Bit

Initial value

Read/Write

I/O

R/W

GAP2

R/W

PS0

R/W

GAP1

R/W

PS1

R/W

192

Bits 1 and 0: Serial clock select (PS1 to PS0)

Bits 1 and 0 select one of three internal clock sources or an external clock.

Serial Clock Period

PS1

PS0

Pin SCK

Clock Source

= 4 MHz

= 2 MHz

= 1 MHz

SCK

output

Prescaler S

/2 (initial value)

1 �s

2 �s

SCK

output

Prescaler S

1 �s

2 �s

4 �s

SCK

output

Prescaler S

2 �s

4 �s

8 �s

SCK

input

External clock

Note:

Can be set, but operation is not guaranteed.

11.2.4 Status Register (STSR)

Notes: 1. Not fixed

2. Cleared to 0 by write operation to STSR.

STSR is an 8-bit register indicating the SCI2 operation state, error status, etc. Writing to this
register during data transmission may cause misoperation.

Upon reset, STSR is initialized to H'E0 or H'E8.

Bits 7 to 5: Reserved bits

Bits 7 to 5 are reserved; they always read 1, and cannot be modified.

Bit 4: Extended data bit (SO2 LAST BIT)

Bit 4 holds the last bit of transmitted data after transmission ends.

Output from pin SO

can be altered by software by modifying this bit either before or after

transmission.

Writing to this bit during data transmission may cause misoperation.

Bit 1 Bit 2

Prescaler

PS1

PS0

Divider Ratio

Bit

Initial value

Read/Write

R/W

OVR

R/W

STF

R/W

GIT

R/W

SO2 LAST

BIT

193

Bit 4
SO2 LAST BIT

Description

Output from pin SO

is low.

(initial value)

Output from pin SO

is high.

Bit 3: Overrun flag (OVR)

If the amount of data transferred exceeds the buffer size setting, or if an extraneous pulse is
superimposed on the normal serial clock due to external noise, SCI2 overruns and bit 3 is set to 1.

Bit 3
OVR

Description

[Clear conditions]
When STSR is written to.

(initial value)

[Set conditions]
When overrun occurs.

Bit 2: Waiting flag (WT)

If an attempt is made to execute a read or write instruction to the 32-byte buffer during a serial
data transfer, the instruction is ignored, and bit 2 is set to 1 along with bit IRRS2 in interrupt
request register 3 (IRR3).

Bit 2
WT

Description

[Clear conditions]
When STSR is written to.

(initial value)

[Set conditions]
When a read/write to the 32-byte buffer is attempted during serial transfer.

Bit 1: Gap interval flag (GIT)

Bit 1 designates whether the extended serial clock high-level interval designated in bits GAP2 and
GAP1 in serial control register 2 (SCR2) occurs every 8 bits or every 16 bits. This setting is valid
only for internal clock operation.

Bit 1
GIT

Description

Gap specified by GAP2 and GAP1 is inserted every 16 bits.

(initial value)

Gap specified by GAP2 and GAP1 is inserted every 8 bits.

194

Bit 0: Start/busy flag (STF)

Setting bit 0 to 1 starts an SCI2 transfer operation. This bit stays at 1 during the transfer, and is
cleared to 0 after the transfer is complete. It can therefore be used as a busy flag as well.
Clearing this bit to 0 during a transfer aborts the transfer, initializing SCI2. The contents of
the 32-byte data buffer and of registers other than STSR are unchanged when this happens.

Bit 0
STF

Explanation

[Read access]

(initial value)

Indicates transfer not in progress.

[Write access]
Stops transfer.

[Read access]
Indicates transfer in progress.

[Write access]
Starts transfer.

11.2.5 Port Mode Register 3 (PMR3)

PMR3 is an 8-bit read/write register, for enabling the PMOS transistors of SCI1 and SCI2 data
output pins (pin P9

/SO

and pin P9

/SO

), and for controlling SCI2 chip select output (pin

CS).

Upon reset, PMR3 is initialized to H'97.

For bit 3, see 10.2.6, Port Mode Register 3 (PMR3).

Bit 7: Reserved bit

Bit 7 is reserved; it always reads 1, and cannot be modified.

Bit

Initial value

Read/Write

R/W

SO2

PMOS

SO1

PMOS

195

Bit 6: Pin SO

PMOS on/off (SO2PMOS)

Bit 6 enables or disables the PMOS buffer transistor of pin P9

/SO

Bit 6
SO2PMOS

Description

PMOS transistor of pin P9

/SO

is enabled: CMOS output.

(initial value)

PMOS transistor of pin P9

/SO

is disabled: NMOS open-drain output.

Bit 5: Chip select output select (CS)

In combination with bit SI2 in port mode register 2 (PMR2), bit 5 selects the

CS output function

of pin P9

/SI

CS. The CS output pin function is valid when an internal clock source is selected

as the serial clock, and only in transmit mode.

PMR2

PMR3

Bit 5

SI2

Description

Pin P9

/SI

functions as P9

I/O pin.

(initial value)

Pin P9

/SI

functions as P9

I/O pin.

Pin P9

/SI

functions as SI

input pin.

Pin P9

/SI

functions as

output pin.

Bits 4 and 2 to 0: Reserved bits

These bits are reserved; they always read 1, and cannot be modified.

196

11.3 Operation

11.3.1 Overview

SCI2 has a 32-byte data buffer, making possible continuous transfer of up to 32 bytes of data with
one operation. SCI2 transmits and receives data in synchronization with clock pulses.

Selection of transmit or receive mode and of the serial clock is made in serial control register 2
(SCR2).

The start address register (STAR) and end address register (EDAR) designate the area within the
32-byte data buffer for holding transfer data. The address range from H'FF80 to H'FF9F is
allocated to this data buffer. The start and end positions of the transfer data area are indicated in
the lower 5 bits of STAR and EDAR.

After parameters have been set in port mode register 2 (PMR2), port mode register 3 (PMR3),
SCR2, STAR, and EDAR, then when the STF bit of the status register (STSR) is set to 1, SCI2
begins a transfer operation. STF remains set to 1 during the transfer, and is cleared to 0 when the
transfer is complete. The STF bit can therefore be used as a busy flag. Clearing the STF bit to 0
during a transfer stops the transfer operation and initializes SCI2. The contents of the data buffer
and of other registers are unchanged in this case.

During a transfer, the CPU cannot read or write the data buffer. If a write instruction is issued it is
ignored; it has the same effect as a NOP instruction except that it takes more states. Read access
during a transfer yields H'FF.

When the transfer is complete, or if a data buffer read or write is attempted during the transfer, bit
IRRS2 in interrupt request register 3 (IRR3) is set to 1. In case of an overrun error or a data buffer
read or write during the transfer, bit OVR or WT of STSR is set to 1.

Note: If the start address is set to a value higher than the end address, the result is as shown in

figure 11-2. The data transfer wraps around from address H'FF9F to address H'FF80 and
continues to the end address.

197

Figure 11-2 Operation When Start Address Exceeds End Address

11.3.2 Clock

Three internal clock sources or an external clock may be selected as the serial clock. When an
internal clock is selected, pin SCK

becomes the clock output pin.

11.3.3 Data Transfer Format

Figure 11-3 shows the SCI2 data transfer format. Data is sent and received starting from the least
significant bit, in LSB-first format. Transmit data is output from one falling edge of the serial
clock until the next falling edge. Receive data is latched at the rising edge of the clock.

When SCI2 operates on an internal clock and is in transmit mode, a gap may be inserted at data
divisions (every 8 bits or 16 bits). During this gap, the serial clock stays at the high level for a
designated number of clock cycles (see figures 11-4 through 11-6).

The

CS output remains low during the gap.

Gap insertion and the length of the gap are designated in bits GAP2 and GAP1 in serial control
register 2 (SCR2). Bit GIT in the status register (STSR) designates whether gaps occur at 8-bit or
16-bit intervals.

H'FF80

H'FF9F

H'00

H'1F

End address

Start address

End

Start

198

Figure 11-6 8-Clock Gap Insertion (Bits GAP2 and GAP1 = 11)

11.3.4 Data Transmit/Receive

SCI2 initialization

Serial communication on SCI2 first of all requires that SCI2 be initialized by software. This

involves clearing bit STF in the status register (STSR) to 0, then selecting pin functions and
transfer modes in port mode register 2 (PMR2), port mode register 3 (PMR3), the start
address register (STAR), the end address register (EDAR), and serial control register 2
(SCR2).

Transmitting

A transmit operation is carried out as follows.

�

Set bit SO2 in port mode register 2 (PMR2) to 1, making pin P9

/SO

the SO

output pin. If

necessary, set the SO2PMOS bit and CS bit in PMR3 for NMOS open-drain output at pin
SO

and for chip select output at pin P9

/SI

CS.

�

Write transmit data in the 32-byte data buffer (H'FF80 to H'FF9F).

�

Set the transfer start address in the lower 5 bits of STAR.

�

Set the transfer end address in the lower 5 bits of EDAR.

�

In SCR2, select transmit mode (bit I/O = 1), the serial clock, and gap insertion (internal clock

operation only).

�

Select the data gap interval with bit GIT of STRS, then set bit STF to 1. Setting bit STF starts

the transmit operation.

SCK
output

SI input data
latch timing

Bit 14

(Bit 6)

Bit 15

(Bit 7)

Bit 16

(Bit 8)

Note:

When bit GIT = 1, a gap is inserted at 8-bit intervals.

Serial clock 8

�

200

�

After data transmission is complete, bit IRRS2 in interrupt request register 3 (IRR3) is set to
1, and bit STF in STSR is cleared to 0.

If an internal clock source is used, a serial clock is output from pin SCK

in synchronization with

the transmit data. After data transmission is completed, the serial clock is not output until bit STF
is again set. During this time, pin SO2 continues to output the value of the last bit transmitted.

When an external clock source is used, data is transmitted in synchronization with the serial clock
input at pin SCK

. After data transmission is completed, further transmission does not take place

even if the serial clock continues to be input; pin SO

continues to output the value of the last bit

transmitted.

Between transmissions, the output value of pin SO

can be changed by rewriting bit SO2 LAST

BIT in STSR.

An attempt to read or write the data buffer during transmission will cause bit IRRS2 in IRR3 to be
set to 1. Bit WT in STSR will also be set to 1.

Receiving

A receive operation is carried out as follows.

�

Set bit SI2 in port mode register 2 (PMR2) to 1, making pin P9

/SI

/CS the SI

input pin.

�

Allocate an area to hold the received data in the 32-byte data buffer and set the start address in
the lower 5 bits of the start address register (STAR).

�

Set the transfer end address in the lower 5 bits of the end address register (EDAR).

�

In serial control register 2 (SCR2), select receive mode (bit I/O = 0) and the serial clock.

�

Set bit STF of the status register (STSR) to 1, starting the receive operation.

�

After receiving is completed, bit IRRS2 in interrupt request register 3 (IRR3) is set to 1, and
bit STF is cleared to 0.

�

Read the received data from the data buffer.

If an internal clock source is used, setting bit STF to 1 in STSR immediately starts a data receive
operation. The serial clock is output from pin SCK

201

When an external clock source is used, after bit STF is set, data is received in synchronization
with the clock input at pin SCK

. After receiving is completed, no further receive operations take

place until bit STF is again set, even if the serial clock continues to be input.

An attempt to read or write the data buffer during receiving will cause bit IRRS2 in IRR3 and bit
WT in STSR to be set to 1. Bit OVR in STSR is set to 1 if an overrun error occurs.

When SCI2 operates on an internal clock and is in transmit mode, a gap may be inserted at data
divisions (every 8 bits or 16 bits). During this gap, serial clock stays at the high level for a
designated number of clock cycles (see figures 11-4 through 11-6).

Gap insertion and the length of the gap are designated in bits GAP2 and GAP1 of SCR2. Bit GIT
of STSR designates whether gaps occur at 8-bit or 16-bit intervals.

11.4 Interrupts

SCI2 can generate interrupts when a transfer is completed and when the data buffer is read or
written during a transfer. These interrupts are assigned to the same vector address.

When the above conditions occur, bit IRRS2 in interrupt request register 3 (IRR3) is set to 1.
SCI2 interrupt requests can be enabled or disabled in bit IENS2 of interrupt enable register 3
(IENR3). For further details, see 3.2.2, Interrupts.

When an overrun error occurs, or when a read or write of the data buffer is attempted during a
transfer, the OVR or WT bit in the status register (STSR) is set to 1. These bits can be used to
determine the cause of the error.

11.5 Application Notes

Do not write to any register during a transfer (while bit STF of STSR is set to 1), since this
can cause misoperation.

When receiving, set bit SI2 in port mode register 2 (PMR2) to 1 and clear bit CS in port mode
register 3 (PMR3) to 0 to select the SI

pin function. If bit CS = 1 and bit SI2 = 1, selecting

the

CS pin function, incorrect data will be received.

202

Section 12 VFD Controller/Driver

12.1 Overview

The H8/3714 Series is equipped with an on-chip vacuum fluorescent display (VFD) controller/
driver and high-voltage, high-current pins, for direct VFD driving.

12.1.1 Features

The VFD controller/driver has the following features.

�

Maximum of 24 segment pins and 16 digit pins (20 segment pins, eight digit pins, and eight
switched segment/digit pins).

�

Brightness can be adjusted in eight steps (dimmer function).

�

Automatic shifting of displayed digit.

�

Digit pins and segment pins can be switched over to use as general-purpose high-voltage pins.

�

Optional key scan interval.

�

Interrupt generated when key scan interval starts.

12.1.2 Block Diagram

Figure 12-1 shows a block diagram of the VFD controller/driver.

Figure 12-1 Block Diagram of VFD Controller/Driver

Internal data bus

VFDR

DBR

VFSR

IRRKS

Display timing

generator circuit

VFD display RAM

Digit pins

Segment pins

Notation:
VFDR: VFD digit control register
DBR: Digit beginning register
VFSR: VFD segment control register
IRRKS: Key scan interrupt request flag (bit 6 of interrupt request register 3)

203

Bits 3 to 0: Digit pin select (DR3 to DR0)

Bits 3 to 0, in combination with bits 3 to 0 of the digit beginning register (DBR), designate the
digit pins used.

Bit 3

Bit 2

Bit 1

Bit 0

DR3

DR2

DR1

DR0

Pins Valid as Digit Pins

to FD

(initial value)

to FD

Note:

For the switching between digit and segment use of pins FD

/FS

to FD

/FS

, which can

function as either digit or segment pins, see 12.2.3, Digit Beginning Register (DBR).

Figure 12-2 Order of Digit Output

m+1

m+2

n�2

n�1

Segment
data

207

12.2.2 VFD Segment Control Register (VFSR)

VFSR is an 8-bit read/write register for control of segment output.

Upon reset, VFSR is initialized to H'20.

Bit 7: VFD/port switching flag (VFLAG)

Bit 7 designates whether pins Pnn/FDnn and Pnn/FSnn are used as VFD pins (FDnn, FSnn) or as
general-purpose ports (Pnn).

Bit 7
VFLAG

Description

All of pins Pnn/FDnn and all of pins Pnn/FSnn function as

(initial value)

general-purpose ports.

Pnn/FDnn and Pnn/FSnn function as VFD pins according to the designations in bits
DR3 to DR0 in the VFD digit control register (VFDR), bits SR4 to SR0 in VFSR, and
bits DBR3 to DBR0 in the digit beginning register (DBR).

Note:

Even when this flag is set to 1, during a key scan interval the segment pins function as
general-purpose ports; for this reason, when this flag is read during a key scan interval it
reads 0.

Bit 6: Key scan enable (KSE)

Bit 6 enables or disables the addition of a key scan interval (T

digit

) to the VFD operation frame

specified by the combination of bits DR3 to DR0 in the VFD digit control register, bits SR4 to
SR0 in the VFD segment control register, and bits DBR3 to DBR0 in the digit beginning register.

Bit 6
KSE

Description

No key scan interval.

(initial value)

A key scan interval can be added. See also under bit 7 (VFLAG) above.

Bit 5: Reserved bit

Bit 5 is reserved; it always reads 1, and cannot be modified.

Bit

Initial value

Read/Write

VFLAG

R/W

KSE

R/W

SR4

R/W

SR3

R/W

SR0

R/W

SR2

R/W

SR1

R/W

208

Bits 4 to 0: Segment pin select (SR4 to SR0)

Bits 4 to 0, in combination with bits 3 to 0 of the digit beginning register (DBR), designate the
segment pins used.

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

SR4

SR3

SR2

SR1

SR0

Pins Valid as Segment Pins

(initial value)

to FS

Note:

For the switching between digit and segment use of pins FD

/FS

to FD

/FS

, which can

function as either digit or segment pins, see 12.2.3, Digit Beginning Register (DBR).

209

12.2.3 Digit Beginning Register (DBR)

DBR is an 8-bit read/write register for on/off control of the VFD controller/driver and for
switching functions of pins that can be either digit or segment pins.

Bit 7: VFD enable (VFDE)

Bit 7 switches the VFD controller/driver on and off.

Bit 7
VFDE Description

VFD controller/driver is in reset state.

(initial value)

VFD controller/driver is operative.

Note:

This setting is unrelated to whether pins Pnn/FDnn and Pnn/FSnn are used as VFD pins or
as general-purpose ports.

Bit 6: Display bit (DISP)

Bit 6 switches the display on and off.

Bit 6
DISP

Description

All segment pins (FS) are in the non-illuminating state (pulled down).

(initial value)

Display RAM data is output to segment pins (FS).

Bit 5: Reserved bit

Bit 5 is reserved; it always reads 1, and cannot be modified.

Bit 4: Reserved bit

Bit 4 is reserved, but it can be written and read.

Bit

Initial value

Read/Write

VFDE

R/W

DISP

R/W

DBR3

R/W

DBR0

R/W

DBR2

R/W

DBR1

R/W

210

Bits 3 to 0: Digit/segment pin function switch (DBR3 to DBR0)

Bits 3 to 0 designate the first digit pin and the first segment pin of those pins that can function
both ways. Bits DR3 to DR0 of the VFD digit control register (VFDR) and bits SR4 to SR0 of
VFSR must be set so that the first digit and segment pins are operational. Otherwise these pins
will not function.

Bit 3

Bit 2

Bit 1

Bit 0

DBR3

DBR2

DBR1

DBR0 Functions of FD

/FS

to FD

/FS

to FD

(initial value)

to FD

, FS

to FD

, FS

to FS

to FD

, FS

to FS

to FD

, FS

to FS

to FD

, FS

to FS

to FD

, FS

to FS

, FS

to FS

Notes: Digit pins (FD) and segment pins (FS) are controlled by both VFDR and VFSR. During a

key scan interval, digit pins (FD) and segment pins (FS) function as general-purpose ports.

Don't care.

211

12.3 Operation

12.3.1 Overview

The VFD controller/driver may use up to 24 segment pins (FS) and up to 16 digit pins (FD). Of
these, 8 pins may be used as either segment or digit pins; their function is switched in the digit
beginning register (DBR). The 32 pins assigned to the VFD controller are high-voltage, high-
current pins capable of directly driving a VFD.

12.3.2 Control Section

The control section consists of the VFD digit control register (VFDR), VFD segment control
register (VFSR), digit beginning register (DBR), display timing generator circuit, and VFD
display RAM (see figure 12-1).

Display timing is determined by the number of digits per frame. When the key scan feature is
activated, the frame is extended by one digit; during that interval only, segment pins and digit pins
may be used as general purpose ports by the CPU. These pins are in the non-illuminating state
(pulled down) during the key scan interval.

12.3.3 RAM Bit Correspondence to Digits/Segments

VFD display data is set in the VFD display RAM at addresses H'FEC0 through H'FEFF.
Table 12-3 shows the correspondence between digit/segment pins and the VFD display RAM bits.

212

213

able 12-3 Digit/Segment Pins and VFD Display RAM Bits

Note: Areas not used f

or displa

y ma

y be used as gener

al-pur

pose RAM.

--------

H'FEC3

H'FEC2

H'FEC7

H'FEC6

H'FECB

H'FECA

H'FECF

H'FECE

H'FED3

H'FED2

H'FED7

H'FED6

H'FEDB

H'FED

H'FEDF

H'FEDE

H'FEE3

H'FEE2

H'FEE7

H'FEE6

H'FEEB

H'FEEA

H'FEEF

H'FEEE

H'FEF3

H'FEF2

H'FEF7

H'FEF6

H'FEFB

H'FEF

H'FEFF

H'FEFE

MSB

LSB

MSB

LSB

54321

H'FEC1

H'FEC0

H'FEC5

H'FEC4

H'FEC9

H'FEC8

H'FECD

H'FECC

H'FED1

H'FED0

H'FED5

H'FED4

H'FED9

H'FED8

H'FEDD

H'FEDC

H'FEE1

H'FEE0

H'FEE5

H'FEE4

H'FEE9

H'FEE8

H'FEED

H'FEEC

H'FEF1

H'FEF0

H'FEF5

H'FEF4

H'FEF9

H'FEF8

H'FEFD

H'FEFC

MSB

LSB

MSB

LSB

r
t

Seg

Dig

r
t

Seg

Dig

12.3.4 Procedure for Starting Operation

The procedure for starting operation of the VFD controller/driver is given below for a case in
which digit pins FD

to FD

and segment pins FS

to FS

are used. It is assumed that data has

already been written to the VFD display RAM area.

�

Select the digit/key-scan time and dimmer resolution with bit FLMO of the VFD digit control
register (VFDR), and select the digit waveform with bits DM2 to DM0. Clear bits DR3 to
DR0 to 0000, making pins FD

to FD

operational.

�

Set the VFLAG bit of the VFD segment control register (VFSR) to 1, making the selected
pins valid as VFD pins. Set bit KSE to enable or disable the key scan interval. Set bits SR4
to SR0 to 11011, making pins FS

to FS

operational.

�

Set bits DBR3 to DBR0 in the digit beginning register (DBR) to 0011, designating pin FD

the first digit pin and pin FS

as the first segment pin. Set bit DISP to 1, turning the display

on, and set bit VFDE to 1, starting VFD controller/driver operation.

12.4 Interrupts

When the key scan interval starts, bit IRRKS in interrupt request register 3 (IRR3) is set to 1.
These VFD interrupt requests can be enabled or disabled by means of bit IENKS of interrupt
enable register 3 (IENR3). For further details, see 3.2.2, Interrupts.

12.5 Occurrence of Flicker when VFD Registers are Rewritten

The VFD controller/driver is initialized whenever one of its registers (VFDR, VFSR, DBR) is
rewritten. If this initialization takes place while a digit is being displayed, the contents displayed
just prior to initialization will in some cases remain as an after-image in other digits. (This
depends in part on the performance of the vacuum fluorescent display, but a momentary glow may
be visible.) Frequent rewriting of the registers can make these after-images bright enough to
appear as a false display. This problem can be avoided by employing the following programming
sequence when VFD controller/driver registers are rewritten.

Step

Description

DISP = 0

VFLAG = 0

Rewrite register (FLMO, DM0 to DM3, etc.)

Wait for at least T

digit

(display time of one digit). (Execute other routines.) If

the wait time is too long, the entire display may flicker. If the key scan feature
is activated, this wait time does not have to be specially programmed.

VFLAG = 1

DISP = 1

214

13.1.2 Block Diagram

Figure 13-1 shows a block diagram of the A/D converter.

Figure 13-1 Block Diagram of A/D Converter

/AN

Port

MPX

PMR0 (8b)

AMR (4b)

/AN

Reference voltage

REF

255

254

253

252

251

�

ADSR

Control logic

Chopper-type comparator

Successive approximation finds the input
voltage by changing a reference voltage
(V ).

REF

RESET
LPM (low-power mode)

Interrupt

Internal data bus

Control circuitry

(successive

approximation,

interrupt request, etc.)

One of 256 switches is selected by binary search.
The reference voltage value resulting from eight
comparisons is set in ADDR.
(The eighth value is equal to the analog input
voltage.)

The internal ladder resistance is 35 k to 40 k typ (approximately).
Upon reset and in low-power operation modes (sleep, watch, subactive,
or standby modes), the ladder resistance is disconnected from AV

by a switching transistor. The AV current at this time is a leakage current
Alcc of 1 A or less (approximate value).

�

Notation:
PMR0:
AMR:
ADSR:
ADRR:
IRRAD:
RESET:
LPM:

Port mode register 0
A/D mode register
A/D start register
A/D result register
A/D conversion end interrupt request flag (interrupt request register 3)
Signal set to 1 upon reset
Signal set to 1 in low-power modes

ADRR

216

13.1.3 Pin Configuration

Table 13-1 shows the A/D converter pin configuration.

Table 13-1 Pin Configuration

Name

Abbrev.

I/O

Function

Analog power supply pin

Input

Analog power supply and reference voltage

Analog ground pin

Input

Analog ground and reference voltage

Analog input pin 0

Input

Analog input channel 0

Analog input pin 1

Input

Analog input channel 1

Analog input pin 2

Input

Analog input channel 2

Analog input pin 3

Input

Analog input channel 3

Analog input pin 4

Input

Analog input channel 4

Analog input pin 5

Input

Analog input channel 5

Analog input pin 6

Input

Analog input channel 6

Analog input pin 7

Input

Analog input channel 7

13.1.4 Register Configuration

Table 13-2 shows the A/D converter register configuration.

Table 13-2 Register Configuration

Name

Abbrev.

R/W

Initial Value

Address

A/D mode register

AMR

R/W

H'78

H'FFBC

A/D start register

ADSR

R/W

H'7F

H'FFBE

A/D result register

ADRR

Not fixed

H'FFBD

Port mode register 0

PMR0

H'00

H'FFEF

217

13.2 Register Descriptions

13.2.1 A/D Result Register (ADRR)

Note:

Not fixed

The A/D result register (ADRR) is an 8-bit read-only register for holding the result of analog-to-
digital conversion.

ADRR can be read by the CPU at any time, but the ADRR value during A/D conversion is not
fixed.

After A/D conversion is complete, the conversion result is stored in ADRR as 8-bit data; this data
is held in ADRR until the next conversion operation starts.

ADRR is not cleared on reset.

13.2.2 A/D Mode Register (AMR)

AMR is an 8-bit read/write register for selecting the A/D conversion speed and analog input pin.

Writing to AMR should be done with the A/D start flag (ADSF) cleared to 0 in the A/D start
register (ADSR).

Upon reset, AMR is initialized to H'78.

Bit

Initial value

Read/Write

ADR7

ADR6

ADR5

ADR4

ADR3

ADR0

ADR2

ADR1

Bit

Initial value

Read/Write

AMR7

R/W

AMR0

R/W

AMR2

R/W

AMR1

R/W

218

Bit 7: Clock select (AMR7)

Bit 7 sets the A/D conversion speed.

Bit 7
AMR7

Conversion Period

= 2 MHz

= 4 MHz

62/

31 �s

14.8 �s

(initial value)

31/

15.5 �s

Notes: 1. Operation is not guaranteed if the conversion time is less than 14.8 �s. Set bit 7 for a

value of at least 14.8 �s.

2. A/D conversion starts after a value of 1 is written to ADSF. The conversion period starts

when the start flag is set and ends when it is reset upon completion of conversion. The
actual time during which sample and hold are repeated is called the conversion interval
(see figure 13-2).

Figure 13-2 Internal Operation of A/D Converter

State

Conversion interval

Conversion period (31 or 62 states)

Interrupt request flag

IRQ sampling
(CPU)

When conversion is complete, the start flag is reset and the interrupt request flag
is set. An interrupt is recognized by the CPU in the last instruction execution state,
and interrupt exception handling is executed after that instruction is completed.

Note: IRQ sampling:

MOV B.

Instruction
execution

WRITE

Start flag

219

13.2.4 Port Mode Register 0 (PMR0)

PMR0 is an 8-bit write-only register for designating whether each of the port 0 pins is used as a
general-purpose input pin or as an analog input channel to the A/D converter. Designation is
made separately for each pin.

Upon reset, PMR0 is initialized to H'00.

Bit n
ANn

Description

Pin P0

/AN

is used for general-purpose input.

(initial value)

Pin P0

/AN

is an analog input channel.

(n = 0 to 7)

13.3 Operation

The A/D converter operates by successive approximations, and yields its conversion result as 8-bit
data.

A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a
value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete.

The completion of conversion also sets bit IRRAD in interrupt request register 3 (IRR3) to 1. An
A/D conversion end interrupt is requested if bit IENAD in interrupt enable register 3 (IENR3) is
set to 1.

If the conversion time or input channel needs to be changed in the A/D mode register (AMR)
during A/D conversion, bit ADSF should first be cleared to 0, stopping the conversion operation,
in order to avoid misoperation.

13.4 Interrupts

When A/D conversion is complete (ADSF changes from 1 to 0), bit IRRAD in interrupt request
register 3 (IRR3) is set to 1.

A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt
enable register 3 (IENR3).

For further details see 3.2.2, Interrupts.

Bit

Initial value

Read/Write

AN7

AN6

AN5

AN4

AN3

AN0

AN2

AN1

222

13.5 Typical Use

An example of how the A/D converter can be used is given below, using channel 1 (AN

) as the

analog input channel. Figure 13-3 shows the operation timing for this example.

Bits AMR2 to AMR0 of the A/D mode register (AMR) are set to 001, and bits AN7 to AN0
of port mode register 0 (PMR0) are set to 00000010, making AN

the analog input channel.

Interrupt request is cleared by setting bit IRRAD to 0, A/D interrupts are enabled by setting
bit IENAD to 1, and A/D conversion is started by setting bit ADSF to 1.

When A/D conversion is complete, bit IRRAD is set to 1, and the A/D conversion results are
sent to the A/D result register (ADRR). At the same time ADSF is cleared to 0, and the A/D
converter goes to the idle state.

Bit IENAD = 1, so an A/D conversion end interrupt is requested.

The A/D interrupt handling routine starts.

The A/D conversion result is read and processed.

The A/D interrupt handling routine ends.

If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place.

Figures 13-4 and 13-5 show flow charts of procedures for using the A/D converter.

223

Section 14 Electrical Specifications

14.1 Absolute Maximum Ratings

Table 14-1 gives the absolute maximum ratings.

Table 14-1 Absolute Maximum Ratings

Item

Symbol

Rating

Unit

Notes

Supply voltage

�0.3 to +7.0

1, 2

Programming voltage

�0.3 to +14.0

1, 2, 3

Analog supply voltage

�0.3 to +7.0

1, 2

Analog input voltage

�0.3 to AV

+0.3

1, 2

Pin voltage (standard pins)

�0.3 to V

+0.3

1, 2, 4

Pin voltage (high-voltage pins)

�45 to V

+0.3

1, 2, 5

Operating temperature

�20 to +75

�C

1, 2

Storage temperature

stg

�55 to +125

�C

1, 2

Notes: 1. Permanent damage may occur to the chip if maximum ratings are exceeded. Normal

operation should be under the conditions specified in Electrical Characteristics.
Exceeding these values can result in incorrect operation and reduced reliability.

2. All voltages are referenced to V

3. Applies to the ZTATTM version.
4. Applies to standard-voltage pins.
5. Applies to high-voltage pins.

229

14.2 HD6473714 Electrical Characteristics

14.2.1 HD6473714 DC Characteristics

Table 14-2 gives the allowable current values of the HD6473714. Table 14-3 gives the DC
characteristics.

Table 14-2 Allowable Output Current Values

Conditions: V

= 4.0 to 5.5 V, V

= 0.0 V, T

= �20 to +75�C

Item

Symbol

Rating

Unit

Notes

Allowable input current (sink)

1, 2

Allowable output current (source)

�I

2, 3

Allowable output current (source)

�I

3, 4

Total allowable input current (sink)

Total allowable output current (source)

�

150

Notes: 1. Allowable input current means the maximum current that can flow from each I/O pin to

2. Applies to standard-voltage pins.
3. Allowable output current means the maximum current that can flow from V

to each I/O

pin.

4. Applies to high-voltage pins.
5. Total allowable input current means the sum of current that can flow at one time from all

I/O pins to V

6. Total allowable output current means the sum of current that can flow from V

to all I/O

pins.

230

Table 14-3 DC Characteristics

Conditions: Unless otherwise indicated, V

= 4.0 to 5.5 V, V

disp

= V

� 40 to V

= 0.0 V, T

= �20 to +75�C

Rating

Item

Symbol

Test Conditions

Min

Typ

Max

Unit

Notes

Input high

RES

0.8 V

+0.3

voltage

IRQ

, IRQ

IRQ

, IRQ

= 2.7 to 5.5 V

0.9 V

+0.3

SCK

, SCK

incl. subactive mode

, SI

EVENT

, UD

= 2.7 to 5.5 V

0.7 V

+0.3

incl. subactive mode

OSC

�0.5 --

+0.3

= 2.7 to 5.5 V

�0.3 --

+0.3

incl. subactive mode

to P0

= 2.7 to 5.5 V

0.7 V

+0.3

, P1

incl. subactive mode

to P1

to P9

to P4

= 2.7 to 5.5 V

0.7 V

+0.3

to P5

incl. subactive mode

to P6

to P7

Input low

RES

, �0.3

0.2

voltage

SCK

, SCK

IRQ

, IRQ

, V

= 2.7 to 5.5 V

�0.3

0.1 V

IRQ

, IRQ

incl. subactive mode

, SI

EVENT

, UD

= 2.7 to 5.5 V

�0.3

0.3 V

incl. subactive mode

OSC

�0.3

0.5

= 2.7 to 5.5 V

�0.3

0.3

incl. subactive mode

to P0

= 2.7 to 5.5 V

�0.3

0.3 V

, P1

incl. subactive mode

to P1

to P9

to P4

= 2.7 to 5.5 V

�40

0.3 V

to P5

incl. subactive mode

to P6

to P7

Note: Connect the TEST pin to V

Applicable
Pins

231

Table 14-3 DC Characteristics (cont)

Conditions: Unless otherwise indicated, V

= 4.0 to 5.5 V, V

disp

= V

� 40 to V

= 0.0 V, T

= �20 to +75�C

Rating

Item

Symbol

Test Conditions

Min

Typ

Max

Unit

Notes

�I

= 1.0 mA

�1.0 --

�I

= 0.5 mA

�0.5 --

= 2.7 to 5.5 V

�0.5 --

�I

= 0.3 mA

�I

= 15 mA

�3.0 --

�I

= 10 mA

�2.0 --

�I

= 4 mA

�1.0 --

= 2.7 to 5.5 V

�1.0 --

Reference

�I

= 4 mA

value

Output low V

= 4.0 to 5.5 V

0.4

voltage

= 1.6 mA

= 2.7 to 5.5 V

0.4

Reference

= 0.5 mA

value

to P4

Pull-down --

�37

to P5

resistance

to P6

150 k

; pull-down

to P7

voltage V

�40 V

Input |I

RES

= 0.0 to V

�A

leakage
current

Applicable
Pins

, P1

to P9

PWM, SO1,
SO

, SCK

SCK

, P1

to P9

PWM, SO

, SCK

SCK

Output high
voltage

to P4

to P5

to P6

to P7

232

Table 14-3 DC Characteristics (cont)

Conditions: Unless otherwise indicated, V

= 4.0 to 5.5 V, V

disp

= V

� 40 to V

= 0.0 V, T

= �20 to +75�C

Rating

Item

Symbol

Test Conditions

Min

Typ

Max

Unit

Notes

OPE

= 5 V,

OSC

= 8 MHz

= 5 V,

OSC

= 4 MHz

= 3 V,

OSC

= 4 MHz

RES

= 5 V,

OSC

= 8 MHz

= 5 V,

OSC

= 4 MHz

= 3 V,

1.5

OSC

= 4 MHz

SLEEP

= 5 V,

2.5

3.5

OSC

= 8 MHz

= 5 V,

1.5

2.0

OSC

= 4 MHz

= 3 V,

1.0

OSC

= 4 MHz

SUB

= 2.7 V

�A

Reference
value

�A

WATCH

3.2

�A

3.8

�A

Reference
value

�A

Power

STBY

32 kHz crystal

�A

dissipation

oscillator not used

in standby

= V

mode

Applicable
Pins

Power
dissipation
when CPU
operating in
active mode

Power
dissipation
during reset
in active
mode

Reference
value
1

Power
dissipation in
sleep mode

Power
dissipation in
subactive
mode

Power
dissipation in
watch mode

= 2.7 V

32 kHz crystal
oscillator used

= 5.0 V

32 kHz crystal
oscillator used

= 2.7 V

32 kHz crystal
oscillator used

= 5.0 V

32 kHz crystal
oscillator used

234

14.2.2 HD6473714 AC Characteristics

Table 14-4 gives the control signal timing of the HD6473714. Table 14-5 gives the serial interface
timing.

Table 14-4 Control Signal Timing

Conditions: Unless otherwise indicated, V

= 4.0 to 5.5 V, V

disp

= V

� 40 to V

= 0.0 V, T

= �20 to +75�C

Rating

Item

Symbol

Test Conditions

Min

Typ

Max

Unit

OSC

8.4

MHz

= 2.7 to 5.5 V

4.2

Clock cycle time

CYC

119

500

= 2.7 to 5.5 V

238

500

238

1000

= 2.7 to 5.5 V

476

1000

Subclock pulse

, X

= 2.7 to 5.5 V

32.768 --

kHz

generator
frequency

Subclock cycle

subcyc

, X

= 2.7 to 5.5 V

30.5

�s

time

Subactive

SUB

= 2.7 to 5.5 V

244.14 --

�s

instruction cycle
time

= 2.7 to 5.5 V

Oscillator t

, X

= 2.7 to 5.5 V

settling time

CPH

OSC

= 2.7 to 5.5 V

100

CPL

OSC

= 2.7 to 5.5 V

100

CPr

OSC

= 2.7 to 5.5 V

CPf

OSC

= 2.7 to 5.5 V

Applicable
Pins

Reference
Diagram

Figure
14-1

Clock pulse
generator
frequency

Instruction cycle
time

Oscillator settling
time (crystal
oscillator)

Oscillator settling
time (ceramic
oscillator)

External clock
pulse width (high)

External clock
pulse width (low)

External clock
rise time

External clock fall
time

OSC

236

Table 14-4 Control Signal Timing (cont)

Conditions: Unless otherwise indicated, V

= 4.0 to 5.5 V, V

disp

= V

� 40 to V

= 0.0 V, T

= �20 to +75�C

Rating

Item

Symbol

Test Conditions

Min

Typ

Max

Unit

RES

pin pulse

REL

RES

= 2.7 to 5.5 V

Figure

width (low)

14-2

IRQ

pin pulse

IRQ

, IRQ

, V

= 2.7 to 5.5 V

Figure

width (high)

IRQ

, IRQ

SUB

14-3

IRQ

pin pulse

IRQ

, IRQ

, V

= 2.7 to 5.5 V

width (low)

IRQ

, IRQ

SUB

EVENT

pin t

EVH

EVENT

= 2.7 to 5.5 V

Figure

pulse width (high)

14-4

EVENT

pin t

EVL

EVENT

= 2.7 to 5.5 V

pulse width (low)

UD pin minimum

UDH

= 2.7 to 5.5 V

Figure

high/low width

UDL

14-5

Table 14-5 Serial Interface Timing

Conditions: Unless otherwise indicated, V

= 4.0 to 5.5 V, V

disp

= V

� 40 to V

= 0.0 V, T

= �20 to +75�C

Rating

Item

Symbol

Test Conditions

Min

Typ

Max

Unit

Output serial

scyc

SCK

, V

= 2.7 to 5.5 V

Figure

clock cycle time

SCK

14-6

Output serial

SCKH

SCK

= 2.7 to 5.5 V

0.4

scyc

clock pulse width

SCK

(high)

Output serial

SCKL

SCK

= 2.7 to 5.5 V

0.4

scyc

clock pulse

SCK

width (low)

SCKr

= 2.7 to 5.5 V

SCKf

= 2.7 to 5.5 V

Input serial

scyc

= 2.7 to 5.5 V

clock cycle time

Input serial

SCKH

= 2.7 to 5.5 V

0.4

scyc

clock pulse
width (high)

Applicable
Pins

Reference
Diagram

Output serial
clock rise time

Output serial
clock fall time

SCK

Applicable
Pins

Reference
Diagram

237

Table 14-5 Serial Interface Timing (cont)

Conditions: Unless otherwise indicated, V

= 4.0 to 5.5 V, V

disp

= V

� 40 to V

= 0.0 V, T

= �20 to +75�C

Rating

Item

Symbol

Test Conditions

Min

Typ

Max

Unit

Input serial

SCKL

= 2.7 to 5.5 V

0.4

scyc

Figure

clock pulse

14-6

width (low)

SCKr

= 2.7 to 5.5 V

SCKf

= 2.7 to 5.5 V

dSO

, SO

200

= 2.7 to 5.5 V

350

sSI

, SI

230

= 2.7 to 5.5 V

470

hSI

, SI

230

= 2.7 to 5.5 V

470

Transfer pending

SCK2

SCK

When pin SCK

is 0.2

�s

Figure

time

input pin

14-7

When pin SCK

0.4

input pin
V

= 2.7 to 5.5 V

When pin SCK

is --

scyc

output pin
V

= 2.7 to 5.5 V

Transfer end

= 2.7 to 5.5 V

acknowledge
time

Applicable
Pins

Reference
Diagram

Input serial
clock rise time

Input serial
clock fall time

Serial output
data delay time

Serial input data
setup time

Serial input data
hold time

SCK

238

14.2.3 HD6473714 A/D Converter Characteristics

Table 14-6 gives the HD6473714 A/D converter characteristics.

Table 14-6 A/D Converter Characteristics

Conditions: Unless otherwise indicated, V

= 4.0 to 5.5 V, V

disp

= V

� 40 to V

= 0.0 V, T

= �20 to +75�C

Rating

Item

Symbol

Test Conditions

Min

Typ

Max

Unit

Notes

Analog AV

�0.3

+0.3

supply
voltage

Analog AV

to AN

input voltage

= 5 V

200

�A

STOP

Reset and power-

�A

down mode

Analog input C

AIN

to AN

capacitance

Allowable R

AIN

to AN

signal source
impedance

Resolution

Bit

Absolute V

= AV

= 5 V

�2.5

LSB

= AV

= --

�2.5

Reference

4.0 to 5.5 V

value

Conversion 31

15.5

14.8

�s

time

Applicable
Pins

Analog
supply
current

Absolute
accuracy

239

14.3 HD6433712, HD6433713 and HD6433714 Electrical Characteristics

14.3.1 HD6433712, HD6433713 and HD6433714 DC Characteristics

Table 14-7 gives the allowable current values of the HD6433712, HD6433713 and HD6433714.
Table 14-8 gives the DC characteristics.

Table 14-7 Allowable Output Current Values

Conditions: V

= 4.0 to 5.5 V, V

= 0.0 V, T

= �20 to +75�C

Item

Symbol

Rating

Unit

Notes

Allowable input current (sink)

1, 2

Allowable output current (source)

�I

2, 3

Allowable output current (source)

�I

3, 4

Total allowable input current (sink)

Total allowable output current (source)

�

150

Total allowable output current to V

disp

�

Notes: 1. Allowable input current means the maximum current that can flow from each I/O pin to

2. Applies to standard-voltage pins.
3. Allowable output current means the maximum current that can flow from V

to each I/O

pin.

4. Applies to high-voltage pins.
5. Total allowable input current means the sum of current that can flow at one time from all

I/O pins to V

6. Total allowable output current means the sum of current that can flow from V

to all I/O

pins.

7. Total allowable output current to V

disp

is the sum of current that can flow from all I/O pins

to V

disp

240

Table 14-8 DC Characteristics

Conditions: Unless otherwise indicated, V

= 4.0 to 5.5 V, V

disp

= V

� 40 to V

= 0.0 V, T

= �20 to +75�C

Rating

Item

Symbol

Test Conditions

Min

Typ

Max

Unit

Notes

Input high

RES

0.8 V

+0.3

voltage

IRQ

, IRQ

IRQ

, IRQ

= 2.5 to 5.5 V

0.9 V

+0.3

SCK

, SCK

incl. subactive mode

, SI

EVENT

, UD

= 2.5 to 5.5 V

0.7 V

+0.3

incl. subactive mode

OSC

�0.5 --

+0.3

= 2.5 to 5.5 V

�0.3 --

+0.3

incl. subactive mode

to P0

= 2.5 to 5.5 V

0.7 V

+0.3

, P1

incl. subactive mode

to P1

to P9

to P4

= 2.5 to 5.5 V

0.7 V

+0.3

to P5

incl. subactive mode

to P6

to P7

Input low

RES

, �0.3

0.2

voltage

SCK

, SCK

IRQ

, IRQ

, V

= 2.5 to 5.5 V

�0.3

0.1 V

IRQ

, IRQ

incl. subactive mode

, SI

EVENT

, UD

= 2.5 to 5.5 V

�0.3

0.3 V

incl. subactive mode

OSC

�0.3

0.5

= 2.5 to 5.5 V

�0.3

0.3

incl. subactive mode

to P0

= 2.5 to 5.5 V

�0.3

0.3 V

, P1

incl. subactive mode

to P1

to P9

to P4

= 2.5 to 5.5 V

�40

0.3 V

to P5

incl. subactive mode

to P6

to P7

Note: Connect the TEST pin to V

Applicable
Pins

241

Table 14-8 DC Characteristics (cont)

Conditions: Unless otherwise indicated, V

= 4.0 to 5.5 V, V

disp

= V

� 40 to V

= 0.0 V, T

= �20 to +75�C

Rating

Item

Symbol

Test Conditions

Min

Typ

Max

Unit

Notes

�I

= 1.0 mA

�1.0 --

�I

= 0.5 mA

�0.5 --

= 2.7 to 5.5 V

�0.5 --

�I

= 0.3 mA

�I

= 15 mA

�3.0 --

�I

= 10 mA

�2.0 --

�I

= 4 mA

�1.0 --

= 2.7 to 5.5 V

�1.0 --

Reference

�I

= 4 mA

value

Output low V

, P1

= 4.0 to 5.5 V

0.4

voltage

, P1

= 1.6 mA

to P9

PWM, SO

= 2.7 to 5.5 V

0.4

Reference

, SCK

= 0.5 mA

value

SCK

disp

= V

�40 V

�37

With
MOS
pull-down

Pull-down --

�37

resistance
150 k

; pull-down

voltage V

�40 V

Input |I

RES

Mask ROM version:

�A

leakage

= 0.0 to V

current

, P1

to P9

PWM, SO1,
SO

, SCK

SCK

Applicable
Pins

Output high
voltage

to P4

to P5

to P6

to P7

to P4

to P5

to P6

to P7

242

Table 14-8 DC Characteristics (cont)

Conditions: Unless otherwise indicated, V

= 4.0 to 5.5 V, V

disp

= V

� 40 to V

= 0.0 V, T

= �20 to +75�C

Rating

Item

Symbol

Test Conditions

Min

Typ

Max

Unit

Notes

I/O leakage |I

TEST

= 0.0 to V

�A

current

SCK

, SCK

, SI

IRQ

, IRQ

IRQ

, IRQ

EVENT

, UD

OSC

to P0

, P1

to P1

to P9

to P4

= V

�40 --

�A

Not

to P5

to V

including

to P6

pins with

to P7

MOS

pull-down

�I

= 5 V, V

= 0 V

300

�A

= 2.7 V,

Reference

= 0 V

value

disp

= V

�36

120

800

�A

= V

disp

= V

�18

280

Reference

= V

value

Input C

Input pins

f = 1 MHz, V

= 0 V

capaci-

other than

= 25�C

tance

power supply
pins and I/O
pins

Applicable
Pins

, P1

to P1

to P9

to P4

to P5

to P6

to P7

Pull-up
MOS
current

Pull-down
MOS
current

243

Table 14-8 DC Characteristics (cont)

Conditions: Unless otherwise indicated, V

= 4.0 to 5.5 V, V

disp

= V

� 40 to V

= 0.0 V, T

= �20 to +75�C

Rating

Item

Symbol

Test Conditions

Min

Typ

Max

Unit

Notes

OPE

= 5 V,

OSC

= 8 MHZ

= 5 V,

OSC

= 4 MHz

= 3 V,

OSC

= 4 MHz

RES

= 5 V,

OSC

= 8 MHz

= 5 V,

2.5

OSC

= 4 MHz

= 3 V,

1.3

OSC

= 4 MHz

SLEEP

= 5 V,

OSC

= 8 MHz

= 5 V,

1.5

OSC

= 4 MHz

= 3 V,

0.6

OSC

= 4 MHz

SUB

�A

Reference
value

�A

WATCH

2.2

�A

2.8

�A

Reference
value

�A

Power

STBY

32 kHz crystal

�A

dissipation

oscillator not used

in standby

= V

mode

Applicable
Pins

Power
dissipation
when CPU
operating in
active mode

Power
dissipation
during reset
in active
mode

Reference
value
1

Power
dissipation in
sleep mode

Power
dissipation in
subactive
mode

Power
dissipation in
watch mode

= 2.5 V

32 kHz crystal
oscillator used

= 5.0 V

32 kHz crystal
oscillator used

= 2.5 V

32 kHz crystal
oscillator used

= 5.0 V

32 kHz crystal
oscillator used

244

14.3.2 HD6433712, HD6433713 and HD6433714 AC Characteristics

Table 14-9 gives the control signal timing of the HD6433712, HD6433713 and HD6433714.
Table 14-10 gives the serial interface timing.

Table 14-9 Control Signal Timing

Conditions: Unless otherwise indicated, V

= 4.0 to 5.5 V, V

disp

= V

� 40 to V

= 0.0 V, T

= �20 to +75�C

Rating

Item

Symbol

Test Conditions

Min

Typ

Max

Unit

OSC

8.4

MHz

= 2.7 to 5.5 V

4.2

Clock cycle time

CYC

119

500

= 2.7 to 5.5 V

238

500

238

1000

= 2.7 to 5.5 V

476

1000

Subclock pulse

, X

= 2.5 to 5.5 V

32.768 --

kHz

generator
frequency

Subclock cycle

subcyc

, X

= 2.5 to 5.5 V

30.5

�s

time

Subactive

SUB

= 2.5 to 5.5 V

244.14 --

�s

instruction cycle
time

= 2.7 to 5.5 V

Oscillator t

, X

= 2.7 to 5.5 V

settling time

CPH

OSC

= 2.7 to 5.5 V

100

CPL

OSC

= 2.7 to 5.5 V

100

CPr

OSC

= 2.7 to 5.5 V

CPf

OSC

= 2.7 to 5.5 V

Applicable
Pins

Reference
Diagram

Figure
14-1

Clock pulse
generator
frequency

Instruction cycle
time

Oscillator settling
time (crystal
oscillator)

Oscillator settling
time (ceramic
oscillator)

External clock
pulse width (high)

External clock
pulse width (low)

External clock
rise time

External clock fall
time

OSC

246

Table 14-9 Control Signal Timing (cont)

Conditions: Unless otherwise indicated, V

= 4.0 to 5.5 V, V

disp

= V

� 40 to V

= 0.0 V, T

= �20 to +75�C

Rating

Item

Symbol

Test Conditions

Min

Typ

Max

Unit

RES

pin pulse

REL

RES

= 2.7 to 5.5 V

Figure

width (low)

14-2

IRQ

pin pulse

IRQ

, IRQ

= 2.7 to 5.5 V

Figure

width (high)

IRQ

, IRQ

SUB

14-3

IRQ

pin pulse

IRQ

, IRQ

= 2.7 to 5.5 V

width (low)

IRQ

, IRQ

SUB

EVENT

pin t

EVH

EVENT

= 2.7 to 5.5 V

Figure

pulse width (high)

14-4

EVENT

pin t

EVL

EVENT

= 2.7 to 5.5 V

pulse width (low)

UD pin minimum

UDH

= 2.7 to 5.5 V

Figure

high/low width

UDL

14-5

Table 14-10 Serial Interface Timing

Conditions: Unless otherwise indicated, V

= 4.0 to 5.5 V, V

disp

= V

� 40 to V

= 0.0 V, T

= �20 to +75�C

Rating

Item

Symbol

Test Conditions

Min

Typ

Max

Unit

Output serial

scyc

SCK

, V

= 2.7 to 5.5 V

Figure

clock cycle timing

SCK

14-6

Output serial

SCKH

SCK

= 2.7 to 5.5 V

0.4

scyc

clock pulse width

SCK

(high)

Output serial

SCKL

SCK

= 2.7 to 5.5 V

0.4

scyc

clock pulse

SCK

width (low)

SCKr

= 2.7 to 5.5 V

SCKf

= 2.7 to 5.5 V

Input serial

scyc

= 2.7 to 5.5 V

clock cycle timing

Input serial

SCKH

= 2.7 to 5.5 V

0.4

scyc

clock pulse
width (high)

Applicable
Pins

Reference
Diagram

Applicable
Pins

Reference
Diagram

Output serial
clock rise time

Output serial
clock fall time

SCK

247

Table 14-10 Serial Interface Timing (cont)

Conditions: Unless otherwise indicated, V

= 4.0 to 5.5 V, V

disp

= V

� 40 to V

= 0.0 V, T

= �20 to +75�C

Rating

Item

Symbol

Test Conditions

Min

Typ

Max

Unit

Input serial

SCKL

= 2.7 to 5.5 V

0.4

scyc

Figure

clock pulse

14-6

width (low)

SCKr

= 2.7 to 5.5 V

SCKf

= 2.7 to 5.5 V

dSO

, SO

200

= 2.7 to 5.5 V

350

sSI

, SI

230

= 2.7 to 5.5 V

470

hSI

, SI

230

= 2.7 to 5.5 V

470

Transfer pending

SCK2

SCK

When pin SCK

is 0.2

�s

Figure

time

input pin

14-7

When pin SCK

0.4

input pin
V

= 2.7 to 5.5 V

When pin SCK

is --

scyc

output pin
V

= 2.7 to 5.5 V

Transfer end

= 2.7 to 5.5 V

acknowledge
time

Applicable
Pins

Reference
Diagram

Input serial
clock rise time

Input serial
clock fall time

Serial output
data delay time

Serial input data
setup time

Serial input data
hold time

SCK

248

14.3.3 HD6433712, HD6433713 and HD6433714 A/D Converter Characteristics

Table 14-11 gives the HD6433712, HD6433713 and HD6433714 A/D converter characteristics.

Table 14-11 A/D Converter Characteristics

Conditions: Unless otherwise indicated, V

= 4.0 to 5.5 V, V

disp

= V

� 40 to V

= 0.0 V, T

= �20 to +75�C

Rating

Item

Symbol

Test Conditions

Min

Typ

Max

Unit

Notes

Analog AV

�0.3

+0.3

supply
voltage

Analog AV

to AN

input voltage

= 5 V

200

�A

STOP

Reset and power-

�A

down mode

Analog input C

AIN

to AN

capacitance

Allowable R

AIN

to AN

signal source
impedance

Resolution

Bit

= AV

= 5 V

�2.5

LSB

= AV

= --

�2.5

Reference

4.0 to 5.5 V

value

Conversion 31

15.5

14.8

�s

time

Applicable
Pins

Analog
supply
current

Absolute
accuracy

249

14.5 Differences in Electrical Characteristics between HD6473714 and

HD6433712/HD6433713/HD6433714

Table 14-12 shows the difference in electrical characteristics between the HD6473714 and
HD6433712/HD6433713/HD6433714.

Table 14-12

Differences in Electrical Characteristics between HD6473714 and
HD6433712/HD6433713/HD6433714

Mask ROM Version ZTATTM Version

Item

Symbol

Test Conditions

Min

Typ

Max

Min

Typ

Max Unit

Operation

2.5

5.5

2.7

5.5

range in
subactive
mode

Input leakage |I

RES

�A

current

Input C

P16/

EVENT

capacitance

P17/V

disp

RES

OPE

= 5 V,

OSC

= 8 MHz

= 5 V,

OSC

= 4 MHz

= 3 V,

OSC

= 4 MHz

RES

= 5 V,

OSC

= 8 MHz

= 5 V,

2.5

OSC

= 4 MHz

= 3 V,

1.3

1.5

OSC

= 4 MHz

SLEEP

= 5 V,

2.5

3.5

OSC

= 8 MHz

= 5 V,

1.5

OSC

= 4 MHz

= 3 V,

0.6

OSC

= 4 MHz

Applicable
Pins

Power
dissipation
when CPU
operating in
active mode

Power
dissipation
during reset
in active
mode

Power
dissipation in
sleep mode

253

Table 14-12

Differences in Electrical Characteristics between HD6473714 and
HD6433713/HD6433714 (cont)

Mask ROM Version ZTATTM Version

Item

Symbol

Test Conditions

Min

Typ

Max

Min

Typ

Max Unit

SUB

= 2.5 V

�A

(no bypass capacitor)

= 2.5 V

(47 �F bypass
capacitor)

= 2.7 V

(no bypass capacitor)

= 2.7 V

(47 �F bypass
capacitor)

= 5 V

(no bypass capacitor)

= 5 V

(47 �F bypass

capacitor)

WATCH

= 2.5 V

2.2

�A

(no bypass capacitor)

= 2.5 V

2.8

(47 �F bypass

capacitor)

= 2.7 V

3.2

(no bypass capacitor)

= 2.7 V

3.8

(47 �F bypass
capacitor)

= 5 V

(no bypass capacitor)

= 5 V

(47 �F bypass

capacitor)

STBY

�A

Applicable
Pins

Power
dissipation
in subactive
mode

Power
dissipation
in watch
mode

Power
dissipation
in standby
mode

254

A.3 Number of States Required for Execution

Table A-2 Instruction Set

Mnemonic

Operation

H N Z V C

MOV.B #xx:8, Rd

B #xx:8

Rd8

-- --

�

0 -- 2

MOV.B Rs, Rd

B Rs8

Rd8

-- --

�

0 -- 2

MOV.B @Rs, Rd

B @Rs16

Rd8

-- --

�

0 -- 4

MOV.B @(d:16, Rs), Rd

B @(d:16, Rs16)

Rd8

-- --

�

0 -- 6

MOV.B @Rs+, Rd

B @Rs16

Rd8

-- --

�

0 -- 6

Rs16+1

Rs16

MOV.B @aa:8, Rd

B @aa:8

Rd8

-- --

�

0 -- 4

MOV.B @aa:16, Rd

B @aa:16

Rd8

-- --

�

0 -- 6

MOV.B Rs, @Rd

B Rs8

@Rd16

-- --

�

0 -- 4

MOV.B Rs, @(d:16, Rd)

B Rs8

@(d:16, Rd16)

-- --

�

0 -- 6

MOV.B Rs, @--Rd

B Rd16�1

Rd16

-- --

�

0 -- 6

Rs8

@Rd16

MOV.B Rs, @aa:8

B Rs8

@aa:8

-- --

�

0 -- 4

MOV.B Rs, @aa:16

B Rs8

@aa:16

-- --

�

0 -- 6

MOV.W #xx:16, Rd

W #xx:16

-- --

�

0 -- 4

MOV.W Rs, Rd

W Rs16

Rd16

-- --

�

0 -- 2

MOV.W @Rs, Rd

W @Rs16

Rd16

-- --

�

0 -- 4

MOV.W @(d:16, Rs), Rd

W @(d:16, Rs16)

Rd16

-- --

�

0 -- 6

MOV.W @Rs+, Rd

W @Rs16

Rd16

-- --

�

0 -- 6

Rs16+2

Rs16

MOV.W @aa:16, Rd

W @aa:16

Rd16

-- --

�

0 -- 6

MOV.W Rs, @Rd

W Rs16

@Rd16

-- --

�

0 -- 4

MOV.W Rs, @(d:16, Rd)

W Rs16

@(d:16, Rd16)

-- --

�

0 -- 6

MOV.W Rs, @--Rd

W Rd16�2

Rd16

-- --

�

0 -- 6

Rs16

@Rd16

MOV.W Rs, @aa:16

W Rs16

@aa:16

-- --

�

0 -- 6

POP Rd

W @SP

Rd16

-- --

�

0 -- 6

SP+2

PUSH Rs

W SP�2

-- --

�

0 -- 6

Rs16

@SP

#xx:8/16

@Rn

@(d:16, Rn)

@�Rn/@Rn+

@aa:8/16

@(d:8, PC)

@@aa

No. of States

Addressing Mode/

Instruction Length (bytes)

Condition Code

Operand Size

258

Table A-2 Instruction Set (cont)

Mnemonic

Operation

H N Z V C

EEPMOV

-- if R4L

0 then

4 -- -- -- -- -- --

Repeat @R5

@R6

R5+1

R6+1

R4L�1

R4L

Until R4L=0

else next

ADD.B #xx:8, Rd

B Rd8+#xx:8

Rd8

�

ADD.B Rs, Rd

B Rd8+Rs8

Rd8

�

ADD.W Rs, Rd

W Rd16+Rs16

Rd16

�

ADDX.B #xx:8, Rd

B Rd8+#xx:8 +C

Rd8

�

� �

�

ADDX.B Rs, Rd

B Rd8+Rs8 +C

Rd8

�

� �

�

ADDS.W #1, Rd

W Rd16+1

Rd16

-- -- -- -- -- -- 2

ADDS.W #2, Rd

W Rd16+2

Rd16

-- -- -- -- -- -- 2

INC.B Rd

B Rd8+1

Rd8

-- --

�

-- 2

DAA.B Rd

B Rd8 decimal adjust

Rd8

�

SUB.B Rs, Rd

B Rd8�Rs8

Rd8

�

SUB.W Rs, Rd

W Rd16�Rs16

Rd16

�

SUBX.B #xx:8, Rd

B Rd8�#xx:8�C

Rd8

�

� �

�

SUBX.B Rs, Rd

B Rd8�Rs8�C

Rd8

�

� �

�

SUBS.W #1, Rd

W Rd16�1

Rd16

-- -- -- -- -- -- 2

SUBS.W #2, Rd

W Rd16�2

Rd16

-- -- -- -- -- -- 2

DEC.B Rd

B Rd8�1

Rd8

-- --

�

-- 2

DAS.B Rd

B Rd8 decimal adjust

Rd8

�

-- 2

NEG.B Rd

B 0�Rd

�

CMP.B #xx:8, Rd

B Rd8�#xx:8

�

CMP.B Rs, Rd

B Rd8�Rs8

�

CMP.W Rs, Rd

W Rd16�Rs16

�

#xx:8/16

@Rn

@(d:16, Rn)

@�Rn/@Rn+

@aa:8/16

@(d:8, PC)

@@aa

No. of States

Addressing Mode/

Instruction Length (bytes)

Condition Code

Operand Size

259

Table A-2 Instruction Set (cont)

Mnemonic

Operation

H N Z V C

MULXU.B Rs, Rd

B Rd8

�

Rs8

Rd16

-- -- -- -- -- -- 14

DIVXU.B Rs, Rd

B Rd16

�

Rs8

Rd16

-- --

-- -- 14

(RdH: remainder,
RdL: quotient)

AND.B #xx:8, Rd

B Rd8

#xx:8

Rd8

-- --

�

0 -- 2

AND.B Rs, Rd

B Rd8

Rs8

Rd8

-- --

�

0 -- 2

OR.B #xx:8, Rd

B Rd8

#xx:8

Rd8

-- --

�

0 -- 2

OR.B Rs, Rd

B Rd8

Rs8

Rd8

-- --

�

0 -- 2

XOR.B #xx:8, Rd

B Rd8

#xx:8

Rd8

-- --

�

0 -- 2

XOR.B Rs, Rd

B Rd8

Rs8

Rd8

-- --

�

0 -- 2

NOT.B Rd

B Rd

-- --

�

0 -- 2

SHAL.B Rd

-- --

�

SHAR.B Rd

-- --

�

SHLL.B Rd

-- --

�

SHLR.B Rd

-- -- 0

�

ROTXL.B Rd

-- --

�

ROTXR.B Rd

-- --

�

#xx:8/16

@Rn

@(d:16, Rn)

@�Rn/@Rn+

@aa:8/16

@(d:8, PC)

@@aa

No. of States

Addressing Mode/

Instruction Length (bytes)

Condition Code

Operand Size

260

Table A-2 Instruction Set (cont)

Mnemonic

Operation

H N Z V C

ROTL.B Rd

-- --

�

ROTR.B Rd

-- --

�

BSET #xx:3, Rd

B (#xx:3 of Rd8)

-- -- -- -- -- -- 2

BSET #xx:3, @Rd

B (#xx:3 of @Rd16)

-- -- -- -- -- -- 8

BSET #xx:3, @aa:8

B (#xx:3 of @aa:8)

-- -- -- -- -- -- 8

BSET Rn, Rd

B (Rn8 of Rd8)

-- -- -- -- -- -- 2

BSET Rn, @Rd

B (Rn8 of @Rd16)

-- -- -- -- -- -- 8

BSET Rn, @aa:8

B (Rn8 of @aa:8)

-- -- -- -- -- -- 8

BCLR #xx:3, Rd

B (#xx:3 of Rd8)

-- -- -- -- -- -- 2

BCLR #xx:3, @Rd

B (#xx:3 of @Rd16)

-- -- -- -- -- -- 8

BCLR #xx:3, @aa:8

B (#xx:3 of @aa:8)

-- -- -- -- -- -- 8

BCLR Rn, Rd

B (Rn8 of Rd8)

-- -- -- -- -- -- 2

BCLR Rn, @Rd

B (Rn8 of @Rd16)

-- -- -- -- -- -- 8

BCLR Rn, @aa:8

B (Rn8 of @aa:8)

-- -- -- -- -- -- 8

BNOT #xx:3, Rd

B (#xx:3 of Rd8)

-- -- -- -- -- -- 2

(#xx:3 of Rd8)

BNOT #xx:3, @Rd

B (#xx:3 of @Rd16)

-- -- -- -- -- -- 8

(#xx:3 of @Rd16)

BNOT #xx:3, @aa:8

B (#xx:3 of @aa:8)

-- -- -- -- -- -- 8

(#xx:3 of @aa:8)

BNOT Rn, Rd

B (Rn8 of Rd8)

-- -- -- -- -- -- 2

(Rn8 of Rd8)

BNOT Rn, @Rd

B (Rn8 of @Rd16)

-- -- -- -- -- -- 8

(Rn8 of @Rd16)

BNOT Rn, @aa:8

B (Rn8 of @aa:8)

-- -- -- -- -- -- 8

(Rn8 of @aa:8)

#xx:8/16

@Rn

@(d:16, Rn)

@�Rn/@Rn+

@aa:8/16

@(d:8, PC)

@@aa

No. of States

Addressing Mode/

Instruction Length (bytes)

Condition Code

Operand Size

261

Table A-2 Instruction Set (cont)

Mnemonic

Operation

H N Z V C

BTST #xx:3, Rd

B (#xx:3 of Rd8)

-- -- --

�

-- -- 2

BTST #xx:3, @Rd

B (#xx:3 of @Rd16)

-- -- --

�

-- -- 6

BTST #xx:3, @aa:8

B (#xx:3 of @aa:8)

-- -- --

�

-- -- 6

BTST Rn, Rd

B (Rn8 of Rd8)

-- -- --

�

-- -- 2

BTST Rn, @Rd

B (Rn8 of @Rd16)

-- -- --

�

-- -- 6

BTST Rn, @aa:8

B (Rn8 of @aa:8)

-- -- --

�

-- -- 6

BLD #xx:3, Rd

B (#xx:3 of Rd8)

-- -- -- -- --

�

BLD #xx:3, @Rd

B (#xx:3 of @Rd16)

-- -- -- -- --

�

BLD #xx:3, @aa:8

B (#xx:3 of @aa:8)

-- -- -- -- --

�

BILD #xx:3, Rd

B (#xx:3 of Rd8)

-- -- -- -- --

�

BILD #xx:3, @Rd

B (#xx:3 of @Rd16)

-- -- -- -- --

�

BILD #xx:3, @aa:8

B (#xx:3 of @aa:8)

-- -- -- -- --

�

BST #xx:3, Rd

B C

(#xx:3 of Rd8)

-- -- -- -- -- -- 2

BST #xx:3, @Rd

B C

(#xx:3 of @Rd16)

-- -- -- -- -- -- 8

BST #xx:3, @aa:8

B C

(#xx:3 of @aa:8)

-- -- -- -- -- -- 8

BIST #xx:3, Rd

B C

(#xx:3 of Rd8)

-- -- -- -- -- -- 2

BIST #xx:3, @Rd

B C

(#xx:3 of @Rd16)

-- -- -- -- -- -- 8

BIST #xx:3, @aa:8

B C

(#xx:3 of @aa:8)

-- -- -- -- -- -- 8

BAND #xx:3, Rd

B C

(#xx:3 of Rd8)

-- -- -- -- --

�

BAND #xx:3, @Rd

B C

(#xx:3 of @Rd16)

-- -- -- -- --

�

BAND #xx:3, @aa:8

B C

(#xx:3 of @aa:8)

-- -- -- -- --

�

BIAND #xx:3, Rd

B C

(#xx:3 of Rd8)

-- -- -- -- --

�

BIAND #xx:3, @Rd

B C

(#xx:3 of @Rd16)

-- -- -- -- --

�

BIAND #xx:3, @aa:8

B C

(#xx:3 of @aa:8)

-- -- -- -- --

�

BOR #xx:3, Rd

B C

(#xx:3 of Rd8)

-- -- -- -- --

�

BOR #xx:3, @Rd

B C

(#xx:3 of @Rd16)

-- -- -- -- --

�

BOR #xx:3, @aa:8

B C

(#xx:3 of @aa:8)

-- -- -- -- --

�

BIOR #xx:3, Rd

B C

(#xx:3 of Rd8)

-- -- -- -- --

�

BIOR #xx:3, @Rd

B C

(#xx:3 of @Rd16)

-- -- -- -- --

�

#xx:8/16

@Rn

@(d:16, Rn)

@�Rn/@Rn+

@aa:8/16

@(d:8, PC)

@@aa

No. of States

Addressing Mode/

Instruction Length (bytes)

Condition Code

Operand Size

262

Table A-2 Instruction Set (cont)

Mnemonic

Operation

H N Z V C

BIOR #xx:3, @aa:8

B C

(#xx:3 of @aa:8)

-- -- -- -- --

�

BXOR #xx:3, Rd

B C

(#xx:3 of Rd8)

-- -- -- -- --

�

BXOR #xx:3, @Rd

B C

(#xx:3 of @Rd16)

-- -- -- -- --

�

BXOR #xx:3, @aa:8

B C

(#xx:3 of @aa:8)

-- -- -- -- --

�

BIXOR #xx:3, Rd

B C

(#xx:3 of Rd8)

-- -- -- -- --

�

BIXOR #xx:3, @Rd

B C

(#xx:3 of @Rd16)

-- -- -- -- --

�

BIXOR #xx:3, @aa:8

B C

(#xx:3 of @aa:8)

-- -- -- -- --

�

BRA d:8 (BT d:8)

-- PC

PC+d:8

-- -- -- -- -- -- 4

BRN d:8 (BF d:8)

-- PC

PC+2

-- -- -- -- -- -- 4

BHI d:8

Z = 0

-- -- -- -- -- -- 4

BLS d:8

Z = 1

-- -- -- -- -- -- 4

BCC d:8 (BHS d:8)

C = 0

-- -- -- -- -- -- 4

BCS d:8 (BLO d:8)

C = 1

-- -- -- -- -- -- 4

BNE d:8

Z = 0

-- -- -- -- -- -- 4

BEQ d:8

Z = 1

-- -- -- -- -- -- 4

BVC d:8

V = 0

-- -- -- -- -- -- 4

BVS d:8

V = 1

-- -- -- -- -- -- 4

BPL d:8

N = 0

-- -- -- -- -- -- 4

BMI d:8

N = 1

-- -- -- -- -- -- 4

BGE d:8

V = 0

-- -- -- -- -- -- 4

BLT d:8

V = 1

-- -- -- -- -- -- 4

BGT d:8

V) = 0

-- -- -- -- -- -- 4

BLE d:8

V) = 1

-- -- -- -- -- -- 4

JMP @Rn

-- PC

Rn16

-- -- -- -- -- -- 4

JMP @aa:16

-- PC

aa:16

-- -- -- -- -- -- 6

JMP @@aa:8

-- PC

@aa:8

-- -- -- -- -- -- 8

BSR d:8

-- SP�2

-- -- -- -- -- -- 6

@SP

PC+d:8

#xx:8/16

@Rn

@(d:16, Rn)

@�Rn/@Rn+

@aa:8/16

@(d:8, PC)

@@aa

No. of States

Addressing Mode/

Instruction Length (bytes)

Condition Code

Operand Size

If
condition
is true
then
PC

PC+d:8
else next;

Branching

Condition

263

Table A-2 Instruction Set (cont)

Mnemonic

Operation

H N Z V C

JSR @Rn

-- SP�2

-- -- -- -- -- -- 6

@SP

Rn16

JSR @aa:16

-- SP�2

-- -- -- -- -- -- 8

@SP

aa:16

JSR @@aa:8

SP�2

-- -- -- -- -- -- 8

@SP

@aa:8

RTS

-- PC

@SP

2 -- -- -- -- -- -- 8

SP+2

RTE

-- CCR

@SP

�

SP+2

@SP

SP+2

SLEEP

-- Transit to sleep mode.

2 -- -- -- -- -- -- 2

LDC #xx:8, CCR

B #xx:8

CCR

�

LDC Rs, CCR

B Rs8

CCR

�

STC CCR, Rd

B CCR

Rd8

-- -- -- -- -- -- 2

ANDC #xx:8, CCR

B CCR

#xx:8

CCR

�

ORC #xx:8, CCR

B CCR

#xx:8

CCR

�

XORC #xx:8, CCR

B CCR

#xx:8

CCR

�

NOP

-- PC

PC+2

2 -- -- -- -- -- -- 2

Notes:

Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0.

If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0.

Set to 1 if decimal adjustment produces a carry; otherwise cleared to 0.

The number of states required for execution is 4n+9 (n = value of R4L).

Set to 1 if the divisor is negative; otherwise cleared to 0.

Set to 1 if the divisor is zero; otherwise cleared to 0.

#xx:8/16

@Rn

@(d:16, Rn)

@�Rn/@Rn+

@aa:8/16

@(d:8, PC)

@@aa

No. of States

Addressing Mode/

Instruction Length (bytes)

Condition Code

Operand Size

264

Appendix B On-Chip Registers

B.1 On-Chip Registers (1)

Bit Names

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

H'A0

STAR

STA4

STA3

STA2

STA1

STA0

SCI2

H'A1

EDAR

EDA4

EDA3

EDA2

EDA1

EDA0

H'A2

SCR2

I/O

GAP2

GAP1

PS1

PS0

H'A3

STSR

SO2 OVR

GIT

STF

LAST
BIT

H'A4

Not used

to
H'AF

H'B0

SMR1

SMR16

SMR15

SMR14

SMR13

SMR12

SMR11

SMR10

SCI1

H'B1

SDRU1

SDRU17 SDRU16 SDRU15 SDRU14 SDRU13 SDRU12 SDRU11 SDRU10

H'B2

SDRL1

SDRL17 SDRL16 SDRL15 SDRL14 SDRL13 SDRL12 SDRL11 SDRL10

H'B3

SPR1

SO1

LAST
BIT

H'B4

H'B5

H'B6

H'B7

H'B8

H'B9

VFSR

VFLAG

KSE

SR4

SR3

SR2

SR1

SR0

H'BA VFDR

FLMO

DM2

DM1

DM0

DR3

DR2

DR1

DR0

H'BB DBR

VFDE

DISP

DBR3

DBR2

DBR1

DBR0

H'BC AMR

AMR7

AMR2

AMR1

AMR0

H'BD ADRR

ADR7

ADR6

ADR5

ADR4

ADR3

ADR2

ADR1

ADR0

H'BE ADSR

ADSF

H'BF

Notation: SCI1: Serial communication interface 1

SCI2: Serial communication interface 2

Addr.
(Last Register

Module

Byte) Name

Name

VFD
con-
troller/
driver

A/D
con-
verter

265

B.1 On-Chip Registers (1) (cont)

Bit Names

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

H'C0

TMA

TMA3

TMA2

TMA1

TMA0

Timer A

H'C1

TCA

TCA7

TCA6

TCA5

TCA4

TCA3

TCA2

TCA1

TCA0

H'C2

TMB

TMB7

TMB2

TMB1

TMB0

Timer B

H'C3

TLB/TCB

TLB7/

TLB6/

TLB5/

TLB4/

TLB3/

TLB2/

TLB1/

TLB0/

TCB7

TCB6

TCB5

TCB4

TCB3

TCB2

TCB1

TCB0

H'C4

TMC

TMC7

TMC6

TMC5

TMC2

TMC1

TMC0

Timer C

H'C5

TLC/TCC

TLC7/

TLC6/

TLC5/

TLC4/

TLC3/

TLC2/

TLC1/

TLC0/

TCC7

TCC6

TCC5

TCC4

TCC3

TCC2

TCC1

TCC0

H'C6

TMD

CLR

EDG

Timer D

H'C7

TCD

TCD7

TCD6

TCD5

TCD4

TCD3

TCD2

TCD1

TCD0

H'C8

TME

TME7

TME2

TME1

TME0

Timer E

H'C9

TLE/TCE

TLE7/

TLE6/

TLE5/

TLE4/

TLE3/

TLE2/

TLE1/

TLE0/

TCE7

TCE6

TCE5

TCE4

TCE3

TCE2

TCE1

TCE0

H'CA --

H'CB --

H'CC PWCR

PWCR0

H'CD PWDRU

PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0

H'CE PWDRL

PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0

H'CF --

H'D0

PDR0

H'D1

PDR1

H'D2

H'D3

H'D4

PDR4

H'D5

PDR5

H'D6

PDR6

H'D7

PDR7

H'D8

H'D9

PDR9

H'DA --

H'DB --

H'DC --

H'DD --

H'DE --

H'DF --

Addr.
(Last Register

Module

Byte) Name

Name

14-bit
PWM

I/O
ports

266

B.1 On-Chip Registers (1) (cont)

Bit Names

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

H'E0

H'E1

PCR1

H'E2

H'E3

H'E4

H'E5

H'E6

H'E7

H'E8

H'E9

PCR9

H'EA --

H'EB PMR1

NOISE

EVENT

IRQC5

IRQC4

IRQC1

IRQC0

CANCEL

H'EC PMR2

UP/

SO2

SI2

SCK2

SO1

SI1

SCK1

PWM

DOWN

H'ED PMR3

SO2

SO1

PMOS

H'EE PMR4

TEO

TEO ON FREQ

VRFR

H'EF

PMR0

AN7

AN6

AN5

AN4

AN3

AN2

AN1

AN0

H'F0

SYSCR1

SSBY

STS2

STS1

STS0

LSON

H'F1

SYSCR2

DTON

H'F2

IEGR

IEG4

IEG1

IEG0

H'F3

IENR1

IEN5

IEN4

IEN1

IEN0

H'F4

IENR2

IENDT

IENTE

IENTD

IENTC

IENTB

IENTA

H'F5

IENR3

IENAD

IENKS

IENS2

IENS1

H'F6

IRR1

IRRI5

IRRI4

IRRI1

IRRI0

H'F7

IRR2

IRRDT

IRRTE

IRRTD

IRRTC

IRRTB

IRRTA

H'F8

IRR3

IRRAD

IRRKS

IRRS2

IRRS1

H'F9

H'FA

H'FB

H'FC --

H'FD --

H'FE

H'FF

Addr.
(Last Register

Module

Byte) Name

Name

System
control

I/O
ports

267

B.2 On-Chip Registers (2)

DBR--Digit Beginning Register

H'BB

VFD Controller

Address to which
register is mapped

Name of on-chip
peripheral
module

Bit
numbers

Initial bit
values

Bit names
and positions.
Dashes (--)
indicate
reserved bits.

Read only

Write only

Read and write

R/W

Possible types of access

Bit

Initial value

Read/Write

VFDE

R/W

DISP

R/W

DBR3

R/W

DBR0

R/W

DBR2

R/W

DBR1

R/W

Segment Pin Select

FD to FD

FD to FD , FS

FD to FD , FS to FS

* * *

FS to FS

Don't care.

Display Bit

All segment pins are in non-illuminating
state (pull-down state).
Digit pins continue operating.
Register and RAM values are unchanged.

Display RAM contents are output to
segment pins.

Full name
of bit

Bit settings
and
descriptions

Note:

268

STAR--Start Address Register

H'A0

SCI2

EDAR--End Address Register

H'A1

SCI2

SCR2--Serial Control Register

H'A2

SCI2

Bit

Initial value

Read/Write

STA4

R/W

STA3

R/W

STA0

R/W

STA2

R/W

STA1

R/W

Designates transfer starting address
in range from H'FF80 to H'FF9F.

Bit

Initial value

Read/Write

EDA4

R/W

EDA3

R/W

EDA0

R/W

EDA2

R/W

EDA1

R/W

Designates transfer end address
in range from H'FF80 to H'FF9F.

Bit

Initial value

Read/Write

I/O

R/W

GAP2

R/W

PS0

R/W

GAP1

R/W

PS1

R/W

Serial Clock Select

/2, SCK is output pin

/4, SCK is output pin

/8, SCK is output pin

External clock, SCK is input pin

Gap Select

No gap insertion

1-clock gap insertion

2-clock gap insertion

8-clock gap insertion

Transmit/Receive Select

Receive mode

Transmit mode

269

SMR1--Serial Mode Register 1

H'B0

SCI1

SDRU1--Serial Data Register U1

H'B1

SCI1

Bit

Initial value

Read/Write

SMR16

SMR15

SMR14

SMR13

SMR10

SMR12

SMR11

Operation Mode Select

Clock continuous output mode

8-bit transfer mode

Clock continuous output mode

16-bit transfer mode

Not 00

Clock Select

/1024, SCK is output pin

/256, SCK is output pin

/64, SCK is output pin

/32, SCK is output pin

/16, SCK is output pin

/8, SCK is output pin

/4, SCK is output pin

/2, SCK is output pin

Not used

External clock, SCK is input pin

Bit

Initial value

Read/Write

SDRU17

R/W

SDRU16

R/W

SDRU15

R/W

SDRU14

R/W

SDRU13

R/W

SDRU10

R/W

SDRU12

R/W

SDRU11

R/W

Used to set transmit data and store received data.
8-bit transfer mode: not used
16-bit transfer mode: upper 8-bits of data register

Note:

Not fixed

271

VFSR--VFD Segment Control Register

H'B9

VFD Controller/Driver

Bit

Initial value

Read/Write

VFLAG

R/W

KSE

R/W

SR4

R/W

SR3

R/W

SR0

R/W

SR2

R/W

SR1

R/W

VFD/Port Switching Flag

All pins doubling as general-purpose ports and VFD pins are used
as general-purpose ports.

Pins designated as digit or segment pins function as VFD pins.

Segment Pin Select

FS to FS

Key Scan Enable

No key scan interval

Key scan interval added

273

PDR0--Port Data Register 0

H'D0

I/O Ports

PDR1--Port Data Register 1

H'D1

I/O Ports

PDR4--Port Data Register 4

H'D4

I/O Ports

PDR5--Port Data Register 5

H'D5

I/O Ports

PDR6--Port Data Register 6

H'D6

I/O Ports

Bit

Initial value

Read/Write

PDR0

Bit

Initial value

Read/Write

PDR1

R/W

PDR1

R/W

PDR1

R/W

PDR1

R/W

Note:

Pins P1

and P1

are input-only pins; whenever they are read, the pin level is read out.

Bit

Initial value

Read/Write

PDR4

R/W

PDR4

R/W

PDR4

R/W

PDR4

R/W

PDR4

R/W

PDR4

R/W

PDR4

R/W

PDR4

R/W

Bit

Initial value

Read/Write

PDR5

R/W

PDR5

R/W

PDR5

R/W

PDR5

R/W

PDR5

R/W

PDR5

R/W

PDR5

R/W

PDR5

R/W

Bit

Initial value

Read/Write

PDR6

R/W

PDR6

R/W

PDR6

R/W

PDR6

R/W

PDR6

R/W

PDR6

R/W

PDR6

R/W

PDR6

R/W

284

PDR7--Port Data Register 7

H'D7

I/O Ports

PDR9--Port Data Register 9

H'D9

I/O Ports

PCR1--Port Control Register 1

H'E1

I/O Ports

PCR9--Port Control Register 9

H'E9

I/O Ports

Bit

Initial value

Read/Write

PDR7

R/W

PDR7

R/W

PDR7

R/W

PDR7

R/W

PDR7

R/W

PDR7

R/W

PDR7

R/W

PDR7

R/W

Bit

Initial value

Read/Write

PDR9

R/W

PDR9

R/W

PDR9

R/W

PDR9

R/W

PDR9

R/W

PDR9

R/W

PDR9

R/W

PDR9

R/W

Bit

Initial value

Read/Write

PCR1

Port 1 I/O Select

Input port

Output port

Bit

Initial value

Read/Write

PCR9

Port 9 I/O Select

Input port

Output port

285

PMR4--Port Mode Register 4

H'EE

I/O Ports

PMR0--Port Mode Register 0

H'EF

I/O Ports

Bit

Initial value

Read/Write

TEO

R/W

TEO ON

R/W

FREQ

R/W

VRFR

R/W

PMR1

IRQC5

Timer E Output Control

P1 pin function

TMOE pin function (off)

TMOE pin function (on)

TEO

PMR4

TEO ON

FREQ

VRFR

P1 /IRQ /TMOE Pin
Function Switch

Standard I/O port

Low-level output

Fixed-frequency output: /2048

Fixed-frequency output: /1024

Pin Status

Variable-frequency output:
output toggles at each timer E
overflow

External interrupt input

IRQ pin function

Don't care.

Note:

Bit

Initial value

Read/Write

AN7

AN6

AN5

AN4

AN3

AN0

AN2

AN1

Analog Input Select

General-purpose input port

Analog input channel

289

SYSCR1--System Control Register 1

H'F0

System Control

SYSCR2--System Control Register 2

H'F1

System Control

Bit

Initial value

Read/Write

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

LSON

R/W

Standby Timer Select

Wait time = 8192 states

Wait time = 16384 states

Wait time = 32768 states

Wait time = 65536 states

Wait time = 131072 states

Low-Speed On Flag

CPU runs on system clock ( )

CPU runs on subclock ( )

SUB

Standby

Sleep mode entered after SLEEP instruction is executed.

Standby mode entered after SLEEP instruction is executed.

Notes: 1. Write is enabled in active mode only.

2. This relates to the transitions between operation modes, so functioning depends on the

combination of this bit with other control bits and interrupts. For details see 3.3, System
Modes.

3. Don't care.

Bit

Initial value

Read/Write

DTON

R/W

Direct Transfer On Flag

In subactive mode, watch mode is entered when a SLEEP
instruction is executed.

1 In subactive mode, if LSON bit = 0, active mode is entered

via watch mode when a SLEEP instruction is executed.

Note:

Write is enabled in subactive mode only.

290

IENR2--Interrupt Enable Register 2

H'F4

System Control

IENR3--Interrupt Enable Register 3

H'F5

System Control

Bit

Initial value

Read/Write

R/W

IENDT

R/W

IENTE

R/W

IENTD

R/W

IENTA

R/W

IENTC

R/W

IENTB

R/W

DTON Interrupt Enable

Interrupts disabled.

Interrupts enabled.

Timer E Interrupt Enable

Interrupts disabled.

Interrupts enabled.

Timer D Interrupt Enable

Interrupts disabled.

Interrupts enabled.

Timer C Interrupt Enable

Interrupts disabled.

Interrupts enabled.

Timer B Interrupt Enable

Interrupts disabled.

Interrupts enabled.

Timer A Interrupt Enable

Interrupts disabled.

Interrupts enabled.

Bit

Initial value

Read/Write

IENAD

R/W

IENKS

R/W

IENS1

R/W

IENS2

R/W

SCI1 Interrupt Enable

Interrupts disabled.

Interrupts enabled.

SCI2 Interrupt Enable

Interrupts disabled.

Interrupts enabled.

Key Scan Interrupt Enable

Interrupts disabled.

Interrupts enabled.

A/D Conversion Complete Interrupt Enable

Interrupts disabled.

Interrupts enabled.

292

IRR2--Interrupt Request Register 2

H'F7

System Control

IRR3--Interrupt Request Register 3

H'F8

System Control

Bit

Initial value

Read/Write

IRRDT

R/W

IRRTE

R/W

IRRTD

R/W

IRRTA

R/W

IRRTC

R/W

IRRTB

R/W

DTON Interrupt Request

No interrupt request

Interrupt request

Timer E Interrupt Request

No interrupt request

Interrupt request

Timer D Interrupt Request

No interrupt request

Interrupt request

Timer C Interrupt Request

No interrupt request

Interrupt request

Timer B Interrupt Request

No interrupt request

Interrupt request

Timer A Interrupt Request

No interrupt request

Interrupt request

Note:

Only 0 can be written, to clear the flag.

Bit

Initial value

Read/Write

IRRAD

R/W

IRRKS

R/W

IRRS1

R/W

IRRS2

R/W

SCI1 Interrupt Request

No interrupt request

Interrupt request

SCI2 Interrupt Request

No interrupt request

Interrupt request

Key Scan Interrupt Request

No interrupt request

Interrupt request

A/D Conversion Complete Interrupt Request

No interrupt request

Interrupt request

Note:

Only 0 can be written, to clear the flag.

294

Appendix D Port States in Each Processing State

Table D-1 Port States

Mode

Port Pins

Reset

Sleep

Standby

Watch

Subactive

Active

to P0

Hi-Z Hi-Z

Hi-Z

Standard
input port

Hi-Z

High-voltage
input port

Hi-Z or pulled up

Hi-Z or

Hi-Z

Standard

pulled up

input port

, P1

Hi-Z or pulled up

prev. state

Hi-Z

Standard I/O

, P1

port

to P4

Hi-Z or

prev. state

Hi-Z or

High-voltage

pulled down

pulled down pulled down pulled down I/O port

to P5

Hi-Z or

prev. state

Hi-Z or

High-voltage

pulled down

pulled down pulled down pulled down I/O port

to P6

Hi-Z or

prev. state

Hi-Z or

High-voltage

pulled down

pulled down pulled down pulled down I/O port

to P7

Hi-Z or

prev. state

Hi-Z or

High-voltage

pulled down

pulled down pulled down pulled down I/O port

to P9

Hi-Z or pulled up

prev. state

Hi-Z

Standard I/O
port

Notation:
Hi-Z: High-impedance state
Prev. state: Input pins are in high-impedance state. Output pins hold their previous output.
Hi-Z or pulled up:

Standard ports for which the pull-up MOS mask option is chosen are pulled
up; ports without the pull-up MOS option are in the high-impedance state.

Hi-Z or pulled down: High-voltage ports for which the pull-down MOS mask option is chosen are

pulled down; ports without the pull-down MOS option are in the high-
impedance state.

309

Appendix E List of Mask Options

HD6433712, HD6433713 and HD6433714

311

Notes: 1.

The wide temperature range specification and I specification are special specifications. There is no
J specification for these products. Please contact your local Hitachi representative for details.
ROM data submitted in an EPROM must be written starting from address H'0000 in accordance with the
memory map of the particular microcontroller. For data outside the ROM area on the memory map use
H'FF.

FP-64A

DP-64S

(3) Package

If E (MOS pull-down) is selected as an option
for one or more high-voltage pins, V

disp

must

be selected for the P1

disp

pin.

Note:

: No MOS pull-down (D)

disp

(2) P1

disp

Crystal oscillator

Ceramic oscillator

External clock

(4) Oscillator at OSC

and OSC

Used

Not used

(5) Oscillator at X

and X

OSC

MHz

= 32.768 kHz

= V

C: No MOS pull-up
E: With MOS pull-down

Date of order

Company

Address

Name

ROM code name

Part no.

, 19

B: With MOS pull-up
D: No MOS pull-down

(1) I/O Options

I/O

I/O option

B C D E

/IRQ

/TMOE

/EVENT

/FS

disp

/PWM

/SCK

/SI

/SO

/SCK

/SI

/CS

/SO

/UD

I/O

I/O option

B C D E

/FD

/FS

/FD

/FS

/FD

/FS

/FD

/FS

/FD

/FS

/FD

/FS

/FD

/FS

/FD

/FS

/FD

I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

Standard pins

High-voltage pins

Fill in (2) below

High-voltage pins

Please indicate the selected specifications by
marking the appropriate box (with an

�

mark). The shaded boxes cannot be selected.

/FS

Standard pins

/FD

HD6433712 HD6433713
HD6433714

Appendix F Rise Time and Fall Time of High-Voltage Pins

With the mask ROM versions there is a choice of high-voltage pin output configurations. Either
PMOS open-drain (D) or MOS pull-down (E) may be selected. (Only PMOS open-drain is
available as the output configuration of high-voltage pins on ZTATTM versions.)

The rise time t

and fall time t

of high-voltage pin output are as follows.

It is possible to estimate t

and t

from the time constant

= C

R (time up to 63% of rise or fall).

The time constant is determined by the PMOS on-resistance and load capacitance. The DC
on-resistance is approximately 200

(based on V

= V

� 3 V at �I

= 15 mA,

3/0.015 = 200). The AC on-resistance however, includes the non-saturation state when the
PMOS transistor turns on (it is not a constant-current source), resulting in a longer time
constant. Assuming a load capacitance of 30 pF at high-voltage pins, the minimum value is
approximately 20 ns.

The time constant is determined by the pull-down resistance and load capacitance (including
wiring capacitance, etc.). As an example, assuming a pull-down resistance of 5 k

and load

capacitance of 30 pF, the following is derived.

�

�12

= 150

�

�9

(150 ns)

MOS pull-down resistance varies from 45 k

to 300 k

, so all due care must be taken in

timing design.

Note: If pull-down resistance is made too small in an attempt to speed up the fall time, �I

will

increase, limiting the output high-level voltage (V

). Pull-down resistance must be set to

a suitable value taking into consideration both operation speed and the output high level.

63%

V
or V

disp

H8/3714 Series
microcontroller

Pull-down

resistance

Load

capacitance

312

Электронный компонент: HD6433713

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