Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.

The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas

Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)

Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand

names are mentioned in the document, these names have in fact all been changed to Renesas

Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and

corporate statement, no changes whatsoever have been made to the contents of the document, and

these changes do not constitute any alteration to the contents of the document itself.

Renesas Technology Home Page: http://www.renesas.com

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

To all our customers

Cautions

Keep safety first in your circuit designs!

Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but

there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire

or property damage.

Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i)

placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or

mishap.

Notes regarding these materials

These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation

product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any

other rights, belonging to Renesas Technology Corporation or a third party.

Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights,

originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in

these materials.

All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents

information on products at the time of publication of these materials, and are subject to change by Renesas Technology

Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact

Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product

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When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and

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Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.

HD404374/HD404384/

HD404389/HD404082/HD404084 Series

Low-Voltage AS Microcomputers with On-Chip A/D Converter

ADE-202-086C (O)

Rev. 4.0

Feb. 2000

Description

The HD404374, HD404384, and HD404389 Series comprise low-voltage, 4-bit single-chip
microcomputers equipped with four 10-bit A/D converter channels, a serial interface, and large-current I/O
pins. These devices are suitable for use in applications requiring high resolution A/D converter control,
such as battery chargers.

The HD404082 and HD404084 series offer less advanced features than the HD404384 series. They are 4-
bit microcomputers that support low-voltage operation for backward software compatibility.

HD404374 Series microcomputers have a 32.768 kHz sub-resonator for realtime clock use, providing a
time counting facility, and a variety of low-power modes to reduce current drain.

The HD407A4374, HD407A4384, HD407A4389, HD407C4374, HD407C4384, and HD407C4389 are
ZTAT

microcomputers with on-chip PROM that drastically shortens development time and ensures a

smooth transition from debugging to mass production. (The PROM programming specifications are the
same as for the 27256 type.)

ZTAT

: Zero Turn-Around Time. ZTAT

is a trademark of Hitachi, Ltd.

Features

�

20 I/O pins

Large-current I/O pins (source: 10 mA max.):4

Large-current I/O pins (sink: 15 mA max.):4

Analog input multiplexed pins: 4 (HD404374, HD404384, and HD404389 Series)

�

8-bit timer: 1 channel

16-bit timer: 1 channel (Can also be used as two 8-bit timer channels)

�

Two timer outputs (including PWM output)

�

Event counter inputs (edge-programmable)

�

Clock-synchronous 8-bit serial interface

�

A/D converter

4 channels

�

10-bits (HD404374 and HD404384 Series)

HD404374/HD404384/HD404389/HD404082/HD404084 Series

6 channels

�

10-bits (HD404389 Series)

None (HD404082 and HD404084 Series)

�

On-chip oscillators

HD404374 Series

�

Main clock (ceramic resonator, crystal resonator, CR oscillation* or external clock operation
possible)

�

Sub-clock (32.768 kHz crystal resonator)

HD404384, HD404389, HD404082, and HD404084 Series

�

Main clock (ceramic resonator, crystal resonator, CR oscillation* or external clock operation
possible)

Note: CR oscillation in an optional function.

�

Interrupts

External: 2 (including one edge-programmable)

Internal : 5 (HD404374/HD404384/HD404389 Series)

: 4 (HD404082/HD404084 Series)

�

Subroutine stack up to 16 levels, including interrupts

�

Low-power dissipation modes

HD404374 Series:

HD404384, HD404389, HD404082, and HD404084 Series:

�

Module standby (timers, serial interface, A/D converter)

�

System clock division software switching (1/4 or 1/32)

�

Inputs for return from stop mode (wakeup): 1

�

Instruction execution time

Min. 0.89

�

s (f

OSC

= 4.5 MHz, division by 1/4)

Min. 0.47

�

s (f

OSC

= 8.5 MHz, division by 1/4)

�

Operation voltage

1.8 V to 5.5 V

2.0 V to 5.5 V (ZTAT

)

Cautions about operation!

�

Electrical properties presented on the data sheet for the mask ROM and ZTAT

versions will surely

and sufficiently satisfy the standard values. However, real capabilities, operation margin, noise margin,
and other properties may vary depending on differences of manufacturing processes, internal wiring
patterns, etc. Therefore, it is requested for users to carry out an evaluation test for each product on an
actual system under the same conditions to see its operation.

�

After power supply has been connected, the values for the memory register, data and stack areas will be
undefined. Initialize prior to use.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Ordering Information

HD404374 Series

Type

Product Name

Model Name

ROM
(Words)

RAM
(Digits)

Package

Mask ROM HD404372

HD404372FT

2,048

512

30-pin plastic SSOP(FP-30D)

HD404372H

48-pin plastic LQFP(FP-48B)

HD40A4372

HD40A4372FT

30-pin plastic SSOP(FP-30D)

HD40A4372H

48-pin plastic LQFP(FP-48B)

HD40C4372

HD40C4372FT

30-pin plastic SSOP(FP-30D)

HD40C4372H

48-pin plastic LQFP(FP-48B)

HD404374

HD404374FT

4,096

30-pin plastic SSOP(FP-30D)

HD404374H

48-pin plastic LQFP(FP-48B)

HD40A4374

HD40A4374FT

30-pin plastic SSOP(FP-30D)

HD40A4374H

48-pin plastic LQFP(FP-48B)

HD40C4374

HD40C4374FT

30-pin plastic SSOP(FP-30D)

HD40C4374H

48-pin plastic LQFP(FP-48B)

ZTAT

HD407A4374

HD407A4374FT 4,096

30-pin plastic SSOP (FP-30D)

HD407C4374

HD407C4374FT

30-pin plastic SSOP(FP-30D)

HD404374/HD404384/HD404389/HD404082/HD404084 Series

HD404384 Series

Type

Product Name

Model Name

ROM
(Words)

RAM
(Digits)

Package

Mask ROM HD404382

HD404382FT

2,048

512

30-pin plastic SSOP (FP-30D)

HD404382S

28-pin plastic DILP (DP-28S)

HD404382H

48-pin plastic LQFP (FP-48B)

HD40A4382

HD40A4382FT

30-pin plastic SSOP (FP-30D)

HD40A4382S

28-pin plastic DILP (DP-28S)

HD40A4382H

48-pin plastic LQFP (FP-48B)

HD40C4382

HD40C4382FT

30-pin plastic SSOP (FP-30D)

HD40C4382S

28-pin plastic DILP (DP-28S)

HD40C4382H

48-pin plastic LQFP (FP-48B)

HD404384

HD404384FT

4,096

30-pin plastic SSOP (FP-30D)

HD404384S

28-pin plastic DILP (DP-28S)

HD404384H

48-pin plastic LQFP (FP-48B)

HD40A4384

HD40A4384FT

30-pin plastic SSOP (FP-30D)

HD40A4384S

28-pin plastic DILP (DP-28S)

HD40A4384H

48-pin plastic LQFP (FP-48B)

HD40C4384

HD40C4384FT

30-pin plastic SSOP (FP-30D)

HD40C4384S

28-pin plastic DILP (DP-28S)

HD40C4384H

48-pin plastic LQFP (FP-48B)

ZTAT

HD407A4384

HD407A4384FT 4,096

30-pin plastic SSOP (FP-30D)

HD407A4384S

28-pin plastic DILP (DP-28S)

HD407C4384

HD407C4384FT

30-pin plastic SSOP (FP-30D)

HD407C4384S

28-pin plastic DILP (DP-28S)

HD404374/HD404384/HD404389/HD404082/HD404084 Series

HD404082 Series

Type

Product Name

Model Name

ROM
(Words)

RAM
(Digits)

Package

Mask ROM HD404081

HD404081FT

1,024

128

30-pin plastic SSOP (FP-30D)

HD404081S

28-pin plastic DILP (DP-28S)

HD404081H

48-pin plastic LQFP (FP-48B)

HD40A4081

HD40A4081FT

30-pin plastic SSOP (FP-30D)

HD40A4081S

28-pin plastic DILP (DP-28S)

HD40A4081H

48-pin plastic LQFP (FP-48B)

HD40C4081

HD40C4081FT

30-pin plastic SSOP (FP-30D)

HD40C4081S

28-pin plastic DILP (DP-28S)

HD40C4081H

48-pin plastic LQFP (FP-48B)

HD404082

HD404082FT

2,048

30-pin plastic SSOP (FP-30D)

HD404082S

28-pin plastic DILP (DP-28S)

HD404082H

48-pin plastic LQFP (FP-48B)

HCD404082

chip

HD40A4082

HD40A4082FT

30-pin plastic SSOP (FP-30D)

HD40A4082S

28-pin plastic DILP (DP-28S)

HD40A4082H

48-pin plastic LQFP (FP-48B)

HD40C4082

HD40C4082FT

30-pin plastic SSOP (FP-30D)

HD40C4082S

28-pin plastic DILP (DP-28S)

HD40C4082H

48-pin plastic LQFP (FP-48B)

HCD40C4082

chip

ZTAT

Uses HD404384 series ZTAT

Notes: 1. The FP-48B is subject to the following limitations:

(1) It is available in a mask ROM version only. For debugging, etc., the ZTAT

version of a

different package will need to be used.

(2) The WS version will become available at the beginning of mass production.

2. Currently in planning stage.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

List of Functions

Product Name

HD404372,
HD40A4372,
HD40C4372

HD404374,
HD40A4374,
HD40C4374,
HD407A4374,
HD407C4374

HD404382,
HD40A4382,
HD40C4382

HD404384,
HD40A4384,
HD40C4384,
HD407A4384,
HD407C4384

HD404388,
HD40A4388,
HD40C4388

ROM(words)

2,048

4,096
ZTAT PROM

2,048

4,096
ZTAT PROM

8,192

RAM (digit)

512

I/O

20 (max)

Large-current
I/O pins

4 (source, 10 mA max), 4 (sink, 15 mA max)

Analog input
multiplexed pins

Timer/

counter

Timer output

2 (PWM output possible)

Event input

1 (edge selection possible)

Serial interface

1 (8-bit synchronous)

A/D converter

10 bits

�

4 channels

10 bits

�

channels

Interrupt

External

sources

Internal

Low-power

modes

Stop mode

Available

Watch mode

Available

Standby mode

Available

Subactive mode Available

Module standby

Available

System clock division software
switching

Available

Main oscillator

Ceramic
oscillation

Available

Crystal
oscillation

Available

CR oscillation

Available (HD40C4372, HD40C4374, HD407C4374, HD40C4382, HD40C4384,
HD407C4384, HD40C4388, HD40C4389, HD407C4389, HD40C4081, HD40C4082,
HCD40C4082, HD40C4084, HCD40C4084)

Sub-oscillator

Crystal
oscillation

Available
(32.768kHz)

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Product Name

HD404372,
HD40A4372,
HD40C4372

HD404374,
HD40A4374,
HD40C4374,
HD407A4374,
HD407C4374

HD404382,
HD40A4382,
HD40C4382

HD404384,
HD40A4384,
HD40C4384,
HD407A4384,
HD407C4384

HD404388,
HD40A4388,
HD40C4388

Minimum instruction execution
time

0.47 ms (f

OSC

= 8.5 MHz) : HD40A4372, HD40A4374, HD407A4374, HD40A4382,

HD40A4384, HD407A4384, HD40A4388, HD40A4389, HD407A4389, HD40A4081,
HD40A4082, HD40A4084

0.89 ms (f

OSC

= 4.5 MHz) : HD404372, HD404374, HD404382, HD404384,

HD404388, HD404389, HD404081, HD404082, HCD404082, HD404084,
HCD404084

1.14 ms (f

OSC

= 3.5 MHz) : HD40C4372, HD40C4374, HD407C4374, HD40C4382,

HD40C4384, HD407C4384, HD40C4388, HD40C4389, HD407C4389, HD40C4081,
HD40C4082, HCD40C4082, HD40C4084, HCD40C4084

Operating
voltage (V)

1.8 to 5.5 V : Mask ROM, 2.0 to 5.5 V : ZTATTM

Package

FP-30D

Available

DP-28S

Available

FP-48B

Available

Chip

Guaranteed operation
temperature(

�

�20 to +75: Mask ROM
�40 to +85: ZTAT

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Product Nme

HD404389,

HD40A4389,

HD40C4389,

HD407A4389,

HD407C4389

HD404081,

HD40A4081,

HD40C4081

HD404082,

HD40A4082,

HD40C4082

HCD404082,

HCD40C4082

HD404084,

HD40A4084,

HD40C4084

HCD404084,

HCD40C4084

ROM(words)

16,384
ZTAT PROM

1,024

2,048

4,096

RAM (digit)

512

128

I/O

20 (max)

Large-current
I/O pins

4 (source, 10 mA max), 4 (sink, 15 mA max)

Analog input
multiplexed pins

Timer/

counter

Timer output

2 (PWM output possible)

Event input

1 (edge selection possible)

Serial interface

1 (8-bit synchronous)

A/D converter

10 bits

�

channels

Interrupt

External

sources

Internal

Low-power

modes

Stop mode

Available

Watch mode

Available

Standby mode

Available

Subactive mode Available

Module standby

Available

System clock division software
switching

Available

Main oscillator

Ceramic
oscillation

Available

Crystal
oscillation

Available

CR oscillation

Available (HD40C4372, HD40C4374, HD407C4374, HD40C4382, HD40C4384,
HD407C4384, HD40C4388, HD40C4389, HD407C4389, HD40C4081, HD40C4082,
HCD40C4082, HD40C4084, HCD40C4084)

Sub-oscillator

Crystal
oscillation

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Product Nme

HD404389,

HD40A4389,

HD40C4389,

HD407A4389,

HD407C4389

HD404081,

HD40A4081,

HD40C4081

HD404082,

HD40A4082,

HD40C4082

HCD40482,

HCD40C4082

HD404084,

HD40A4084,

HD40C4084

HCD404084,

HCD40C4084

Minimum
instruction
execution time

0.47

�

s (f

OSC

= 8.5 MHz) : HD40A4372, HD40A4374, HD407A4374, HD40A4382,

HD40A4384, HD407A4384, HD40A4388, HD40A4389, HD407A4389, HD40A4081,
HD40A4082, HD40A4084

0.89

�

s (f

OSC

= 4.5 MHz) : HD404372, HD404374, HD404382, HD404384,

HD404388, HD404389, HD404081, HD404082, HCD404082, HD404084,
HCD404084

1.14

�

s (f

OSC

= 3.5 MHz) : HD40C4372, HD40C4374, HD407C4374, HD40C4382,

HD40C4384, HD407C4384, HD40C4388, HD40C4389, HD407C4389, HD40C4081,
HD40C4082, HCD40C4082, HD40C4084, HCD40C4084

Operating
voltage (V)

1.8 to 5.5 V : Mask ROM, 2.0 to 5.5 V : ZTAT

Package

FP-30D

Available

DP-28S

Available

FP-48B

In planning
stage

Chip

Available

Guaranteed operation
temperature(

�

�20 to +75:
Mask ROM
�40 to +85:
ZTAT

+75

�20 to +75:
Mask ROM
�40 to +85:
ZTAT

+75

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Pin Arrangement

GND

Vcc

AVcc

/AN

AVss

OSC

OCS

TEST

X2
X1

RESET

INT

/SI/SO

SCK

/TOC

/TOB

/EVNB

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16

FP-30D

(Top View)

P-MOS large current pins

N-MOS large current pins

HD404374 Series

36
35
34
33
32
31
30
29
28
27
26
25

1
2
3
4
5
6
7
8
9

10
11
12

NC
D

INT

NC
R2

/SI/SO

/AN

OSC

TEST

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37

RESET

/EVNB

/TOB

/TOC

SCK

GND

FP-48B

(Top View)

P-MOS large current pins

N-MOS large current pins

HD404374/HD404384/HD404389/HD404082/HD404084 Series

GND

Vcc

AVcc

/AN

AVss

OSC

OCS

TEST

NC
NC

RESET

INT

/SI/SO

SCK

/TOC

/TOB

/EVNB

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16

FP-30D

(Top View)

P-MOS large current pins

N-MOS large current pins

GND

Vcc

AVcc

/AN

AVss

OSC

OCS

TEST

RESET

/EVNB

INT

/SI/SO

SCK

/TOC

/TOB

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

DP-28S

(Top View)

P-MOS large current pins

N-MOS large current pins

HD404384 Series

36
35
34
33
32
31
30
29
28
27
26
25

1
2
3
4
5
6
7
8
9

10
11
12

NC
D

INT

NC
R2

/SI/SO

/AN

OSC

TEST

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37

RESET

/EVNB

/TOB

/TOC

SCK

GND

FP-48B

(Top View)

N-MOS large current pins

HD404374/HD404384/HD404389/HD404082/HD404084 Series

GND

Vcc

AVcc

/AN

TEST

OSC

RESET

INT

/SI/SO

SCK

/TOC

/TOB

/EVNB

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16

FP-30D

(Top View)

P-MOS large current pins

N-MOS large current pins

HD404389 Series

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15

INT

/SI/SO

SCK

/TOC

/TOB

/EVNB

GND

OSC

TEST

NC
NC

RESET

FP-30D

(Top View)

P-MOS large current pins

N-MOS large current pins

28
27
26
25
24
23
22
21
20
19
18
17
16
15

1
2
3
4
5
6
7
8
9

10
11
12
13
14

INT

/SI/SO

SCK

/TOC

/TOB

GND

OSC

TEST

RESET

/EVNB

DP-28S

(Top View)

P-MOS large current pins

N-MOS large current pins

HD404082 and HD404084 Series

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Pad Coordinates

HCD404082 and HCD404084

Chip size (X

�

Y):

Coordinates:

Home point position:

Pad size (X

�

Y):

Chip thickness:

4.63

�

4.77 (mm)

Pad center

Chip center

�

90 (

�

280 (

�

Chip center

(X=0,Y=0)

Mold

Pad

Coodinates

Pad

Coodinates

No.

Pad name

X (

�

Y (

�

No.

Pad name

X (

�

Y (

�

GND

-458

1403

572

-1403

-826

1403

982

-1403

-1338

1403

1338

-1403

-1338

1006

1338

-1020

-1338

525

1338

-637

-1338

285

1338

-254

OSC1

-1338

-550

1338

129

OSC2

-1338

-954

1338

768

TEST

-1338

-1251

1338

1170

RESETN

-1197

-1403

1153

1403

-577

-1403

751

1403

-194

-1403

349

1403

189

-1403

-53

1403

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Pin Description

HD404374 and HD404384 Series

Pin Number

Item

Symbol

FP-30D

DP-28S

DP-48B

I/O

Function

Power
supply

Apply the power supply voltage to this pin.

GND

Connect to ground.

Test

TEST

Input

Not for use by the user application.
Connect to GND potential.

Reset

RESET

Input

Used to reset the MCU.

Oscillation OSC

Input

Internal oscillator input/output pins.
Connect a ceramic resonator, crystal
resonator, or external oscillator circuit.

OSC

Output

When using CR oscillation, connect a
resistor.

13*

Input

Realtime clock oscillator input/output pins.
Connect a 32.768 kHz crystal. If 32.768
kHz crystal oscillation is not used, fix the

12*

Output

X1 pin to V

and leave the X2 pin open.

Port

�D

21�30

19�28

27, 29, 31, 33, 35�
37, 39, 40, 43

I/O

I/O pins addressed bit by bit. D

to D

are

large-current source pins (max. 10 mA),
and D

to D

are large-current sink pins

(max. 15 mA).

, R1

, R2

�R7

15�20,
4�7

13�18,
4�7

17, 19, 21, 23�25,
1�4

I/O

I/O pins, addressed in 4-bit units.

Interrupt

INT

Input

External interrupt input pin

Wakeup

Input

Input pin used for transition from stop
mode to active mode.

Serial

SCK

I/O

Serial interface clock I/O pin

interface

Input

Serial interface receive data input pin

Output

Serial interface transmit data output pin

Timer

TOB,TOC

17, 18

15, 16

21, 23

Output

Timer output pins

EVNB

Input

Event count input pin

A/D
converter

A/D converter power supply pin. Connect
as close as possible to the V

pin so as to

be at the same potential as V

Ground pin for AV

. Connect as close as

possible to the GND pin so as to be at the
same potential as GND.

�AN

4�7

1�4

Input

A/D converter analog input pins

Other

12*

13*

5, 8, 10, 12*

13*

, 14, 16, 18,

20, 22, 26, 28, 30,
32, 34, 38, 41, 42,
44, 46

Connect to GND potential.

Notes: *1 Applies to HD404374 Series.

*2 Applies to HD404384 Series.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

HD404389 Series

Pin Number

Item

Symbol

FP-30D

I/O

Function

Power
supply

Apply the power supply voltage to this pin.

GND

Connect to ground.

Test

TEST

Input

Not for use by the user application. Connect to GND potential.

Reset

RESET

Input

Used to reset the MCU.

Oscillation OSC

Input

Internal oscillator input/output pins. Connect a ceramic resonator,
crystal resonator, or external oscillator circuit.

OSC

Output

When using CR oscillation, connect a resistor.

Port

�D

21�30

I/O

I/O pins addressed bit by bit. D

to D

are large-current source

pins (max. 10 mA), and D

to D

are large-current sink pins (max.

15 mA).

, R1

, R2

�R7

15�20,
4�7

I/O

I/O pins, addressed in 4-bit units.

Interrupt

INT

Input

External interrupt input pin

Wakeup

Input

Input pin used for transition from stop mode to active mode.

Serial

SCK

I/O

Serial interface clock I/O pin

interface

Input

Serial interface receive data input pin

Output

Serial interface transmit data output pin

Timer

TOB,TOC

17, 18

Output

Timer output pins

EVNB

Input

Event count input pin

A/D
converter

A/D converter power supply pin. Connect as close as possible to
the V

pin so as to be at the same potential as V

Ground pin for AV

. Connect as close as possible to the GND pin

so as to be at the same potential as GND.

�AN

4�9

Input

A/D converter analog input pins

HD404374/HD404384/HD404389/HD404082/HD404084 Series

HD404082 and HD404084 Series

Pin Number

Item

Symbol

FP-30D

DP-28S Chip

I/O

Function

Power
supply

Apply the power supply voltage to this pin.

GND

Connect to ground.

Test

TEST

Input

Not for use by the user application. Connect to GND
potential.

Reset

RESET

Input

Used to reset the MCU.

Oscillation OSC

Input

Internal oscillator input/output pins. Connect a ceramic
resonator, crystal resonator, or external oscillator circuit.

OSC

Output When using CR oscillation, connect a resistor.

Port

�D

21�30

19�28

17�26

I/O

I/O pins addressed bit by bit. D

to D

are large-current

source pins (max. 10 mA), and D

to D

are large-current

sink pins (max. 15 mA).

, R1

, R2

�R7

15�20,
4�7

13�18,
4�7

11�16,
3�6

I/O

I/O pins, addressed in 4-bit units.

Interrupt

INT

Input

External interrupt input pin

Wakeup

Input

Input pin used for transition from stop mode to active
mode.

Serial

SCK

I/O

Serial interface clock I/O pin

interface

Input

Serial interface receive data input pin

Output Serial interface transmit data output pin

Timer

TOB,TOC

17, 18

15, 16

13, 14

Output Timer output pins

EVNB

Input

Event count input pin

Other

3, 8, 12,
13

3, 8

Connect to GND potential.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Memory Map

ROM Memory Map

The ROM memory map is shown in figure 1 and is described below.

Vector address area ($0000 to $000F): When an MCU reset or interrupt handling is performed, the
program is executed from the vector address. A JMPL instruction should be used to branch to the start
address of the reset routine or the interrupt routine.

Zero page subroutine area ($0000 to $003F):A branch can be made to a subroutine in the area $0000 to
$003F with the CAL instruction.

Pattern area ($0000 to $0FFF): ROM data in the area $0000 to $0FFF can be referenced as pattern data
with the P instruction.

Program area ($0000 to $03FF (HD404081, HD40A4081, HD40C4081)), ($0000 to $07FF (HD404372,
HD40A4372, HD40C4372, HD404382, HD40A4382, HD40C4382, HD404082, HCD404082,
HD40A4082, HD40C4082, HCD40C4082)), ($0000 to $0FFF (HD404374, HD40A4374, HD40C4374,
HD404384, HD40A4384, HD40C4384, HD407A4374, HD407C4374, HD407A4384, HD407C4384,
HD404084, HCD404084, HD40A4084, HD40C4084, HCD40C4084)), ($0000 to $1FFF (HD404388,
HD40A4388, HD40C4388)), ($0000 to $3FFF (HD404389, HD40A4389, HD40C4389, HD407A4389,
HD407C4389)).

HD404374/HD404384/HD404389/HD404082/HD404084 Series

$0000

$000F
$0010

$003F
$0040
$03FF
$0400

$07FF
$0800

Vector addresses

(16 words)

Zero page subroutine area

(64 words)

Pattern and program area

(2,048 words)

Pattern and program area

(1,024 words)

Pattern and program area

(4,096 words)

$0FFF
$1000

$1FFF

$3FFF

$2000

Pattern and program area

(8,192 words)

Pattern and program area

(16,384 words)

$0000

$0001

$0002

$0003

$0004

$0005

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

JMPL instruction

(Jump to reset routine)

JMPL instruction

(Jump to

routine)

JMPL instruction

(Jump to

INT

routine)

JMPL instruction

(Jump to timer A routine)

JMPL instruction

(Jump to timer B routine)

JMPL instruction

(Jump to timer C routine)

JMPL instruction

(Jump to A/D or serial interface routine)

ROM address

*1 HD404081, HD40A4081, HD40C4081
*2 HD40372, HD40A4372, HD40C4372, HD404382,
HD40A4382, HD40C4382, HD404082, HCD404082,
HD40A4082, HD40C4082, HCD40C4082
*3 HD404374, HD40A4374, HD40C4374, HD404384,
HD40A4384, HD40C4384, HD407A4374, HD407C4374,
HD407A4384, HD407C4384, HD404084, HCD404084,
HD40A4084, HD40C4084, HCD40C4084
*4 HD404388, HD40A4388, HD40C4388
*5 HD404389, HD40A4389, HD40C4389, HD407A4389,
HD407C4389

Notes:

Figure 1 ROM Memory Map

RAM Memory Map

The MCU has on-chip RAM comprising a memory register area, data area, and stack area. In addition to
these areas, an interrupt control bit area, special register area, and register flag area are mapped onto RAM
memory space as a RAM-mapped register area.The RAM memory map is shown in figure 2 and described
below.

After power supply has been connected, regardless of a reset, the values for the memory register,
data and stack areas will be undefined. Make sure to initialize prior to use.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Speed Select Reg.
Miscellaneous Reg.

Port Mode Reg.0
Port Mode Reg.1
Port Mode Reg.2
Port Mode Reg.3

Module Standby Reg.1
Module Standby Reg.2
Timer Mode Reg.A
Timer Mode Reg.B1
Timer Mode Reg.B2

Timer Mode Reg.C1
Timer Mode Reg.C2

Serial Mode Reg.1
Serial Mode Reg.2
Serial Data Reg.Lower
Serial Data Reg.Upper
A/D Mode reg.
A/D Data Reg.Lower
A/D Data Reg.Middle
A/D Data Reg.Upper

Port D

DCR

Port D

DCR

Port D

DCR

Port R0 DCR
Port R1 DCR
Port R2 DCR

Port R7 DCR

$000

$03F

$040

$04F

$050

$08F

$090

$23F

$240

$3BF
$3C0

$3FF

HD404374 Series
HD404384 Series
HD404389 Series

HD404082 Series

Memory register (MR) area

(16 digits)

Data (432 digits)

Stack area

(64 digits)

Interrupt control bit area

Not used

W
W

W
W
W
W

W
W
W
W
W

R/W
R/W

W
W

R/W
R/W

W
W

R/W
R/W

R
R
R

W
W
W

Timer-B

Timer-C

Not used

$000
$001
$002
$003
$004
$005
$006
$007
$008
$009

$00A
$00B

$00C
$00D

$00E

$00F

$010
$011
$012
$013
$014
$015
$016
$017
$018

$01F

$020

$023
$024
$025
$026
$027
$028
$029

$02A
$02B

$02C

$02F

$030
$031
$032
$033
$034
$035
$036
$037

$03A
$03B

$03C

$03F

Timer Read Reg.B Lower

(TRBL)

Timer Write Reg.B Lower

(TWBL)

Timer Read Reg.B Upper

(TRBU)

Timer Write Reg.B Upper

(TWBU) W

Timer Read Reg.C Lower

(TRCL)

Timer Write Reg.C Lower

(TWCL)

Timer Read Reg.C Upper

(TRCU)

Timer Write Reg.C Upper

(TWCU) W

$012
$013

$016
$017

*2
*2
*2
*2

Not used

$000

$03F

$040

$04F

$050

$08F

$090

$0BF
$0C0

$3BF
$3C0

$3FF

Memory register (MR) area

(16 digits)

Data (48 digits)

Stack area

(64 digits)

Not used

(SSR)

(MIS)

(PMR0)
(PMR1)
(PMR2)
(PMR3)

(MSR1)
(MSR2)

(TMA)

(TMB1)
(TMB2)

(TRBL/TWBL)

(TRBU/TWBU)

(TMC1)
(TMC2)

(TRCL/TWCL)

(TRCU/TWCU)

(SMR1)
(SMR2)

(SRL)

(SRU)

(AMR)

(ADRL)

(ADRM)

(ADRU)

(DCD0)
(DCD1)
(DCD2)

(DCR0)
(DCR1)
(DCR2)

(DCR7)

Notes: R : Read

W : Write

R/W : Read/Write

Two registers are mapped onto

the same address ($012, $013,

$016, $017).

Applies to HD404374, HD404384, and HD404389 Series.

RAM�mapped
register area

HD404084 Series

$000

$03F

$040

$04F

$050

$08F

$090

$13F

$140

$3BF
$3C0

$3FF

Memory register (MR) area

(16 digits)

Data (176 digits)

Stack area

(64 digits)

Not used

RAM�mapped
register area

Figure 2 RAM Memory Map

HD404374/HD404384/HD404389/HD404082/HD404084 Series

RAM-mapped register area ($000 to $03F):

�

Interrupt control bit area ($000 to $003)

This area consists of bits used for interrupt control. Its configuration is shown in figure 3. Individual
bits can only be accessed by RAM bit manipulation instructions (SEM/SEMD, REM/REMD,
TM/TMD). There are restrictions on access to certain bits. The individual bits and instruction
restrictions are shown in figure 4.

�

Special register area ($004 to $01F, $024 to $03F)

This area comprises mode registers and data registers for external interrupts, the serial interface, timers,
A/D converter, etc., and I/O pin data control registers. Its configuration is shown in figures 2 and 5.
These registers are of three kinds: write-only (W), read-only (R), and read/write (R/W). RAM bit
manipulation instructions cannot be used on the other registers.

�

This area consists of the DTON and WDON flags and interrupt control bits. Its configuration is shown
in figure 3. Individual bits can only be accessed by RAM bit manipulation instructions (SEM/SEMD,
REM/REMD, TM/TMD). There are restrictions on access to certain bits. The individual bits and
instruction restrictions are shown in figure 4.

Memory register (MR) area ($040 to $04F):

In this data area, the 16 memory register digits (MR(0) to MR(15)) can also be accessed by the register-
register instructions LAMR and XMRA. The configuration of this area is shown in figure 6.

Data area ($090 to $23F (HD404374, HD404384, HD404389 Series))

($090 to $0BF (HD404082 Series))
($090 to $13F (HD404084 Series))

Stack area ($3C0 to $3FF):

This is the stack area used to save the contents of the program counter (PC), status flag (ST), and carry flag
(CA) when a subroutine call (CAL or CALL instruction) or interrupt handling is performed. As four digits
are used for one level, the area can be used as a subroutine stack with a maximum of 16 levels. The saved
data and saved status information are shown in figure 6. The program counter is restored by the RTN and
RTNI instructions. The status and carry flags are restored by the RTNI instruction, but are not affected by
the RTN instruction. Any part of the area not used for saving can be used as a data area.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

RAM address

$000

$001

$002

$003

Bit 1
RSP

(Stack pointer reset)

IM0

(

INT

interrupt

mask)

IMTA

(Timer A interrupt

mask)
IMTC

(Timer C interrupt

mask)

Bit 0

(Interrupt enable flag)

IF0

(

INT

interrupt

request flag)

IFTA

(Timer A interrupt

request flag)

IFTC

(Timer C interrupt

request flag)

$020

$021

$022

$023

IF
IM
IE
SP

: Interrupt Request Flag
: Interrupt Mask
: Interrupt Enable Flag
: Stack Pointer

Notes: *1 Applies to HD404374 Series.

*2 Applies to HD404374, HD404384, and HD404389 Series.

Bit 3

IMWU

(

interrupt mask)

Not used

IMTB

(Timer B interrupt

mask)

IMAD

(A/D converter

interrupt mask)

Bit 2

IFWU

(

interrupt

request flag)

Not used

IFTB

(Timer B interrupt

request flag)

IFAD

(A/D converter interrupt

request flag)

ADSF

(A/D start flag)

Not used

IFS

(Serial interrupt

request flag)

WDON

(Watchdog on flag)

Not used

LSON

(Low speed on flag)

Not used

DTON

(DTON flag)

GEF

(Gear enable flag)

Not used

IMS

(Serial interrupt

mask)

Figure 3 Interrupt Control Bit and Register Flag Area Configuration

HD404374/HD404384/HD404389/HD404082/HD404084 Series

LSON

ICSF

ICEF

GEF

RSP

WDON

ADSF

DTON

Not Used

SEM/SEMD

Allowed

Not executed

Allowed

Not executed in active mode

Used in subactive mode

Not executed

Allowed

Not executed

Inhibited

Allowed

Not executed

Allowed

Inhibited

Allowed

Inhibited

REM/REMD

TM/TMD

Bits in the interrupt control bit area and register flag area can be set and reset by the SEM or SEMD
instruction and the REM or REMD instruction, and tested by the TM or TMD instruction. They are not
affected by any other instructions.
The following restrictions apply to individual bits.

The WDON bit is reset only by stop mode clearance by means of an MCU reset.
Do not use the REM or REMD instruction on the ADSF bit during A/D conversion.
The DTON bit is always in the reset state in active mode.
If the TM or TMD instruction is used on a bit for which its use is prohibited, or on a nonexistent
bit, the status flag value will be undetermined

Notes :

* 1 Applies to HD404374 Series.
* 2 Applies to HD404374, HD404384, and HD404389 Series.

Figure 4 Instruction Restrictions

HD404374/HD404384/HD404389/HD404082/HD404084 Series

RAM address

Bit 3

Bit 2

Bit 1

Bit 0

$000
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$010
$011
$012
$013
$014
$015
$016
$017
$018

$01F
$020
$023
$024
$025
$026
$027
$028
$029
$02A
$02B
$02C

$02F
$030
$031
$032
$033
$034
$035
$036
$037

$03A
$03B
$03C

$03F

SSR

MIS

PMR0
PMR1
PMR2
PMR3

MSR1
MSR2

TMA

TMB1
TMB2

TRBL/TWBL

TRBU/TWBU

TMC1
TMC2

TRCL/TWCL

TRCU/TWCU

SMR1
SMR2

SRL

SRU

AMR

ADRL

ADRM

ADRU

DCD0
DCD1
DCD2

DCR0
DCR1
DCR2

DCR7

Interrupt control bit area

32 kHz oscillation stop setting

32 kHz frequency division

ratio selection

System clock selection

System clock frequency

division ratio switching

Pull-up MOS control

Interrupt frame period selection

INT

/TOB

/EVNB

/SI/SO

SCK

/TOC

Timer C clock on/off

Timer A / time base

Timer B lock on/off

A/D clock on/off

Serial clock on/off

Timer A clock source selection

Timer B clock source selection

Timer C clock source selection

Reload on/off

Timer B output mode setting

Time C output mode selection

EVNB edge detection selection

Timer B register (lower)

Timer B register (upper)

Timer C register (lower)

Timer C register (upper)

Serial data register (lower)

Serial data register (upper)

A/D data register (bit 5 to 2)
A/D data register (bit 9 to 6)

Serial transfer clock speed selection

/SI/SO PMOS control

SO idle H/L setting

Analog channel selection

A/D conversion time

A/D data register (bit 1, 0)

PortD

DCR

PortD

DCR

PortD

DCR

PortD

DCR

PortR0

DCR

PortR1

DCR

PortR1

DCR

PortR2

DCR

PortR2

DCR

PortR2

DCR

PortR7

DCR

PortR7

DCR

PortR7

DCR

PortR7

DCR

PortD

DCR

PortD

DCR

PorD

DCR

PortD

DCR

PortD

DCR

PortD

DCR

Notes: *1 Applies to HD404374 Series.

*2 Applies to HD404374, HD404384, and HD404389 Series.

Not used

Not used
Not used

Not used

Figure 5 Special Function Register Area

HD404374/HD404384/HD404389/HD404082/HD404084 Series

MR (0)

MR (1)

MR (2)

MR (3)

MR (4)

MR (5)

MR (6)

MR (7)

MR (8)

MR (9)

MR (10)

MR (11)

MR (12)

MR (13)

MR (14)

MR (15)

$040

$041

$042

$043

$044

$045

$046

$047

$048

$049

$04A

$04B

$04C

$04D

$04E

$04F

Level

$3FC

$3FD

$3FE

$3FF

1020

1021

1022

1023

Bit 3

Bit 2

Bit 1

Bit 0

$3FF

1,023

960

$3C0

(a) Memory registers

(b) Stack area

to PC

: Program counter

: Status flag

: Carry flag

Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Functional Description

Registers and Flags

The MCU has nine registers and two flags for CPU operations. they are shown in figure 7 and described
below.

Accumulator

B register

W register

X register

Y register

SPX register

SPY register

Carry flag

Status flag

Initial value: Undefined, R/W

Initial value: 1, no R/W

Program counter
Initial value: $0000,
no R/W

Stack pointer
Initial value: $3FF, no R/W

(A)

(B)

(W)

(X)

(Y)

(SPX)

(SPY)

(CA)

(ST)

(PC)

(SP)

Figure 7 Registers and Flags

Accumulator (A) and B register (B):
The accumulator and B register are 4-bit registers used to hold the result of an ALU operation, and for data
transfer to or from memory, an I/O area, or another register.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

W register (W), X register (X) and Y register (Y):
The W register is a 2-bit register, and the X and Y registers are 4-bit registers, used for RAM register
indirect addressing. The Y register is also used for D port addressing.

SPX register (SPX) and SPY register (SPY):
The SPX and SPY registers are 4-bit registers used as X register and Y register auxiliary registers,
respectively.

Carry flag (CA):
This flag holds ALU overflow when an arithmetic/logic instruction is executed. It is also affected by the
SEC, REC, ROTL, and ROTR instructions. The contents of the carry flag are saved to the stack when
interrupt handling is performed, and are restored from the stack by the RTNI instruction (but are not
affected by the RTN instruction).

Status flag (ST):
This flag holds ALU overflow when an arithmetic/logic or compare instruction is executed, and the result
of an ALU non-zero or bit test instruction. It is used as the branch condition for the BR, BRL, CAL, and
CALL instructions. The status flag is a latch-type flag, and does not change until the next arithmetic/logic,
compare, or bit test instruction is executed. After a BR, BRL, CAL, or CALL instruction, the status flag is
set to 1 regardless of whether the instruction is executed or skipped. The contents of the status flag are
saved to the stack when interrupt handling is performed, and are restored from the stack by the RTNI
instruction (but are not affected by the RTN instruction).

Program counter (PC):
This is a 14-bit binary counter that holds ROM address information.

Stack pointer (SP):
The stack pointer is a 10-bit register that holds the address of the next save space in the stack area. The
stack pointer is initialized to $3FF by an MCU reset. The stack pointer is decremented by 4 each time data
is saved, and incremented by 4 each time data is restored. The upper 4 bits of the stack pointer are fixed at
1111, so that a maximum of 16 stack levels can be used.

There are two ways in which the stack pointer is initialized to $3FF: by an MCU reset as mentioned above,
or by resetting the RSP bit with the REM or REMD instruction.

Reset

An MCU reset is performed by driving the

RESET pin low. At power-on, and when subactive mode,

watch mode, or stop mode is cleared,

RESET should be input for at least tRC to provide the oscillation

settling time for the oscillator.In other cases, the MCU is reset by inputting

RESET for at least two

instruction cycles.

Table 1 shows the areas initialized by an MCU reset, and their initial values.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Table 1 (1) Initial Values after MCU Reset

Item

Abbr.

Initial
value

Contents

Program counter

(PC)

$0000

Program executed from ROM start address

Status flag

(ST)

Branching by conditional branch instruction enabled

Stack pointer

(SP)

$3FF

Stack level is 0

Interrupt

Interrupt enable flag

(IE)

All interrupts disabled

flags/ mask Interrupt request flag

(IF)

No interrupt requests

Interrupt mask

(IM)

Interrupt requests masked

I/O

Port data register

(PDR)

All bits 1 "1" level output possible

Data control registers

(DCD0 ~ 2)

All bits 0 Output buffer off (high impedance)

Data control registers

(DCR0

DCR1

DCR2

�

DCR2

DCR7

�

DCR7

)

All bits 0

Port mode register 0

(PMR0)

---0

See port mode register 0 section

Port mode register 1

(PMR1)

---0

See port mode register 1 section

Port mode register 2

(PMR2)

0--0

See port mode register 2 section

Port mode register 3

(PMR3)

0000

See port mode register 3 section

Timers

Timer mode register A

(TMA)

0000

See timer mode register A section

Timer mode register B1

(TMB1)

0000

See timer mode register B1 section

Timer mode register B2

(TMB2)

-000

See timer mode register B2 section

Timer mode register C1

(TMC1)

0000

See timer mode register C1 section

Timer mode register C2

(TMC2)

-0--

See timer mode register C2 section

Prescaler S

(PSS)

$000

Prescaler W

(PSW)

$00

Timer/counter A

(TCA)

$00

Timer/counter B

(TCB)

$00

Timer/counter C

(TCC)

$00

Timer write register B

(TWBU,L)

$X0

Timer write register C

(TWCU,L)

$X0

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Table 1 (2) Initial Values after MCU Reset

Item

Abbr.

Initial
value

Contents

Serial
interface

Serial mode register 1

(SMR1)

0000

See serial mode register 1 section

Serial mode register 2

(SMR2)

-0X-

See serial mode register 2 section

Serial data register

(SRU,L)

$XX

Octal counter

000

A/D
converter

A/D mode register

(AMR)

0000

See A/D mode register section

A/D data register U

(ADRU)

0111

See A/D data register section

A/D data register M

(ADRM)

1111

A/D data register L

(ADRL)

11- -

Bit

Low speed on flag

(LSON)

See low-power mode section

registers

Watchdog timer on flag

(WDON)

See timer C section

A/D start flag

(ADSF)

See A/D converter section

Direct transfer on flag

(DTON)

See low-power mode section

Gear enable flag

(GEF)

See system clock gear function

Others

Miscellaneous register

(MIS)

0-00

See low-power mode and input/output sections

System clock select
register

(SSR)

0000

See low-power mode and oscillator circuit sections

Module standby register 1

(MSR1)

--00

See timer section

Module standby register 2

(MSR2)

--00

See serial interface and A/D converter sections

Notes: 1. The state of registers and flags other than those listed above after an MCU reset is shown in

table 1 (3).

2. X: Indicates invalid value, - indicates that the bit does not exist.

Table 1 (3) Initial Values after MCU Reset

Item

Abbr.

After Stop Mode Clearance by

After Other MCU Reset

Carry flag

(CA)

Retain value immediately prior to

Value immediately prior to MCU reset is not

Accumulator

(A)

entering stop mode

guaranteed. Must be initialized by program.

B register

(B)

W register

(W)

X/SPX register (X/SPX)

Y/SPY register (Y/SPY)

RAM

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Interrupts

There are a total of seven interrupt sources, comprising wakeup input (

), external interrupts (

INT

timer/counter (timer A, timer B, timer C) interrupts, a serial interface interrupt, and an A/D converter
interrupt.

Each interrupt source is provided with an interrupt request flag, interrupt mask, and vector address, used for
storing and controlling interrupt requests. In addition, an interrupt enable flag is provided to control
interrupts as a whole.

Of the interrupt sources, the A/D converter and serial interface share the same vector address. Software
must therefore determine which of the interrupt sources is requesting an interrupt at the start of interrupt
handling.

Interrupt control bits and interrupt handling:
The interrupt control bits are mapped onto RAM addresses $000 to $003 and $023, and can be accessed by
RAM bit manipulation instructions. However, the interrupt request flags (IF) cannot be set by software.
When the MCU is reset, the interrupt enable flag (IE) and interrupt request flags (IF) are initialized to 0,
and the interrupt masks (IM) are initialized to 1.

Figure 8 shows a block diagram of the interrupt control circuit, table 2 shows interrupt priorities and vector
addresses, and table 3 lists the conditions for executing interrupt handling for each of the nine kinds of
interrupt source. When the interrupt request flag is set to 1 and the interrupt mask is cleared to 0, an
interrupt is requested. If the interrupt enable flag is set to 1 at this time, interrupt handling is started. The
vector address corresponding to the interrupt source is generated by the priority control circuit.

The interrupt handling sequence is shown in figure 9, and the interrupt handling flowchart in figure 10.
When an interrupt is accepted, execution of the previous instruction is completed in the first cycle. In the
second cycle, the interrupt enable flag (IE) is reset. In the second and third cycles, the contents of the carry
flag, status flag, and program counter are saved on the stack. In the third cycle, a jump is made to the
vector address and instruction execution is resumed from that address.

In each vector address area, a JMPL instruction should be written that branches to the start address of the
interrupt routine. In the interrupt routine, the interrupt request flag that caused interrupt handling must be
reset by software.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Table 3

Interrupt Processing and Activation Conditions

Interrupt Source

Interrupt Control Bit

INT

Timer A

Timer B

Timer C

A/D or
Serial

IFWU�

IMWU

IF0�

IM0

IFTA�

IMTA

IFTB�

IMTB

IFTC�

IMTC

IFAD�

IMAD

+IFS�

IMS

Note:

Operation is not affected whether the value is 0 or 1.

Instruction
execution*

Interrupt
acceptance

Save to stack
IE reset

Execution of JMPL instruction
at vector address

Save to stack
Vector address
generated

Execution of
instruction at
start address of
interrupt routine

Instruction cycle

Note: The stack is accessed and the IE reset after the instruction is executed, even if it is a 2cycle instruction.

Figure 9 Interrupt Sequence

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Interrupt enable flag (IE: $000,0):
The interrupt enable flag controls interrupt enabling/disabling of all interrupt requests as shown in table 4.
The interrupt enable flag is reset by interrupt handling and set by the RTNI instruction.

Table 4

Interrupt Enable Flag (IE: $000,0)

Interrupt Enable Flag (IE)

Interrupt Enabling/Disabling

Interrupts disabled

Interrupts enabled

Wakeup interrupt request flag (IFWU: $000,2):
The wakeup interrupt request flag (IFWU) is set by the detection of a falling edge in

input in active

mode, subactive mode,watch mode, or standby mode. In stop mode, when a falling edge is detected at the
wakeup pin, the MCU waits for the oscillation settling time, then switches to active mode. When a
transition is made from stop mode to active mode with IE set to 1 and IMWU cleared to 0, wakeup
interrupt handling is executed after the switch to active mode. The wakeup interrupt request flag (IFWU) is
not set in this case (table 5).

Table 5

Wakeup Interrupt Request Flag (IFWU: $000,2)

Wakeup Interrupt Request Flag
(IFWU)

Interrupt Request

No wakeup interrupt request

Wakeup interrupt request generated

Wakeup Interrupt Mask (IMWU: $000,3):
This bit masks an interrupt request by the wakeup interrupt request flag (table 6).

Table 6

Wakeup Interrupt Request Mask (IMWU: $000,3)

Wakeup Interrupt Mask (IMWU)

Interrupt Request

Wakeup interrupt request enabled

Wakeup interrupt request masked (held pending)

HD404374/HD404384/HD404389/HD404082/HD404084 Series

External interrupt request flag (IF0: $001, 0):
The external interrupt request flag is set by an

INT

input falling edge (table 7).

Table 7

External Interrupt Request Flag (IF0: $001, 0)

External Interrupt Request Flag
(IF0)

Interrupt Request

No external interrupt request

External interrupt request generated

External interrupt mask (IM0: $001, 1):
This bit masks an interrupt request by the external interrupt request flag (table 8).

Table 8

External Interrupt Mask (IM0: $001, 1)

External Interrupt Mask (IM0)

Interrupt Request

External interrupt request enabled

External interrupt request masked (held pending)

Timer A interrupt request flag (IFTA: $002,0):
The timer A interrupt request flag is set by timer A overflow output (table 9).

Table 9

Timer A Interrupt Request Flag (IFTA: $002,0)

Timer A Interrupt Request Flag
(IFTA)

Interrupt Request

No timer A interrupt request

Timer A interrupt request generated

Timer A interrupt mask (IMTA: $002,1):
This bit masks an interrupt request by the timer A interrupt request flag (table 10).

Table 10

Timer A Interrupt Mask (IMTA: $002,1)

Timer A Interrupt Mask (IMTA)

Interrupt Request

Timer A interrupt request enabled

Timer A interrupt request masked (held pending)

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Timer B interrupt request flag (IFTB: $002,2):
The timer B interrupt request flag is set by timer B overflow output (table 11).

Table 11

Timer B Interrupt Request Flag (IFTB: $002,2)

Timer B Interrupt Request Flag
(IFTB)

Interrupt Request

No timer B interrupt request

Timer B interrupt request generated

Timer B interrupt mask (IMTB: $002,3):
This bit masks an interrupt request by the timer B interrupt request flag (table 12).

Table 12

Timer B Interrupt Mask (IMTB: $002,3)

Timer B Interrupt Mask (IMTB)

Interrupt Request

Timer B interrupt request enabled

Timer B interrupt request masked (held pending)

Timer C interrupt request flag (IFTC: $003,0):
The timer C interrupt request flag is set by timer C overflow output (table 13).

Table 13

Timer C Interrupt Request Flag (IFTC: $003,0)

Timer C Interrupt Request Flag
(IFTC)

Interrupt Request

No timer C interrupt request

Timer C interrupt request generated (held pending)

Timer C interrupt mask (IMTC: $003,1):
This bit masks an interrupt request by the timer C interrupt request flag (table 14).

Table 14

Timer C Interrupt Mask (IMTC: $003,1)

Timer C Interrupt Mask (IMTC)

Interrupt Request

Timer C interrupt request enabled

Timer C interrupt request masked (held pending)

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Serial interrupt request flag (IFS: $023,2):
The serial interrupt request flag is set on completion of serial data transfer, or if data transfer is halted
midway (table 15).

Table 15

Serial Interrupt Request Flag (IFS: $023,2)

Serial Interrupt Request Flag (IFS) Interrupt Request

No serial interrupt request

Serial interrupt request generated

Serial interrupt mask (IMS: $023,3):
This bit masks an interrupt request by the serial interrupt request flag (table 16).

Table 16

Serial Interrupt Mask (IMS: $023,3)

Serial Interrupt Mask (IMS)

Interrupt Request

Serial interrupt request enabled

Serial interrupt request masked (held pending)

A/D interrupt request flag (IFAD: $003,2) (Applies to HD404374, HD404384, and HD404389 Series):
The A/D interrupt request flag is set on completion of A/D conversion (table 17).

Table 17

A/D Interrupt Request Flag (IFAD: $003,2)

A/D Interrupt Request Flag (IFAD) Interrupt Request

No A/D interrupt request

A/D interrupt request generated

A/D interrupt mask (IMAD: $003,3) (Applies to HD404374, HD404384, and HD404389 Series):
This bit masks an interrupt request by the A/D interrupt request flag (table 18).

Table 18

A/D Interrupt Mask (IMAD: $003,3)

Serial Interrupt Mask (IMAD)

Interrupt Request

A/D interrupt request enabled

A/D interrupt request masked (held pending)

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Operating Modes

The five operating modes shown in table 19 can be used for the MCU.

The function of each mode is shown in table 20, and the state transition diagram among each mode in
figure 11.

Table 19

Operating Modes and Clock Status

Mode Name

Active

Standby

Stop

Watch*

Subactive*

1, 3

Activation method

RESET

cancellation,
interrupt
request,

input in stop
mode
STOP/SBY
instruction in
subactive
mode (when
direct
transfer is
selected)

SBY
instruction

STOP
instruction
when
TMA3 = 0

STOP
instruction
when
TMA3 = 1

INT

/timer A

interrupt
request in
watch mode

Status

System oscillator

Stopped

Subsystem oscillator*

OP*

Cancellation method

RESET

input,
STOP/SBY
instruction

RESET

input,
interrupt
request

RESET

input,

input

RESET

input,

INT

/timer A

interrupt
request

RESET

input,

STOP/SBY
instruction

Notes: OP: implies in operation.

1. Applies to HD404374 Series.

2. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select

3. Subactive mode is an optional function; specify it on the fnction option list.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Table 20

Operation in Low-Power Dissipation Modes

Function

Stop Mode

Watch mode*

Standby Mode

Subactive Mode*

1, 3

CPU

Retained

RAM

Retained

Timer A

Stopped

Timer B

Stopped

Timer C

Stopped

Serial interface

Stopped *

A/D *

Stopped

I/O

Retained

Notes: OP: implies in operation.

1. Applies to HD404374 Series.

2. Transmission/Reception is activated if a clock is input in external clock mode. However,

interrupts stop.

3. Subactive mode is an optional function specified on the function option list.

4. Applies to HD404374, HD404384, and HD404389 Series.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Reset by

RESET

input or
watchdog timer

Reset

(TMA3=0)

(TMA3=1)

Timer A,

INT

interrupt

Standby mode

Active mode

SBY

instruction

interrupt

SBY

instruction

interrupt

STOP

instruction

(TMA3=1,LSON=0)

(TMA3=1,LSON=1)

osc

fcyc

SUB

�

CPU

�

CLK

�

PER

LSON

DTON

TMA3

Main oscillator frequency
Sub-oscillator frequency
(for realtime clock)
f

OSC

/32 or fOSC/4 (selected by

software)
fx/8
fx/8 or fx/4 (selected by software)
System clock
Clock for realtime clock
Peripheral function clock
Low speed on flag
Direct transfer on flag
Timer mode register A bit3

Timer A,

INT

interrupt

STOP

instruction

STOP
instruction

Stop mode

(TMA3=0,SSR3=0,LSON=0)

(TMA3=0,SSR3=1,LSON=0)

Subactive mode

DTON

Don't care

Transition Condition

STOP/SBY instruction

LSON

TMA3

Watch mode

osc

�

CPU

�

CLK

�

PER

: Stop
: Stop
: Stop
: Stop
: Stop

osc

�

CPU

�

CLK

�

PER

: Active
: Active
: fcyc
: fcyc
: fcyc

osc

�

CPU

�

CLK

�

PER

: Stop
: Active
: Stop
: Stop
: Stop

osc

�

CPU

�

CLK

�

PER

: Active
: Active
: Stop
: fcyc
: fcyc

osc

�

CPU

�

CLK

�

PER

: Stop
: Active
: f

SUB

: fw
: f

SUB

osc

�

CPU

�

CLK

�

PER

: Active
: Active
: fcyc
: fw
: fcyc

osc

�

CPU

�

CLK

�

PER

: Active
: Active
: Stop
: fw
: fcyc

osc

�

CPU

�

CLK

�

PER

: Stop
: Active
: Stop
: fw
: Stop

osc

�

CPU

�

CLK

�

PER

: Stop
: Active
: Stop
: fw
: Stop

Note: Watch mode and subactive mode apply to HD404374 Series.

Figure 11 MCU Status Transitions

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Active mode:
In active mode all functions operate. In this mode, the MCU operates on clocks generated by the OSC

and

OSC

oscillator circuits.

Standby mode:
In standby mode the oscillators continue to operate but clocks relating to instruction execution halt. As a
result, CPU operation stops, and registers, RAM, and the D port/R port set for output retain their state
immediately prior to entering standby mode. Interrupts, timers, the serial interface, and other peripheral
functions continue to operate.

Power consumption is lower than in active mode due to the halting of the CPU.

The MCU is switched to standby mode by executing the SBY instruction in active mode. Standby mode is
cleared by

RESET input or an interrupt request. When standby mode is cleared by RESET input, an MCU

reset is performed. When standby mode is cleared by an interrupt request, the MCU enters active mode
and executes a instruction following the SBY instruction. After executing the instruction, if the interrupt
enable flag is set to 1, interrupt handling is executed; if the interrupt enable flag is cleared to 0, the interrupt
request is held pending and normal instruction execution is continued.

MCU operation flowchart is shown in figure 12.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Stop mode:
In stop mode, all MCU function stop except that states prior to entry into stop mode are retained. This
mode thus has the lowest power consumption of all operating mode.

In stop mode, the OSC

and OSC

oscillators stop. Bit 3 (SSR3) of the system clock select register (SSR:

$004) (figure 22) can be used to select the active (= 0) or stopped (= 1) state for the X1 and X2 oscillators.

The MCU is switched to stop mode by executing a STOP instruction while bit 3 (TMA3) of timer mode
register A (TMA: $00F) (figure 33) is cleared to 0 in active mode. Stop mode is cleared by

RESET or WU

input. When stop mode is cleared by

RESET, the RESET signal should be input for at least the oscillation

settling time (tRC) (see "AC Characteristics") shown in figure 13. Then, the MCU is initialized and starts
instruction execution from the start (address 0) of the program (IE = 0, IMWU = 0). If IE is set before
entering stop mode (IE = 1, IMWU = 0), wakeup interrupt handling is executed after the transition to active
mode.

When the MCU detects a falling edge at

in stop mode, it automatically waits for the oscillation

settling time, then switches to active mode. After the transition to active mode, the MCU resumes program
execution from the instruction following the STOP instruction.

If stop mode is cleared by wakeup input, RAM data and registers retain their values prior to entering stop
mode.

Stop mode

Oscillator

Internal clock

RESET

STOP instruction executed

res

(At least oscillation settling time (t

))

Figure 13 Timing Chart for Clearing Stop Mode by RESET Input

Note:

If stop mode is cleared by wakeup input when an external clock is used as the system clock
(OSC1), the subclock should not be stopped in stop mode.

Watch mode ( Applies to HD404374 Series) :
In watch mode, the realtime clock function (timer A) and LCD function using the X1 and X2 oscillators
operate, but other functions stop. This mode thus has the second lowest power consumption after stop
mode, and is useful for performing realtime clock display only.

In watch mode, the OSC

and OSC

oscillators stop but the X1 and X2 oscillators continue to operate.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

The MCU is switched to watch mode by executing a STOP instruction while TMA3 = 1 in active mode, or
by executing a STOP/SBY instruction in subactive mode.

Watch mode is cleared by

RESET input or an INT

,timer A or

interrupt request. For

RESET input,

refer to the section on stop mode. When watch mode is cleared by an

INT

, timer A or

W U

interrupt

request, the mode transition depends on the value of the LSON bit: the MCU enters active mode if LSON =
0, and enters subactive mode if LSON = 1. In the case of a transition to active mode, interrupt request
generation is delayed to secure the oscillation settling time: the delay is the tRC set time for the timer A
interrupt, and, for the

INT

interrupt or

interrupt, Tx (T + t

< Tx < 2T + t

) if bit 1 and 0 (MIS1,

MIS0) of the miscellaneous register are set to 00, or Tx (t

< Tx < T + t

) if MIS1 and MIS0 are set to 01

or 10 (figures 14 and 15). Other operations when the transition is made are the same as when watch mode
is cleared (figure 12).

Subactive mode ( Applies to HD404374 Series):
In subactive mode, the OSC

and OSC

oscillator circuits stop and the MCU operates on clocks generated

by the X1 and X2 oscillator circuits. In this mode, functions other than the A/D converter operate, but
since the operating clocks are slow, power consumption is the lowest after watch mode.

A CPU instruction processing speed of 244

�

s or 122

�

s can be selected according to whether bit 2 (SSR2)

of the system clock select register (SSR: $004) is set to 1 or cleared to 0. The value of the SSR2 bit should
be changed (0

1 or 1

0) only in active mode. If the value is changed in subactive mode, the MCU may

operate incorrectly.

Subactive mode is cleared by executing a STOP/SBY instruction. A transition is then made to either watch
mode or active mode according to the value of the low speed on flag (LSON: $020,0) and the direct
transfer on flag (DTON: $020,3).

Subactive mode is a function option, and should be specified in the function option list.

Interrupt frame ( Applies to HD404374 Series):
In watch mode and subactive mode, �

CLK

is supplied to the timer A,

, and

INT

acceptance circuits.

Prescaler W and timer A operate as time bases, and generate interrupt frame timing. Either of two values
can be selected for the interrupt frame period, T, by means of the miscellaneous register (MIS: $005)
(figure 15).

In watch mode and subactive mode, the timing for generation of timer A,

INT

and

interrupts is

synchronized with the interrupt frame. Except for the case of an active mode transition, the interrupt strobe
timing is used for interrupt request generation. Timer A generates overflow and interrupt requests at the
interrupt strobe timing.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Watch mode

Oscillation
stabilization
period

Active mode

Interrupt
strobe

INT

Interrupt
request generation

T: Interrupt frame period
t

: Oscillation stabilization period

Only in case of
transition to active
mode

Note: If the time from the fall of the

INT

signal until the interrupt is accepted and

active mode is entered and is designated T

, then T

will be in the following range :

T+t

2T+t

(MIS1, MIS0=00)

T+t

(MIS1, MIS0=01 or 10)

Figure 14 Interrupt Frame

Miscellaneous Register (MIS: $005)

Bit

Read/Write

Reset

Bit name

MIS3

Not used*

MIS1*

MIS0*

Interrupt Frame

period T(

Oscillation Settling

Time t

(

MIS1

MIS0

0.24414

3.90625

0.12207(0.24414)*

7.8125

31.25

Oscillator Circuit

Condition

External clock input, CR oscillation frequency

Ceramic resonator

Crystal resonator

Not used

Notes: *1. Applies to HD404374 series.
*2. T and t

values are for use of a 32.768 kHz crystal oscillator at the X1-X2 pins.

*3. This value applies only in case of direct transition operation.
*4. Must always be cleared to 0. Setting to 1 will cause incorrect operation.

See pull-up
MOS control,
figure 30

Figure 15 Miscellaneous Register (MIS)

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Direct transition from subactive to active mode (Applies to HD404374 Series):
A direct transition can be made from subactive mode to active mode by controlling the direct transfer on
flag (DTON: $020,3) and low speed on flag (LSON: $020,0). The procedure is shown below.

(a) Set LSON = 0 and DTON = 1 in subactive mode.

(b) Execute a STOP or SBY instruction.

automatically switches from subactive mode to active mode (figure 16).

Notes: 1. The DTON flag ($020,3) can be set in only subactive mode. It is always in the reset state in

active mode.

2. The condition for transition time T

from the subactive mode to active mode is as follows:

< T

< T + t

Subactive mode

STOP/SBY
instruction execution

MCU internal
processing time

Oscillation
stabilization time

Active mode

(Set LSON =0, DTON =1)

Interrupt strobe

Direct transition
completion timing

T: Interrupt frame period
t

: Oscillation settling time

: Direct transition time

Figure 16 Direct Transition Timing

MCU operation sequence:
The MCU operates in accordance with the flowchart shown in figure 17.

RESET input is asynchronous

input, and the MCU immediately enters the reset state upon

RESET input, regardless of its current state.

In the low-power mode operation sequence, if a STOP/SBY instruction is executed while the IE flag is
cleared and the interrupt flag is set, releasing the relevant interrupt mask, the STOP/SBY instruction is
canceled (regarded as NOP) and the next instruction is executed. Therefore, when executing a STOP/SBY
instruction, all interrupt flags must be cleared, or interrupts masked, beforehand.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Usage notes (Applies to HD404374 Series):
In watch mode and subactive mode, an interrupt will not be detected correctly if the

INT

high or

low-level period is shorter than the interrupt frame period.

The MCU's edge sensing method is shown in figure 18. The MCU samples the

I NT

and

signals at

regular intervals, and if consecutive sampled values change from high to low, it determines that a falling
edge has been generated.

Interrupt detection errors occur since this sampling is performed at the interrupt frame period. If the high-
level period of the

INT

signal is within an interrupt frame, as shown in figure 19 (a), the signal

will be low at point A and point B, with the result that the falling edge will not be recognized. Similarly, If
the low-level period of the

INT

signal is within an interrupt frame, as shown in figure 19 (b), the

signal will be high at point A and point B, with the result that the falling edge will not be recognized.

In watch mode and subactive mode, therefore, ensure that the high-level and low-level periods of the

INT

and

signals is at least as long as the interrupt frame period.

INT

Sampling

High

Low

Figure 18 Edge Sensing Method

INT

Interrupt frame

Point A: Low

Point B: Low

INT

Interrupt frame

Point A: High

Point B: High

(a) High-level mode

(b) Low-level mode

Figure 19 Sampling Examples

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Internal Oscillator Circuit

Figure 20 shows the clock pulse generator circuit. As shown in table 21, a ceramic oscillator or crystal
oscillator can be connected to OSC1 and OSC2, and a 32.768 kHz crystal oscillator can be connected to X1
and X2. External clock operation is possible for the system oscillator. CR oscillation for system oscillator
is possible. CR oscillation function is optional. Set bit 1 (SSR1) of the system clock select register (SSR:
$004) according to the frequency of the oscillator connected to OSC1 and OSC2 (figure 22).

Note:

If the setting of bit 1 in the system clock select register does not match the frequency of the system
oscillator, the subsystem using 32.768 kHz oscillation will not operate correctly in the HD404374
Series.

Also, the CR oscillation frequency differs depending on the operating voltage and resistance value. Set bit
1 of the system clock select register to match the operating frequency. Note that if the frequency being used
does not match the setting of bit 1 of the system clock select register, subsystems using the 32.768 kHz
oscillation frequency will not operate correctly.

OSC

LSON

System

clock

selection

circuit

OSC

System

oscillator

1/4 or 1/32

division

circuit*

Timing

generation

circuit

OSC

cyc

Sub

system

clock

oscillator

1/8 or 1/4

division

circuit*

Timing

generator

circuit

SUB

subcyc

1/8

division

circuit

Timing

generation

circuit

wcyc

�

CPU

�

PER

CPU

�ROM

�RAM
� Registers, flags

�I/O

Peripheral

functions

Interrupts

TMA3 bit

Timer A

interrupts

Time
base
clock

selection

circuit

�

CLK

Notes: The division ratio can be selected by setting bit 0 or bit 2 in the system clock select register
(SSR:$004).

HD404374 series

Figure 20 Clock Pulse Generator Circuit

HD404374/HD404384/HD404389/HD404082/HD404084 Series

System Clock Gear Function

The MCU has a built-in system clock gear function that allows the system clock divided by 4 or by 32 to be
selected by software for the instruction execution time. Efficient power consumption can be achieved by
operating at the divided-by-4 rate when high-speed processing is needed, and at the divided-by-32 rate at
the other times. Figure 21 shows the system clock conversion method.

System clock conversion from division-by-4 to division-by-32 is performed as follows. First, make the
division-by-32 setting (SSR0 write), then set the gear enable flag (GEF: $021,3). This flag is used to
distinguish between gear conversion and a transition to standby mode. Next, execute an SBY instruction.
When the gear enable flag is not set, standby mode is entered; when this flag is set, gear conversion mode
is entered. In this case a transition is made to standby mode for the duration of the gear conversion, but
after the synchronization time has elapsed, a transition is made automatically to active mode. As soon as
the transition is made to active mode, the gear enable flag is reset.

The same procedure is used for conversion from division-by-32 to division-by-4.

Clear all interrupts, then disable interrupts, before carrying out gear conversion. Incorrect operation may
result if an interrupt is generated during gear conversion.

Division-by-32 setting (SSR0 = 1)

Set gear enable flag

Execute SBY instruction

Execute next instruction

Synchronization time

Division-by-4 setting (SSR0 = 0)

Set gear enable flag

Execute SBY instruction

Execute next instruction

Synchronization time

Figure 21 System Clock Division Ratio Conversion Flowchart

HD404374/HD404384/HD404389/HD404082/HD404084 Series

System clock select register (SSR: $004)

Make sure to set bit 3 of the system clock select register to 1 if the HD404374 series is being used without
the subsystem clock, and on the HD404384, HD404389, HD404082, and HD404084 series. The microcomputer
will malfunction if the setting is not 1.

Bit

Read/Write

Initial value on reset

Bit name

SSR3

SSR2*

SSR1*

SSR0

System clock division ratio switch

Division-by-4 (f

cyc

- f

OSC

/4)

Division-by-32 (f

cyc

- f

OSC

/32)

System clock division ratio switch

osc

=0.4�1.0MHz

osc

=1.6�8.5MHz

Subsystem clock division ratio switch

SUB

=fx/8

SUB

=fx/4

(HD404374 Series)

Subsystem clock operates in stop mode

Subsystem clock stops in stop mode

Note: * Applies to HD404374 Series.

The CR oscillation frequency differs depending on the operating voltage and resistance value.
Set SSR1 to match the operating frequency. Note that if the frequency being used does not
match the SSR1 setting, subsystems using the 32.768 kHz oscillation frequency will not
operate correctly.

Subsystem clock stop setting

This bit must be set to 1 following power-on and reset if the HD404374 series is being
used without the subsystem clock, and on the HD404384, HD404389, HD404082, and
HD404084 series. If it is set to 0 (the initial value), malfunctioning may occur in the stop
mode.

Figure 22 System Clock Select Register

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Table 21

Oscillator Circuit Examples

Circuit Structure

Circuit Constants

External clock
operation

External
oscillator

OSC

Open

Ceramic oscillator
(OSC

, OSC

)

OSC

GND

Ceramic
oscillator

Ceramic oscillator: CSA4.00MG (Murata)

=1M

�

20%

=24pF

�

20%

Crystal oscillator
(OSC

, OSC

)

OSC

GND

Crystal
oscillator

=1M

�

20%

=10�20pF

�

20%

CR oscillator*

(OSC

, OSC

)

OSC

=20k

�

Crystal oscillator
(X1, X2)
HD404374 Series

GND

Crystal
oscillator

Crystal: 32.768 kHz: MX38T (Nihon Denpa
Kogyo)
C

=20pF

�

20%

Notes: 1. With a crystal or ceramic oscillator, circuit constants will differ depending on the resonator, stray

capacitance in the interconnecting circuit, and other factors. Suitable constants should be
determined in consultation with the resonator manufacturer.

2. Make the connections between the OSC

and OSC

pins (X1 and X2 pins) and external

components as short as possible, and ensure that no other lines cross these lines (see layout
example in figure 23).

3. When 32.768 kHz crystal oscillation is not used, fix the X1 pin at V

and leave the X2 pin open.

4. Applies to HD40C4372, HD40C4374, HD40C4382, HD40C4384, HD40C4388, HD40C4389,

HD40C4081, HD40C4082, HCD40C4082, HD40C4084, HCD40C4084, HD407C4374 and
HD407C4384.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Input/Output

The MCU has 20 input/output pins (D

to D

, R0, R1

, R1

, R2

, R7

to R7

). The features of these

pins are described below.

�

The four pins D

to D

are source large-current (10 mA max.) I/O pins.

�

The four pins D

to D

are sink large-current (15 mA max.) I/O pins.

�

I/O pins comprise pins (D

, R0

, R1

to R2

, R7

to R7

) that also have a peripheral function

(timer, serial interface, etc.). With these pins, the peripheral function setting has priority over the D port
or R port pin setting. When a peripheral function setting has been made for a pin, the pin function and
input/output mode will be switched automatically in accordance with that setting.

�

Selection of input or output for I/O pins, or selection of the port or peripheral function for pins
multiplexed as peripheral function pins, is performed by the program.

�

All output of the peripheral function pins are CMOS outputs. The SO pin and R2

port pin can be

designated as NMOS open-drain output by the program.

�

A reset clears peripheral function selection. And since the data control registers (DCD, DCR) are also
reset, input/output pins go to the high-impedance state.

�

Each I/O pin has a built-in pull-up MOS that can be turned on and off individually by the program.

Figure 24 shows the I/O buffer configuration, and table 22 shows I/O pin circuit configuration control by
the program.

Table 23 shows the circuit configuration of each I/O pin.

Pull-up
MOS

Pull-up control signal

Buffer control signal

Output data

Input data

PMOS

NMOS

Input control signal

MIS3

DCD, DCR

PDR

Figure 24 I/O Pin Circuit Configuration

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Table 22

Programmable I/O Circuits

MIS3 (bit 3 of MIS)

DCD,DCR

PDR

CMOS buffer

PMOS

NMOS

Pull-up MOS

Note:

-- : OFF

Table 23 Circuit Configurations of I/O Pins

Type

Circuit Configuration

Pins

I/O pins

Input control signal

MIS3

DCD, DCR

PDR

Pull-up control signal

Buffer control signal

Output data

Input data

-D

, R1

, R2

Input control signal

MIS3

DCR

PDR

Pull-up control signal

Buffer control signal

Output data

Input data

SMR22

�R7

Input control signal

Pull-up control signal

Buffer control signal

Output data

A/D input

A/D channel control signal

Input data

MIS3

DCR

PDR

-R7

-AN

Notes: In a reset, since the I/O control registers are reset, input/output pins go to the high-impedance state

and peripheral function selections are cleared.

1. Applies to HD404374, HD404384, and HD404389 Series.

2. Applies to HD404082 and HD404084 Series.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Table 23

Circuit Configurations of I/O Pins (cont)

Type

Circuit Configuration

Pins

Perip-
heral
function
pins

I/O pins

MIS3

PDR

Pull-up control signal

I/O control signal

Output data

Input data

SCK

Output
pins

MIS3

PDR

Pull-up control signal

PMOS control signal

Output data

SMR22

MIS3

PDR

Pull-up control signal

Output data

TOB, TOC

Input
pins

RESET

Input data

RESET

MIS3

PDR

etc.

INT

EVNB, SI

A/D Input

A/D channel control signal

, AN

Note:

In a reset, since the I/O control registers are reset, input/output pins go to the high-impedance state
and peripheral function selections are cleared.

1. Applies to HD404389 Series.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

D Port

The D port consists of 10 I/O pins that are addressed bit-by-bit.

Ports D

to D

are source large-current I/O pins, and ports D

to D

are sink large-current I/O pins.

The D port can be set and reset by the SED and RED instructions or the SEDD and REDD instructions.
Output data is stored in the port data register (PDR) for each pin. The entire D port can be tested by the TD
or TDD instruction.

The D port output buffer is turned on and off by the D port data control registers (DCD0 to DCD2: $030 to
$032). The DCD registers are mapped onto memory addresses (figure 25).

Port D

is multiplexed as interrupt input pin

INT

. Setting as interrupt pin is performed by bit 0 (PMR00)

of port mode register 0 (PMR0: $008) (figure 26).

Data control registers (DCD0�2 : $030�$032)

(DCR0�2, 7 : $034�$036, $03B)

Register Name

DCDn

DCRm

Bit

Read/Write

Reset

Bit name

Read/Write

Reset

Bit name

DCDn3

DCRm3

DCDn2

DCRm2

DCDn1

DCRm1

DCDn0

DCRm0

All bits

CMOS buffer off (high impedance)

CMOS buffer active

CMOS buffer control

Register Name

DCD0

DCD1

DCD2

DCR0

DCR1

DCR2

DCR7

Bit 3

Bit 2

Bit 1

Bit 0

Correspondence between each bit of DCD and DCR and ports

(n=0 to 2)

(m=0 to 2, 7)

Figure 25 Data Control Registers (DCD, DCR)

HD404374/HD404384/HD404389/HD404082/HD404084 Series

R Port

The R port consists of 10 I/O pins that are addressed in 4-bit units.

Input can be performed by means of the LAR and LBR instructions, and output by means of the LRA and
LRB instructions. Output data is stored in the port data register (PDR) for each pin.

The R port output buffer is turned on and off by the R port data control registers (DCR0 to DCR2, DCR7:
$034 to $036, $03B). The DCR registers are mapped onto memory addresses (figure 25).

Port R0

is multiplexed as wakeup input pin

. Setting of this pin as peripheral function pins is

performed by port mode register 1 (PMR1: $009) (figure 27).

Port R1

is multiplexed as peripheral function pin EVNB. Setting of this pin as peripheral function pins is

performed by bit 0 (PMR20) of port mode register 2 (PMR2: $00A) (figure 28).

Ports R1

and R2

are multiplexed as peripheral function pins TOB, and TOC, respectively. Setting of

these pins as peripheral function pins is performed by bits 3 (PMR23) of port mode register 2 (PMR2:
$00A) and bit 0 (PMR30) of port mode register 3 (PMR3: $00B)(figures 28 and 29).

Ports R2

and R2

are multiplexed as peripheral function pins

SCK and SI/SO, respectively. Setting of

these pins as peripheral function pins is performed by bits 1 to 3 (PMR31 to PMR33) of port mode register
3 (PMR3: $00B) (figure 29).

Ports R7

to R7

are multiplexed as peripheral function pins AN

to AN

(HD404374, HD404384, and

HD404389 Series only). Setting of these pins as peripheral function pins is performed by bits 1 to 3
(AMR1 to AMR3) of the A/D mode register (AMR: $028) (see figure 64 in section 8, A/D Converter).

Port mode register 0 (PMR0: $008)

Bit

Read/Write

Initial value on reset

Bit name

Not used

PMR00

PMR00

/INT

pin mode selection

INT

Figure 26 Port Mode Register 0 (PMR0: $008)

HD404374/HD404384/HD404389/HD404082/HD404084 Series

/TOC pin mode selection

TOC

Bit

Read/Write

Initial value on reset

Bit name

PMR33

PMR32

PMR32

PMR33

/SI/SO pin mode selection

PMR31

PMR31

/SCK pin mode selection

SCK

PMR30

PMR30

Port mode register 3 (PMR3: $00B)

: Don't care

Figure 29 Port Mode Register 3 (PMR3: $00B)

Pull-Up MOS Control

Program-controllable pull-ups MOS are incorporated in all I/O pins.

On/off control of all pull-ups MOS is performed by bit 3 (MIS3) of the miscellaneous register (MIS: $005)
and the port data register (PDR) for each pin, enabling the pull-up MOS to be turned on or off
independently for each pin (table 22, figure 30).

Except for analog input multiplexed pins, the pull-up MOS on/off setting can be made independent of the
setting as an on-chip supporting module pin.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Bit

Read/Write

Initial value on reset

Bit name

MIS3

Not used

MIS1

MIS0

selection

(See figure 15 in the

Operating Modes section)

Miscellaneous register (MIS: $005)

Bit 2 of the miscellaneous register must always be set to 0. The microcomputer will malfunction
if it is set to 1.

MIS3

pull-up MOS control

All pull-ups MOS off

pull-up MOS active

Note: 1. This bit must always be set to 0. The microcomputer will malfunction if it is set to 1.

MIS2

Setting bit2

Set to 0

Use prohibited

Figure 30 Miscellaneous Register (MIS:$005)

Handling of I/O Pins Not Used by User System

If I/O pins that are not used by the user system are left floating, they may generate noise that can result in
chip malfunctions. Therefore, the pin potential must be fixed.

In this case, pull the pins up to V

with the built-in pull-up MOS or with an external resistor of

approximately 100 k

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Prescalers

The MCU has the following prescalers, S and W (HD404374 Series).

The operating conditions for each prescaler are shown in table 24, and the output supply destinations in
figure 31.

Timer A to C input clocks other than external events, and serial transfer clocks other than external clocks
are selected from the prescaler outputs in accordance with the respective mode register.

Prescaler Operation

Prescaler S (PSS):
Prescaler S is an 11-bit counter that has the system clock as input. When the MCU is reset, prescaler S is
reset to $000, then divides the system clock. Prescaler S operation is stopped by a reset by the MCU, and
in stop mode and watch mode

. It does not stop in any other modes.

Prescaler W (PSW) (HD404374 Series):
Prescaler W is a counter that has a clock divided from the X1 input (32 kHz crystal oscillation) as input.

When the MCU is reset, prescaler W is reset to $00, then divides the input clock. Prescaler W can also be
reset by software.

Table 24

Prescaler Operating Conditions

Prescaler

Input Clock

Reset Conditions

Stop Conditions

Prescaler S

System clock in active and
standby modes, subsystem
clock in subactive mode*

MCU reset, stop mode
clearance

MCU reset, stop mode,
watch mode*

Prescaler W

Clock obtained by division-
by-8 of 32.768 kHz
oscillation by subsystem
clock oscillator

MCU reset, software*

MCU reset, stop mode

Notes: 1

Applies to HD404374 Series

If bits TMA3 to TMA1 in timer mode register A (TMA) are all set to 1, PSW is cleared to $00.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Timers

The MCU incorporates three timers, A to C.

�

Timer A: Free-running timer

�

Timer B: Multifunctional timer

�

Timer C: Multifunctional timer

Timer A is an 8-bit free-running timer. Timers B and C are 8-bit multifunctional timers; Each one of their
have the functions shown in table 25 and their operating mode can be set by the program.

Table 25

Timer Functions

Functios

Timer A

Timer B

Timer C

Clock source

Prescaler S

Available

Prescaler W*

Available

External event

Available

Timer functions

Free-running

Available

Time-base*

Available

Event counter

Available

Reload

Available

Watchdog

Available

Timer outputs

Toggle

Available

PWM

Available

Note:

-- implies not available

* Applies to HD404374 Series

Timer A

Timer A Functions

Timer A has the following functions.

�

Free-running timer

�

Realtime clock time base

The block diagram of timer A is shown in figure 32.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

1/4

1/2

32.768-kHz
oscillator

System
clock

Data bus

Clock line

Signal line

Prescaler W

(PSW)

Selector

Prescaler S (PSS)

Selector

Internal data bus

Timer A interrupt

request flag

(IFTA)

Clock

Overflow

Timer

counter A

(TCA)

Timer mode

(TMA)

2 f

1/2 t

Wcyc

�

PER

128

512

1024

2048

� � � � � � � �

� � � �

HD404374 Series

Figure 32 Timer A Block Diagram

Timer A Operation

Free-running timer operation:
The timer A input clock is selected by timer mode register A (TMA: $00F).

Timer A is reset to $00 by an MCU reset, and counts up each time the input clock is input. When the input
clock is input after the timer A value reaches $FF, overflow output is generated, and the timer A value
becomes $00. The generated overflow output sets the timer A interrupt request flag (IFTA: $002,0). Timer
A continues counting up after the count value returns to $00, so that an interrupt is generated regularly
every 256 input clock cycles.

Realtime clock time base operation (HD404374 Series):
Timer A can be used as the realtime clock time base by setting bit 3 (TMA3) of timer mode register A to 1.
As the prescaler W output is input to timer/counter A, interrupts are generated with accurate timing using
the 32.768 kHz crystal oscillator as the basic clock.

When timer A is used as the realtime clock time base, prescaler W and timer/counter A can be reset to $00
by the program.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Bit

Read/Write

Initial value on reset

Bit name

TMA3*

TMA2

TMA1

TMA0

TMA3*

TMA2

TMA1

TMA0

Source prescaler

PSS

PSW

Input clock period

2,048 t

cyc

1,024 t

cyc

512 t

cyc

128 t

cyc

32 t

cyc

8 t

cyc

4 t

cyc

2 t

cyc

32 t

wcyc

16 t

wcyc

8 t

wcyc

2 t

wcyc

1/2 t

wcyc

Operating mode

Timer A

mode

Time base

mode

Timer mode register A (TMA: $00F)

Not Used

PSW, TCA reset

x : Don't care

Notes : 1. t

wcyc

= 244.14

�

s (using 32.768 kHz crystal oscillator)

2. Timer/counter overflow output period (s) = input clock period (s)

�

256.

3. The division ratio must not be changed while time base mode is being used, as this

will result in an error in the overflow period.

4. Applies to HD404374 Series. In HD404384, HD404389, HD404082 and HD404084

Series, write as 0.

Figure 33 Timer Mode Register A (TMA)

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Timer B

Timer B Functions: Timer B has the following functions.

�

Free-running/reload timer

�

External event counter

�

Timer output operation (toggle output, PWM output)

The block diagram of timer B is shown in figure 34.

Timer B ineterrupt

request flag

(IFTB)

(TCBL)

(TCBU)

Timer read
register BU
(TRBU)

Internal data bus

Timer read

(TRBL)

Timer counter B

Timer write register B

(TWBL)

(TWBU)

Free-runnning/Reload control

Timer mode

(TMB1)

Timer mode

(TMB2)

Data bus

Clock line

Signal line

Selector

Overflow

Prescaler S

(PSS)

System

clock

�

128

�

512

�

2048

Timer output

control logic

Timer C clock source

Edge detection

logic

TOB

EVNB

�

PER

Figure 34 Timer B Block Diagram

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Timer B Operation

�

Free-running/reload timer:

Free-running/reload timer operation, the input clock source, and the prescaler division ratio are selected
by means of timer mode register B1 (TMB1).

Timer B is initialized to the value written to timer write register B (TWBL, TWBU) by software, and
counts up by 1 each time the input clock is input. When the input clock is input after the timer B value
reaches $FF, overflow output is generated. Timer B is then set to the value in timer write register B if
the reload timer function is selected, or to $00 if the free-running timer function is selected, and starts
counting up again.

Overflow output sets the timer B interrupt request flag (IFTB). This flag is reset by the program or by
an MCU reset.

For details, see figure 3, Interrupt Control Bit and Register Flag Area Configuration, and table 1, Initial
Values after MCU Reset.

�

External event counter operation:

When external event input is designated for the input clock, timer B operates as an external event
counter. When external event input is used, the R1

/EVNB pin is designated as the EVNB pin by port

mode register 2 (PMR2).

The external event detected edge for timer B can be designated as a falling edge, rising edge, or both
falling and rising edges in the input signal by means of timer mode register B2 (TMB2). If both falling
and rising edges are selected, the input signal falling and rising edge interval should be at least 2tcyc.

Timer B counts up by 1 each time a falling edge is detected in the signal input at the EVNB pin. Other
operations are the same as for the free-running/reload timer function.

�

Timer output operation:

With timer B, the R13/TOB pin is designated as the TOB pin by the setting of bit 3 of port mode
register 2 (PMR2), and toggle waveform output or PWM waveform output can be selected by timer
mode register B2 (TMB2).

Toggle output:

With toggle output, the output level is changed upon input of the next clock pulse after the timer B
value reaches $FF. Use of this function in combination with the reload timer allows a clock signal
with any period to be output, enabling it to be used as buzzer output. The output waveform is
shown in figure 35 (1).

PWM output:

With PWM output, variable-duty pulses are output. The output waveform is as shown in figure 35
(2), according to the contents of timer mode register B1 (TMB1) and timer write register B (TWBL,
TWBU). When the waveform is output with bit 3 (TMB13) of timer mode register B1 cleared to 0,
the write to timer write register B to change the duty is effective from the next frame, whereas if the
waveform is output with the TMB13 bit set to 1 (reload setting), the next frame is output
immediately after the timer write register write.

�

Module standby:

With timer B, the supply of the system clock to the timer/counter can be halted by setting bit 0 of
module standby register 1 (MSR1: $00D) to 1. In the module standby state, the mode register value is
retained but the counter value is not guaranteed.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Timer B Registers

Timer B operation setting and timer B value reading/writing is controlled by the following registers.

Timer mode register B1 (TMB1: $010)

Timer mode register B2 (TMB2: $011)

Timer write register B (TWBL: $012, TWBU: $013)

Timer read register B (TRBL: $012, TRBU: $013)

Port mode register 2 (PMR2: $00A)

Module standby register 1 (MSR1: $00D)

�

Timer mode register B1 (TMB1: $010):

Timer mode register B1 (TMB1) is a 4-bit write-only register, used to select free-running/reload timer
operation and the input clock as shown in figure 36.

Timer mode register B1 (TMB1) is reset to $0 by an MCU reset:

A modification of timer mode register B1 (TMB1) becomes effective after execution of two instructions
following the timer mode register B1 (TMB1) write instruction. The program must provide for timer B
initialization by writing to timer write register B (TWBL, TWBU) to be executed after the post-
modification mode has become effective.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

TMB13

TMB12

TMB11

TMB10

Bit

Read/Write

Initial value on reset

Bit name

TMB12

TMB11

TMB10

Input clock period and input clock source

2,048 t

cyc

512 t

cyc

128 t

cyc

32 t

cyc

8 t

cyc

4 t

cyc

2 t

cyc

/EVNB (external event input)

TMB13

Free-running/reload timer

Free-running timer

Reload timer

Timer mode register B1 (TMB1: $010)

Figure 36 Timer Mode Register B1 (TMB1)

�

Timer mode register B2 (TMB2: $011):

Timer mode register B2 (TMB2) is a 3-bit write-only register, used to select the timer B output mode
and EVNB pin detected edge as shown in figure 37.

Timer mode register B2 (TMB2) is reset to $0 by an MCU reset.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

TMB20

EVNB pin detected edge

Not detected

Falling edge detection

Rising edge detection

Both rising and falling edge detection

TMB22

Timer B output waveform

Toggle output

PWM output

TMB21

Timer mode register B2 (TMB2: $011)

Bit

Read/Write

Initial value on reset

Bit name

TMB22

TMB21

TMB20

Figure 37 Timer Mode Register B2 (TMB2)

�

Timer write register B (TWBL: $012, TWBU:$013):

Timer write register B (TWBL, TWBU) is a write-only register composed of a lower digit (TWBL) and
an upper digit (TWBU) (figures 38 and 39).

The lower digit (TWBL) of timer write register B is reset to $0 by an MCU reset, while the upper digit
(TWBU) is undetermined.

Timer B can be initialized by writing to timer write register B (TWBL, TWBU). To write the data, first
write the lower digit (TWBL). The lower digit write does not change the timer B value. Next, write the
upper digit (TWBU). Timer B is then initialized to the timer write register B (TWBL, TWBU) value.
When writing to timer write register B (TWBL, TWBU) from the second time onward, if it is not
necessary to change the lower digit (TWBL) reload value, timer B initialization is completed by the
upper digit write alone.

TWBL3

TWBL2

TWBL1

TWBL0

Timer write register B (lower) (TWBL: $012)

Bit

Read/Write

Initial value on reset

Bit name

Figure 38 Timer Write Register B (Lower) (TWBL)

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Undetermined

TWBU3

Undetermined

TWBU2

Undetermined

TWBU1

Undetermined

TWBU0

Timer write register B (upper) (TWBU: $013)

Bit

Read/Write

Initial value on reset

Bit name

Figure 39 Timer Write Register B (Upper) (TWBU)

�

Timer read register B (TRBL: $012, TRBU: $013):

Timer read register B (TRBL, TRBU) is a read-only register composed of a lower digit (TRBL) and an
upper digit (TRBU) from which the value of the upper digit of timer B is read directly (figures 40 and
41).

First, read the upper digit (TRBU) of timer read register B. The current value of the timer B upper digit
is read and, at the same time, the value of the timer B lower digit is latched in the lower digit (TRBL) of
timer read register B. The timer B value is obtained when the upper digit (TRBU) of timer read register
B is read by reading the lower digit (TRBL) of timer read register B.

Undetermined

TRBL3

Undetermined

TRBL2

Undetermined

TRBL1

Undetermined

TRBL0

Timer read register B (lower) (TRBL: $012)

Bit

Read/Write

Initial value on reset

Bit name

Figure 40 Timer Read Register B (Lower) (TRBL)

Bit

Read/Write

Initial value on reset

Bit name

Undetermined

TRBU3

Undetermined

TRBU2

Undetermined

TRBU1

Undetermined

TRBU0

Timer read register B (upper) (TRBU: $013)

Figure 41 Timer Read Register B (Upper) (TRBU)

HD404374/HD404384/HD404389/HD404082/HD404084 Series

�

Port mode register 2 (PMR2: $00A):

Port mode register 2 (PMR2) is a write-only register used to set the function of the R1

/EVNB and

/TOB pins as shown in figure 42.

Port mode register 2 (PMR2) is reset to $0 by an MCU reset.

/EVNB pin mode selection

EVNB

Bit

Read/Write

Initial value on reset

Bit name

PMR23

PMR23

/TOB pin mode selection

TOB

Not used

PMR20

PMR20

Port mode register 2 (PMR2: $00A)

Figure 42 Port Mode Register 2 (PMR2: $00A)

�

Module standby register 1 (MSR1: $00D):

Module standby register 1 (MSR1) is a write-only register used to designate supply or stopping of the
clock to timer B as shown in figure 43.

Module standby register 1 (MSR1) is reset to $0 by an MCU reset.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Timer C Operation

�

Free-running/reload timer:

Free-running/reload timer operation, the input clock source, and the prescaler division ratio are selected
by means of timer mode register C1 (TMC1).

Timer C is initialized to the value written to timer write register C (TWCL, TWCU) by software, and
counts up by 1 each time the input clock is input. When the input clock is input after the timer C value
reaches $FF, overflow output is generated. Timer C is then set to the value in timer write register C
(TWCL, TWCU) if the reload timer function is selected, or to $00 if the free-running timer function is
selected, and starts counting up again.

Overflow output sets the timer C interrupt request flag (IFTC). This flag is reset by the program or by
an MCU reset.

For details, see figure 3, Interrupt Control Bit and Register Flag Area Configuration, and table 1, Initial
Values after MCU Reset.

�

16-bit timer operation:

When timer B overflow flag is selected as the clock source, timer C can be used as a 16-bit timer that
counts the timer B clock source pulses. In this case, since the timer B and timer C free-running/reload
settings are independent, the settings should be made to suit the purpose.

�

Watchdog timer operation:

By using the timer C overflow output, timer C can be used as a watchdog timer for detecting program
runaway. The watchdog timer is enabled when the watchdog on flag (WDON) is set to 1, and generates
an MCU reset when timer C overflows. Usually, timer C initialization is performed by the program
before the timer C value reaches $FF, so controlling program runaway.

�

Timer output operation:

With timer C, the R2

/TOC pin is designated as the TOC pin by setting bit 0 of port mode register 3

(PMR3) to 1, and toggle waveform output or PWM waveform output can be selected by timer mode
register C2 (TMC2).

Toggle output

The operation is similar to that for timer B toggle output.

PWM output

The operation is similar to that for timer B PWM output.

�

Module standby:

The operation is similar to that for timer B module standby.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Timer C Registers

Timer C operation setting and timer C value reading/writing is controlled by the following registers.

Timer mode register C1 (TMC1: $014)

Timer mode register C2 (TMC2: $015)

Timer write register C (TWCL: $016, TWCU: $017)

Timer read register C (TRCL: $016, TRCU: $017)

Port mode register 3 (PMR3: $00B)

Module standby register 1 (MSR1: $00D)

�

Timer mode register C1 (TMC1: $014):

Timer mode register C1 (TMC1) is a 4-bit write-only register, used to select free-running/reload timer
operation, the input clock, and the prescaler division ratio as shown in figure 45.

Timer mode register C1 (TMC1) is reset to $0 by an MCU reset.

A modification of timer mode register C1 (TMC1) becomes effective after execution of two instructions
following the timer mode register C1 (TMC1) write instruction. The program must provide for timer C
initialization by writing to timer write register C (TWCL, TWCU) to be executed after the post-
modification mode has become effective.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

�

Timer mode register C2 (TMC2: $015):

Timer mode register C2 (TMC2) is a 1-bit write-only register, used to select the timer C output mode as
shown in figure 46.

Timer mode register C2 (TMC2) is reset to $0 by an MCU reset.

TMC22

TMC22

Timer mode register C2 (TMC2: $015)

Bit

Read/Write

Initial value on reset

Bit name

Timer C output waveform

Toggle output

PWM output

Figure 46 Timer Mode Register C2 (TMC2)

�

Timer write register C (TWCL: $016, TWCU: $017):

Timer write register C (TWCL, TWCU) is a write-only register composed of a lower digit (TWCL) and
an upper digit (TWCU) (figures 47 and 48).

Timer write register C (TWCL, TWCU) operation is similar to that for timer write register B (TWBL,
TWBU).

Timer write register C (lower) (TWCL: $016)

TWCL3

TWCL2

TWCL1

TWCL0

Bit

Read/Write

Initial value on reset

Bit name

Figure 47 Timer Write Register C (Lower) (TWCL)

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Timer write register C (upper) (TWCU: $017)

Bit

Read/Write

Initial value on reset

Bit name

Undetermined

TWCU3

Undetermined

TWCU2

Undetermined

TWCU1

Undetermined

TWCU0

Figure 48 Timer Write Register C (Upper) (TWCU)

�

Timer read register C (TRCL: $016, TRCU: $017):

Timer read register C (TRCL, TRCU) is a read-only register composed of a lower digit (TRCL) and an
upper digit (TRCU) from which the value of the upper digit of timer C is read directly (figures 49 and
50).

Timer read register C (TRCL, TRCU) operation is similar to that for timer read register B (TRBL,
TRBU).

Timer read register C (lower) (TRCL: $016)

Bit

Read/Write

Initial value on reset

Bit name

Undetermined

TRCL3

Undetermined

TRCL2

Undetermined

TRCL1

Undetermined

TRCL0

Figure 49 Timer Read Register C (Lower) (TRCL)

Timer read register C (upper) (TRCU: $017)

Bit

Read/Write

Initial value on reset

Bit name

Undetermined

TRCU3

Undetermined

TRCU2

Undetermined

TRCU1

Undetermined

TRCU0

Figure 50 Timer Read Register C (Upper) (TRCU)

HD404374/HD404384/HD404389/HD404082/HD404084 Series

�

Port mode register 3 (PMR3: $00B):

Port mode register 3 (PMR3) is a write-only register used to set the function of the R2

/TOC pin as

shown in figure 51.

Port mode register 3 (PMR3) is reset to $0 by an MCU reset.

/TOC pin mode selection

TOC

Bit

Read/Write

Initial value on reset

Bit name

PMR33

PMR32

PMR32

PMR33

/SI/SO pin mode selection

PMR31

PMR31

SCK

pin mode selection

SCK

PMR30

PMR30

Port mode register 3 (PMR3: $00B)

: Don't care

Figure 51 Port Mode Register 3 (PMR3)

�

Module standby register 1 (MSR1: $00D):

Module standby register 1 (MSR1) is a write-only register used to designate supply or stopping of the
clock to timer C as shown in figure 43.

Module standby register 1 (MSR1) is reset to $0 by an MCU reset.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Serial Interface Operation

Selecting and changing serial interface operating mode:
The operating modes that can be selected for the serial interface are shown in table 26. The combination of
port mode register 3 (PMR3) values should be selected from this table. When the serial interface operating
mode is changed, the serial interface internal state must be initialized by writing to serial mode register 1
(SMR1).

Note : The serial interface is initialized by writing to serial mode register 1 (SMR1: $024). See figure 56

Serial Mode Register 1, for details.

Table 26

Serial Interface Operating Modes

PMR3

Bit3

Bit2

Bit1

Serial interface operating mode

Clock continuous output mode

Receive mode

Transmit mode

Note : * Don't care

Serial interface pin setting:
The R2

SCK pin and R2

/SI/SO pin are set by writing data to port mode register 3 (PMR3). See Serial

Interface Registers, for details.

Serial clock source setting:
The serial clock is set by writing data to serial mode register 1 (SMR1). See Serial Interface Registers, for
details.

Serial data setting:
Transmit serial data is set by writing data to the serial data register (SRL, SRU).

Receive serial data is obtained by reading the serial data register (SRL, SRU). Serial data is shifted by
means of the serial clock to perform input/output from/to an external device.

The output level of the SO pin is undetermined until the first data is output after a reset by the MCU, or
until high/low control is performed in the idle state.

Transfer control:
Serial interface operation is started by an STS instruction. The octal counter is reset to 000 by the STS
instruction, and is incremented by 1 on each rise of the serial clock. When 8 serial clock pulses have been
input, or if data transmission/reception is suspended midway, the octal counter is reset to 000, the serial
interrupt request flag (IFS) is set, and transfer is terminated.

The serial clock is selected by means of serial mode register 1 (SMR1). See figure 56.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Serial interface operating states:
The serial interface has the operating states shown in figure 53 in external clock mode and internal clock
mode.

STS instruction wait state

Serial clock wait state

Transfer state

Clock continuous output state (internal clock mode only)

�

STS instruction wait state

Upon MCU reset ((00) and (10) in figure 53), the serial interface enters the STS instruction wait state.
In the STS instruction wait state, the internal state of the serial interface is initialized. Even if the serial
clock is input at this time, the serial interface will not operate. When the STS instruction is executed
((01), (11)), the serial interface enters the serial clock wait state.

�

Serial clock wait state

The serial clock wait state is the interval from STS instruction execution until the first serial clock
falling edge. When the serial clock is input in the serial clock wait state ((02), (12)), the octal counter
begins counting, the contents of the serial data register (SRL, SRU) begin shifting, and the serial
interface enters the transfer state. However, if clock continuous output mode is selected in internal
clock mode, the serial interface enters the clock continuous output state ((17)) instead of the transfer
state.

If a write to serial mode register 1 (SMR1) is performed in the serial clock wait state, the serial interface
enters the STS instruction wait state ((04), (14)).

�

Transfer state

The transfer state is the interval from the first serial clock falling edge until the eighth serial clock rising
edge. In the transfer state, if an STS instruction is executed or if eight serial clocks have been input, the
octal counter is cleared to 000, and the serial interface makes a state transition. If an STS instruction is
executed ((05), (15)), the serial interface enters the serial clock wait state. After eight serial clocks have
been input, the serial interface enters the serial clock wait state ((03)) when in external clock mode, and
enters the STS instruction wait state ((13)) when in internal clock mode.

In internal clock mode, the serial clock stops after output of eight clocks.

If a write to serial mode register 1 (SMR1) is performed in the transfer state ((06), (16)), the serial
interface is initialized and enters the STS instruction wait state.

When the serial interface switches from the transfer state to another state, the octal counter is reset to
000 and the serial interrupt request flag (IFS) is set.

�

Clock continuous output state (internal clock mode only)

In the clock continuous output state, no receive or transmit operation is performed, and the serial clock
is only output from the

SCK pin. It is therefore effective in internal clock mode.

If the serial clock is input ((17)) when bit 3 (PMR33) of port mode register 3 (PMR3) is cleared to 0 and
the serial interface is in the serial clock wait state, a transition is made to the clock continuous output
state.

If a write to serial mode register 1 (SMR1) is performed in the clock continuous output state ((18)), the
serial interface enters the STS instruction wait state.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

STS instruction wait state

(octal counter ="000",

serial clock disabled)

MCU reset (00)

Serial clock wait state

(octal counter ="000")

Transfer state

(octal counter

"000")

SMR1 write (14)

STS instruction (11)

Serial clock (12)

serial clocks (03)

STS instruction (05)

(IFS

"1")

STS instruction (15)

(IFS

"1")

External clock mode

STS instruction wait state

(octal counter ="000",

serial clock disabled)

Serial clock wait state

(octal counter ="000")

Transfer state

(octal counter

"000")

SMR1 write (04)

STS instruction (01)

Serial clock (02)

SMR1 write (06)

(IFS

"1")

8 serial clocks (13)

SMR1 write (16)

(IFS

"1")

MCU reset (10)

Serial clock (17)

SMR1 write (18)

Clock continuous output state

(PMR33 ="0")

Internal clock mode

( ) Refer to the text for details on the circled numbers in the figure.

Figure 53 Serial Interface Operating States

HD404374/HD404384/HD404389/HD404082/HD404084 Series

State

SCK

pin (input)

SO pin

IFS

MSB

LSB

Undefined

Idle

Idle H/L setting

Dummy write to
cause state transition

Port setting

STS wait state

Serial clock
wait state

Transfer state

STS wait state

Serial clock
wait state

External clock setting

Idle H/L setting

(Flag reset by transfer
completion processing)

MCU reset

PMR3 write

SMR1 write

SMR2 write

SRL, SRU write

STS instruction

State

SCK

pin (output)

SO pin

IFS

MSB

LSB

Undefined

Idle H/L setting

Port setting

STS wait state

Serial clock
wait state

Transfer state

STS wait state

(Flag reset by transfer
completion processing)

MCU reset

PMR3 write

SMR1 write

SMR2 write

SRL, SRU write

STS instruction

(2) Internal clock mode

(1) External clock mode

External clock setting

Transmit data write

Idle H/L setting

Figure 54 Examples of Serial Interface Operation Sequence

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Serial clock error detection (external clock mode):

The serial interface will operate incorrectly in the transfer state if external noise results in unnecessary
pulses being added to the serial clock. Serial clock error detection in such cases is carried out as shown in
figure 55.

If more than eight serial clock pulses are input due to external noise while in the transfer state, at the eighth
clock pulse (including any external noise pulses), the octal counter is cleared to 000 and the serial interrupt
request flag (IFS) is set. At the same time, the serial interface exits the transfer state and enters the serial
clock wait state, but returns to the transfer state at the next regular clock pulse falling edge.

Meanwhile, in the interrupt handling routine, transfer end processing is performed, the serial interrupt
request flag is reset, and a dummy write is performed into serial mode register 1 (SMR1). The serial
interface then returns to the STS wait state, and the serial interrupt request flag (IFS) is set again. It is
therefore possible to detect a serial clock error by testing the serial interrupt request flag after the dummy
write to serial mode register 1.

Usage notes:

�

Initialization after register modification

If a port mode register 3 (PMR3) write is performed in the serial clock wait state or transfer state, a
serial mode register 1 (SMR1) write should be performed again to initialize the serial interface.

�

Serial interrupt request flag (IFS:$023, 2) setting

If a serial mode register 1 (SMR1) write or STS instruction is executed during the first low-level
interval of the serial clock in the transfer state, the serial interrupt request flag (IFS) will not be set. To
ensure that the serial interrupt request flag (IFS) is properly set in this case, programming is required to
make sure that the

SCK pin is in the 1 state (by executing an input instruction for the R2 port) before

executing a serial mode register 1 (SMR1) write or an STS instruction.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

100

Serial Interface Registers

Serial interface operation setting and serial data reading/writing is controlled by the following registers.

Serial mode register 1 (SMR1: $024)

Serial mode register 2 (SMR2: $025)

Serial data register (SRL: $026, SRU: $027)

Port mode register 3 (PMR3: $00B)

Module standby register 2 (MSR2: $00E)

Serial mode register 1 (SMR1: $024):

Serial mode register 1 (SMR1) has the following functions. See figure 56.

�

Serial clock selection

�

Prescaler division ratio selection

�

Serial interface initialization

The serial mode register 1 (SMR1) is a 4-bit write-only register, and is reset to $0 by an MCU reset.

A write to serial mode register 1 (SMR1) halts the supply of the serial clock to the serial data register (SRL,
SRU) and the octal counter, and resets the octal counter to 000. Therefore, if serial mode register 1
(SMR1) is written to during serial interface operation, data transmission/reception will be suspended and
the serial interrupt request flag (IFS) will be set.

A modification of serial mode register 1 (SMR1) becomes effective after execution of two instructions
following the serial mode register 1 (SMR1) write instruction. The program must therefore provide for the
STS instruction to be executed two cycles after the instruction that writes to serial mode register 1 (SMR1).

HD404374/HD404384/HD404389/HD404082/HD404084 Series

101

Serial mode register 1 (SMR1: $024)

SMR13 SMR12 SMR11 SMR10

SCK pin

Serial clock

source

Serial clock

(PSS division ratio

�

2 or 4)

Serial clock

cycle

Output

Input

Output

Input

PSS

System clock

External clock

PSS

System clock

External clock

PSS

(

�

PER

/2048)

�

(

�

PER

/512)

�

(

�

PER

/128)

�

(

�

PER

/32)

�

(

�

PER

/8)

�

(

�

PER

/2)

�

PER

(

�

PER

/2048)

�

(

�

PER

/512)

�

(

�

PER

/128)

�

(

�

PER

/32)

�

(

�

PER

/8)

�

(

�

PER

/2)

�

PER

4096 tcyc

1024 tcyc

256 tcyc

64 tcyc

16 tcyc

4 tcyc

tcyc

8192 tcyc

2048 tcyc

512 tcyc

128 tcyc

32 tcyc

8 tcyc

tcyc

Bit

Read/Write

Initial value on reset

Bit name

SMR13

SMR12

SMR11

SMR10

Figure 56 Serial Mode Register 1 (SMR1)

Serial mode register 2 (SMR2: $025):

Serial mode register 2 (SMR2) has the following functions. See figure 57.

�

/SI/SO pin PMOS control

�

Idle high/low control

Serial mode register 2 (SMR2) is a 2-bit write-only register. The register value cannot be modified in the
transfer state.

Bit 2 (SMR22) of serial mode register 2 (SMR2) controls the on/off status of the R2

/SI/SO pin PMOS.

The bit 2 (SMR22) only is reset to 0 by an MCU reset.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

102

Bit 1 (SMR21) of serial mode register 2 (SMR2) performs SO pin high/low control in the idle state. The
SO pin changes at the same time as the high/low write.

SMR21

/SI/SO pin output buffer control

PMOS active

PMOS off (NMOS open-drain output)

SMR22

Idle high/low control

SO pin set to low-level output in idle state

SO pin set to high-level output in idle state

Serial mode register 2 (SMR2: $025)

Bit

Read/Write

Initial value on reset

Bit name

SMR22

undeternined

SMR21

Figure 57 Serial Mode Register 2 (SMR2)

Serial data register (SRL: $026, SRU: $027):

The serial data register (SRL, SRU) has the following functions. See figures 58 and 59.

�

Transmit data write and shift operations

�

Receive data shift and read operations

The data written to the serial data register (SRL, SRU) is output LSB-first from the SO pin in
synchronization with the falling edge of the serial clock.

External data input LSB-first from the SI pin is latched in synchronization with the rising edge of the serial
clock. Figure 60 shows the serial clock and data input/output timing chart.

Writing and reading of the serial data register (SRL, SRU) must be performed only after data
transmission/reception is completed. The data contents are not guaranteed if a read or write is performed
during data transmission or reception.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

104

Port mode register 3 (PMR3: $00B):

Port mode register 3 (PMR3) has the following functions. See figure 61.

�

SCK pin selection

�

/SI/SO pin selection

Port mode register 3 (PMR3) is a 4-bit write-only register used to select serial interface pin settings as
shown in figure 61. It is reset to $0 by an MCU reset.

/TOC pin mode selection

PMR30

/SCK pin mode selection

PMR31

TOC

SCK

PMR33 PMR32

/SI/SO pin mode selection

: Don't care

Port mode register 3 (PMR3: $00B)

Bit

Read/Write

Initial value on reset

Bit name

PMR33

PMR32

PMR31

PMR30

Figure 61 Port Mode Register 3 (PMR3)

HD404374/HD404384/HD404389/HD404082/HD404084 Series

106

A/D Converter (HD404374/HD404384/HD404389 Series)

The MCU has a built-in successive approximation type A/D converter using a resistance ladder method,
capable of digital conversion of four analog inputs with an 10-bit resolution. The A/D converter block
diagram is shown in figure 63.

The A/D converter comprises the following four registers.

�

A/D mode register (AMR: $028)

�

A/D start flag (ADSF: $020,2)

�

A/D data register (ADRL: $029, ADRM: $02A, ADRU: $02B)

�

Module standby register 2 (MSR2: $00E)

Note : With the HD404374, HD404384, and HD404389 Series emulator, write 1 to bit 0 (ADRL0) of A/D

data register-lower (ADRL). This bit need not be written in the mask ROM and ZTAT

versions

in these series, although writing 1 will have no effect.

Interrupt flag

(IFAD)

Encoder

A/D data

(ADRU, ADRM, ADRL)

Internal data bus

Selector

Conversion time control

A/D

start flag

(ADSF)

COMP

Reference

voltage

Reference

voltage control

/AN

*AN

/AN

�

A/D

control

logic

A/D mode

(AMR)

Note: * Applies to HD404389 Series.

D/A

Operating mode signal (set to 1 in
stop, watch, and subactive modes,
and during module standby)

Figure 63 A/D Converter Block Diagram

HD404374/HD404384/HD404389/HD404082/HD404084 Series

107

A/D mode register (AMR: $028):
The A/D mode register is a 4-bit write-only register that shows the A/D converter speed setting and
information on the analog input pin specification. The A/D conversion time is selected by bit 0, and the
channel by bits 1, 2, and 3 (figure 64).

A/D start flag (ADSF: $020,2):
A/D conversion is started by writing 1 to the A/D start flag. When conversion ends, the converted data is
placed in the A/D data register and the A/D start flag is cleared at the same time. (figure 65).

Bit

Read/Write

Initial value on reset

Bit name

AMR3

AMR2

AMR1

AMR0

Analog input channel selection

No selection

AN0

AN1

AN2

AN3

AN4*

AN5*

AMR1

AMR2

AMR3

AMR0

A/D conversion time

65 t

cyc

125 t

cyc

A/D mode register (AMR: $028)

Note: * Applies to the HD404389 series. This selection is not available on the HD

404374 and HD404384 series.

Figure 64 A/D Mode Register (AMR)

HD404374/HD404384/HD404389/HD404082/HD404084 Series

108

Bit

Read/Write

Initial value on reset

Bit name

R/W

DTON

R/W

ADSF

R/W

WDON

R/W

LSON

A/D start flag (ADSF: $020,2)

DTON (see low-power mode section)

WDON (see timer section)

LSON (see low-power mode section)

A/D start flag (ADSF)

A/D conversion starts

Indicates end of A/D conversion

Figure 65 A/D Start Flag (ADSF)

A/D data register (ADRL: $029, ADRM: $02A, ADRU: $02B):
The A/D data register is a read-only register consisting of a middle 4 bits and lower 2 bits. This register is
not cleared by a reset. Also, data read during A/D conversion is not guaranteed. At the end of A/D
conversion, the resulting 10-bit data is stored in this register, and is held until the next conversion operation
starts (figures 66, 67, 68, and 69).

MSB

LSB

bit9

bit0

ADRU : $02B

ADRM : $02A

ADRL : $029

3 2 1 0

3 2

Figure 66 A/D Data Register

HD404374/HD404384/HD404389/HD404082/HD404084 Series

109

Bit

Read/Write

Initial value on reset

Bit name

ADRL3

ADRL2

Not used

--*

Not used

A/D data register-lower (ADRL: $029)

Note: * Should be written with 1 with the emulator.

Figure 67 A/D Data Register-Lower (ADRL)

Bit

Read/Write

Initial value on reset

Bit name

ADRM3

ADRM2

ADRM1

ADRM0

A/D data register-middle (ADRM: $02A)

Figure 68 A/D Data Register-Middle (ADRM)

Bit

Read/Write

Initial value on reset

Bit name

ADRU3

ADRU2

ADRU1

ADRU0

A/D data register-upper (ADRU: $02B)

Figure 69 A/D Data Register-Upper (ADRU)

Module standby register 2 (MSR2: $00E):

Writing 1 to bit 1 of module standby register 2 stops the supply of the system clock to the A/D module and
cuts the current (I

) flowing in the ladder resistor.

Usage notes:

�

Use the SEM or SEMD instruction to write to the A/D start flag (ADSF).

�

Do not write to the ADSF during A/D conversion.

�

Data in the A/D data register is undetermined during A/D conversion.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

111

ZTAT

Microcomputer with Built-in Programmable ROM

Precautions for use of ZTAT

microcomputer with built-in programmable ROM

(1) Precautions for writing to programmable ROM built in ZTAT

microcomputer

In the ZTAT

microcomputer with built-in plastic mold one-time programmable ROM, incomplete

electrical connection between the PROM writer and socket adapter causes writing errors and, makes the
computer unoperatable. To enhance the writing efficiency, attention should be paid to the following points:

(a) Make sure that the socket adapter is firmly fixed to the PROM writer and connected electrically with

each other (neither opened nor shorted), before starting the writing process.

(b) To secure the electrical connection between the contact pin and IC lead, make sure that there is no

foreign substance on the contact pin of the socket adapter, which may cause improper electrical
connection.

connection between the contact pin and IC lead. If the lead is bent, correct the bending and insert it
again.

(d) If any trouble is noticed during a blank check to be performed to prevent erroneous writing due to

improper electrical connection, carry out the writing process again according to above steps (a), (b), and
(c).

(e) During the writing process, do not touch the socket adapter and IC to prevent erroneous writing.

(f) To write continuously in the IC, follow steps (a), (b), (c), (d) and (e).

(g) If a writing error recurs, or the rate of writing errors occur frequently, stop writing and check the PROM

writer, socket adapter, etc. for defects.

(h) If any problem is noticed in the written program or in the program after being left at a high temperature,

consult our technical staff.

(2) Precautions when new PROM writer, socket adapter or IC is used

When a new PROM writer, socket adapter or IC is employed, breakdown of the IC may occur or its writing
may become impossible because the noise, overshoot, timing or other electrical characteristics may be
inconsistent with the assured IC writing characteristics. To avoid such troubles, check the following points
before starting the writing process.

(a) To ensure stable writing operation, check that the V

of the power supplied to the PROM writer,

power source current capacity of V

, and current consumption at the time of writing to IC are provided

with sufficient margin.

(b) To prevent breakdown of the IC, check that the power source voltage between GND-V

and GND-

, and overshoot or undershoot of the power source at the connecting terminal of the socket adapter

are within the ratings. Particularly, if the overshoot or undershoot exceeds the maximum rating, the p-n
connection may be damaged, leading to permanent breakdown. If overshoot or undershoot occurs,
recheck the power source damping resistance of capacity.

socket adapter and check the power noise between the GND-V

and GND-V

near the IC connecting

HD404374/HD404384/HD404389/HD404082/HD404084 Series

112

terminal. If power source noise is noticed, insert an appropriate capacitor between the GND power
sources depending on the noise generated. In case of high frequency noise , insert a capacitor of low
inductance.

(d) For stable writing and reading operation, insert the IC into the socket adapter and check the input

waveform, timing and noise near the R/W, CS, address and data terminals. Particularly, since recent
ICs have increased in speed, caution should be exercised against the noise to the power source or
address due to crosstalk from the output data terminal. To avoid these problems, inserting a low
inductance capacitor between the GND and power source or inserting a damping resistance to the output
data terminal is effective.

(e) Particularly, when a multiple PROM writer is used, perform above items (a), (b), (c), and (d) assuming

all ICs inserted into the socket adapter.

(f) In the case of a multiple PROM writer, when an unacceptable result is noticed during a blank check

performed to prevent erroneous writing due to improper electrical connection of the power source, etc.,
rewriting is impossible unless every writing process can be stopped. Therefore, the potential increases
due to erroneous writing because of improper connection. Be sure to check the electrical connection
between the PROM writer and socket adapter and IC.

(g) If any abnormality is noticed while checking a written program, consult our technical staff.

Programming of Built-in programmable ROM

The MCU can stop its function as an MCU in PROM mode for programming the built-in PROM.

PROM mode is set up by setting the

RESET and MO terminals to "Low" level and the TEST terminal to

"Vpp" level.

Writing and reading specifications of the PROM are the same as those for the commercial EPROM27256.
Using a socket adapter for specific use of each product, programming is possible with a general-purpose
PROM writer.

Since an instruction of the HMCS400 series is 10 bits long, a conversion circuit is incorporated to adapt the
general-purpose PROM writer. This circuit splits each instruction into five lower bits and five higher bits
to write from or read to two addresses. This enables use of a general-purpose PROM. For instance, to
write to a 16kword of built-in PROM writer with a general-purpose PROM, specify 32kbyte address
($0000-$7FFF). An example of PROM memory map is shown in figure 70.

Notes:

1. When programming with a PROM writer, set up each ROM size to the address given in table 29. If it is

programmed erroneously to an address given in table 29 or later, check of writing of PROM may
become impossible. Particularly, caution should be exercised in the case of a plastic package since
reprogramming is impossible with it. Set the data in unused addresses to $FF.

2. If the indexes of the PROM writer socket, socket adapter and product are not aligned precisely, the

product may break down due to overcurrent. Be sure to check that they are properly set to the writer
before starting the writing process.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

113

3. Two levels of program voltages (V

) are available for the PROM: 12.5V and 21V. Our product

employs a V

of 12.5V. If a voltage of 21V is applied, permanent breakdown of the product will

result. The V

of 12.5V is obtained for the PROM writer by setting it according to the Intel 27258

specifications.

Table 27

Socket Adapters

Package

Model Name

Manufacturer

FP-30D

Please ask Hitachi service section.

DP-28S

Please ask Hitachi service section.

Writing/Verification

Programming of the built-in program ROM employs a high speed programming method. With this method,
high speed writing is effected without voltage stress to the device or without damaging the reliability of the
written data.

A basic programming flow chart is shown in figure 71 and a timing chart in figure 72.

For precautions for PROM writing procedure, refer to "Precautions for use of ZTAT

microcomputer with

build-in programmable ROM".

Table 28

Selection of Mode

Mode

to O

Writing

"Low"

"High"

Data input

Verification

"High"

"Low"

Data output

Prohibition of programming

"High"

High impedance

Table 29

PROM Writer Program Address

ROM size

Address

$0000~$0FFF

$0000~$1FFF

$0000~$3FFF

16k

$0000~$7FFF

HD404374/HD404384/HD404389/HD404082/HD404084 Series

114

Programmable ROM

The HD407A4374/HD407C4374/HD407A4384/HD407C4384, HD407A4389/HD407C4389 are ZTAT

microcomputers with built-in PROM that can be programmed in PROM mode.

PROM Mode Pin Description

(1) HD407A4374/HD407C4374/HD407A4384/HD407C4384

Pin No.

MCU Mode

PROM Mode.

FP-30D

DP-28S

Pin name

I/O

Pin name

I/O

GND

/AN

I/O

/AN

I/O

/AN

I/O

/AN

I/O

GND

OSC

TEST

GND

RESET

I/O

/EVNB

I/O

/TOB

I/O

/TOC

I/O

SCK

I/O

/SI/SO

I/O

INT

I/O

HD404374/HD404384/HD404389/HD404082/HD404084 Series

115

(2) HD407A4389 and HD407C4389

Pin No.

MCU Mode

PROM Mode.

FP-30D

Pin name

I/O

Pin name

I/O

GND

/AN

I/O

/AN

I/O

/AN

I/O

/AN

I/O

GND

TEST

OSC

RESET

I/O

/EVNB

I/O

/TOB

I/O

/TOC

I/O

SCK

I/O

/SI/SO

I/O

INT

I/O

Note:

I/O: I/O pin, I: Input-only pin, O: Output-only pin

HD404374/HD404384/HD404389/HD404082/HD404084 Series

117

Pin Functions in PROM Mode

Applies the on-chip PROM programming voltage (12.5 V

�

0.3 V).

CE:
Inputs a control signal to set the on-chip PROM to the write/verify enabled state.

OE:
Inputs a data output control signal during verification.

to A

On-chip PROM address input pins.

to O

On-chip PROM data bus I/O pins.

MO, RESET, TEST:
PROM mode setting pins. PROM mode is set by driving the

RESET, and MO pins low, and driving the

TEST pin to the V

level.

Other pins:
V

and AV

should be connected to V

potential.

GND, AV

, and X1 should be connected to GND potential.

Other pins should be left open.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

118

$0000

Vector address

Zero-page subroutine
(64 words)

Pattern
(4,096 words)

Program
(16,384 words)

$0001

$001F

$0080

$007F

$2000

$1FFF

$7FFF

$0020

Bit 4

Bit 8

Bit 3

Bit 7

Bit 2

Bit 6

Bit 1

Bit 5

Bit 0

Bit 9

Upper three bits are not to be used
(fill them with 111)

Upper 5 bits

Lower 5 bits

$0000

$000F
$0010

$003F
$0040

$3FFF

$0000

$0001

$0002

$0003

$0004

$0005
$0006

$0007
$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

JMPL instruction

(jump to

RESET

routine)

JMPL instruction

(jump to

routine)

JMPL instruction

(jump to timer A routine)

JMPL instruction

(jump to

INT

routine)

JMPL instruction

(jump to timer B routine)

JMPL instruction

(jump to timer C routine)

JMPL instruction

(jump to A/D, serial routine)

$07FF
$0800

Figure 70 Memory Map in PROM Mode

HD404374/HD404384/HD404389/HD404082/HD404084 Series

120

Programming Electrical Characteristics

DC Characteristics (V

= 6V

�

0.25V, V

= 12.5V

�

0.3V, V

= 0V, T

= 25

�

C, unless otherwise

specified)

Item

Symbol

Test Conditions

min

typ

max

Unit

Input high voltage

to O

to A

2.2

+0.3 V

Input low voltage

to O

to A

�0.3

0.8

Output high voltage

to O

=�200

�

2.4

Output low voltage

to O

=1.6mA

0.4

Input leakage current O

to O

to A

=5.25V/0.5V

�

current

AC Characteristics (V

= 6V

�

0.25V, V

= 12.5V

�

0.3V, T

= 25

�

C, unless otherwise specified)

Item

Symbol

Test Conditions

min

typ

max

Unit

Address setup time

�

setup time

OES

�

Data setup time

�

Address hold time

�

Data hold time

�

Data output disable time

See figure 72

130

setup time

VPS

�

Program pulse width

0.95

1.0

1.05

pulse width during overprogramming

OPW

2.85

78.75

setup time

VCS

�

Data output delay time

500

Notes: Input pulse level: 0.8 V to 2.2 V

Input rise/fall times:

20ns

Input timing reference levels: 1.0 V, 2.0 V

Output timing reference levels: 0.8 V, 2.0 V

HD404374/HD404384/HD404389/HD404082/HD404084 Series

122

Notes on PROM Programming

Principles of Programming/Erasure: A memory cell in a ZTATTM microcomputer is the same as an
EPROM cell; it is programmed by applying a high voltage between its control gate and drain to inject hot
electrons into its floating gate. These electrons are stable, surrounded by an energy barrier formed by an
SiO

film. The change in threshold voltage of a memory cell with a charged floating gate makes the

corresponding bit appear as 0; a cell whose floating gate is not charged appears as a 1 bit (figure 73).

The charge in a memory cell may decrease with time. This decrease is usually due to one of the following
causes:

�

Ultraviolet light excites electrons, allowing them to escape. This effect is the basis of the erasure
principle.

�

Heat excites trapped electrons, allowing them to escape.

�

High voltages between the control gate and drain may erase electrons.

If the oxide film covering a floating gate is defective, the electron erasure rate will be greater. However,
electron erasure does not often occur because defective devices are detected and removed at the testing
stage.

Control gate

Floating gate

Drain

SiO

Source

Control gate

Floating gate

Drain

SiO

Source

Erasure (1)

Write (0)

Figure 73 Cross-Sections of a PROM Cell

PROM Programming: PROM memory cells must be programmed under specific voltage and timing
conditions. The higher the programming voltage V

and the longer the programming pulse t

is applied,

the more electrons are injected into the floating gates. However, if V

exceeds specifications, the pn

junctions may be permanently damaged. Pay particular attention to overshooting in the PROM
programmer. In addition, note that negative voltage noise will produce a parasitic transistor effect that may
reduce breakdown voltages.

The ZTATTM microcomputer is electrically connected to the PROM programmer by a socket adapter.
Therefore, note the following points:

�

Check that the socket adapter is firmly mounted on the PROM programmer.

�

Do not touch the socket adapter or the LSI during the programming. Touching them may affect the
quality of the contacts, which will cause programming errors.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

123

PROM Reliability after Programming: In general, semiconductor devices retain their reliability,
provided that some initial defects can be excluded. These initial defects can be detected and rejected by
screening. Baking devices under high-temperature conditions is one method of screening that can rapidly
eliminate data-hold defects in memory cells. (Refer to the previous Principles of Programming/Erasure
section.)

ZTATTM microcomputer devices are extremely reliable because they have been subjected to such a
screening method during the wafer fabrication process, but Hitachi recommends that each device be
exposed to 150

�

C at one atmosphere for at least 48 hours after it is programmed, to ensure its best

performance. The recommended screening procedure is shown in figure 74.

Note:

If programming errors occur continuously during PROM programming, suspend programming and
check for problems in the PROM programmer or socket adapter. If programming verification
indicates errors in programming or after high-temperature exposure, please inform Hitachi.

Note: Exposure time is measured from when the temperature in the heater reaches 150

�

Programming, verification

Exposure to high temperature, without power

150

�

C, 48 h

+8 h
0 h

�

Program read check
V = 4.5 V or 5.5 V

Figure 74 Recommended Screening Procedure

Programming percentage: Programming percentage is guarenteed to more than 95%.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

124

Addressing Modes

RAM Addressing Modes

The MCU has three RAM addressing modes, as shown in figure 75 and described below.

Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used
as a RAM address.

Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains
the opcode, and the contents of the second word (10 bits) are used as a RAM address.

Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from
$040 to $04F, are accessed with the LAMR and XMRA instructions.

W register

X register

Y register

RAM address

Register Indirect Addressing

RAM address

Direct Addressing

2nd word of Instruction

Opcode

1st word of Instruction

RAM address

Memory Register Addressing

Opcode

Instruction

Figure 75 RAM Addressing Modes

HD404374/HD404384/HD404389/HD404082/HD404084 Series

125

ROM Addressing Modes and the P Instruction

The MCU has four ROM addressing modes, as shown in figure 76 and described below.

Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing
the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits
(PC

�PC

) with 14-bit immediate data.

Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program
can branch to any address in the current page by executing the BR instruction. This instruction replaces the
eight low-order bits of the program counter (PC

�PC

) with eight-bit immediate data. If the BR instruction

is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next
physical page, as shown in figure 78. This means that the execution of the BR instruction on a page
boundary will make the program branch to the next page.

Note that the HMCS400-series cross assembler has an automatic paging feature for ROM pages.

Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000�
$003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data
are placed in the six low-order bits of the program counter (PC

�PC

), and 0s are placed in the eight high-

order bits (PC

�PC

Table Data Addressing Mode: A program can branch to an address determined by the contents of four-bit
immediate data, the accumulator, and the B register by executing the TBR instruction.

P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction
as shown in figure 77. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator
and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If
both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and
R2 port output registers at the same time.

The P instruction has no effect on the program counter.

Branch Destination of BR Instruction on Page Boundary: If a BR instruction is located on a page
boundary (256n + 255), because of the hardware architecture the program counter contents will shift to the
next page when that instruction is executed. When using a BR instruction on a page boundary, therefore,
the branch destination must be set within the next page (see figure 78).

The HMCS400-series cross assembler has an automatic paging feature for ROM pages, regardless of the
model.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

126

2nd word of instruction

Opcode

1st word of instruction

[JMPL]
[BRL]
[CALL]

Program counter

Direct Addressing

Zero Page Addressing

Instruction

[CAL]

Opcode

Program counter

Accumulator

Program counter

Table Data Addressing

B register

[TBR]

Instruction

Opcode

Instruction

Program counter

Current Page Addressing

[BR]

Figure 76 ROM Addressing Modes

HD404374/HD404384/HD404389/HD404082/HD404084 Series

127

Accumulator

Referenced ROM address

Address Designation

B register

[P]

Instruction

Opcode

If RO = 1

Accumulator, B register

ROM data

Note: Designate RO

as 0. Cannot assign pattern output to port R.

Figure 77 P Instruction

BR AAA

AAA NOP

256 (n � 1) + 255

256n

BR AAA
BR BBB

256n + 254
256n + 255
256 (n + 1)

BBB NOP

Figure 78 Branching when the Branch Destination is on a Page Boundary

HD404374/HD404384/HD404389/HD404082/HD404084 Series

128

Instruction Set

The MCU Series has 101 instructions, classified into the following 10 groups:

�

Immediate instructions

�

RAM addressing instructions

�

RAM register instructions

�

Arithmetic instructions

�

Compare instructions

�

RAM bit manipulation instructions

�

ROM addressing instructions

�

Input/output instructions

�

Control instructions

The functions of these instructions are listed in tables 30 to 39, and an opcode map is shown in table 40.

Table 30

Immediate Instructions

Operation

Mnemonic

Operation Code

Function

Status

Words/
Cycles

Load A from immediate

LAI i

1 i

1/1

Load B from immediate

LBI i

0 i

1/1

Load memory from
immediate

LMID i,d

0 i

2/2

Load memory from
immediate, increment Y

LMIIY i

1 i

M, Y + 1

1/1

HD404374/HD404384/HD404389/HD404082/HD404084 Series

129

Table 31

Register-Register Instructions

Operation

Mnemonic

Operation Code

Function

Status

Words/
Cycles

Load A from B

LAB

0 1

1/1

Load B from A

LBA

0 1

1/1

Load A from W

LAW

0 0

2/2*

Load A from Y

LAY

0 1

1/1

Load A from SPX

LASPX

0 1

SPX

1/1

Load A from SPY

LASPY

1 1

SPY

1/1

Load A from MR

LAMR m

1 m

MR (m)

1/1

Exchange MR and A

XMRA m

1 m

MR (m)

1/1

Note:

The assembler automatically provides an operand for the second word of the LAW instruction.

Table 32

RAM Address Instructions

Operation

Mnemonic

Operation Code

Function

Status

Words/
Cycles

Load W from immediate

LWI i

1 0

1/1

Load X from immediate

LXI i

0 i

1/1

Load Y from immediate

LYI i

1 i

1/1

Load W from A

LWA*

1 0

0 0

2/2*

Load X from A

LXA

0 1

1/1

Load Y from A

LYA

1 1

1/1

Increment Y

1 1

Y + 1

1/1

Decrement Y

1 1

Y � 1

1/1

Add A to Y

AYY

1 0

Y + A

OVF

1/1

Subtract A from Y

SYY

1 0

Y � A

1/1

Exchange X and SPX

XSPX

0 0

SPX

1/1

Exchange Y and SPY

XSPY

0 0

SPY

1/1

Exchange X and SPX,
Y and SPY

XSPXY

0 0

SPX,Y

SPY

1/1

Note:

* The assembler automatically provides an operand for the second word of the LAW and LWA

instruction.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

130

Table 33

RAM Register Instructions

Operation

Mnemonic

Operation Code

Function

Status

Words/
Cycles

Load A from memory

LAM

1 0

1/1

LAMX

1 0

SPX

LAMY

1 0

SPY

LAMXY

1 0

SPX, Y

SPY

Load A from memory

LAMD d

1 0

2/2

Load B from memory

LBM

0 0

1/1

LBMX

0 0

SPX

LBMY

0 0

SPY

LBMXY

0 0

SPX, Y

SPY

Load memory from A

LMA

1 0

1/1

LMAX

1 0

SPX

LMAY

1 0

SPY

LMAXY

1 0

SPX, Y

SPY

Load memory from A

LMAD d

1 0

2/2

Load memory from A,
increment Y

LMAIY

1 0

M, Y + 1

1/1

LMAIYX

1 0

M, Y + 1

SPX

Load memory from A,
decrement Y

LMADY

1 0

M, Y � 1

1/1

LMADYX

1 0

M, Y � 1

SPX

HD404374/HD404384/HD404389/HD404082/HD404084 Series

131

Table 33

RAM Register Instructions (cont)

Operation

Mnemonic

Operation Code

Function

Status

Words/
Cycles

Exchange memory
and A

XMA

0 0

1/1

XMAX

0 0

SPX

XMAY

0 0

SPY

XMAXY

0 0

SPX, Y

SPY

Exchange memory
and A

XMAD d

0 0

2/2

Exchange memory
and B

XMB

0 0

1/1

XMBX

0 0

SPX

XMBY

0 0

SPY

XMBXY

0 0

SPX, Y

SPY

HD404374/HD404384/HD404389/HD404082/HD404084 Series

132

Table 34

Arithmetic Instructions

Operation

Mnemonic

Operation Code

Function

Status

Words/
Cycles

Add immediate to A

AI i

0 i

A + i

OVF

1/1

Increment B

0 1

B + 1

1/1

Decrement B

0 1

B � 1

1/1

Decimal adjust for
addition

DAA

0 0

1/1

Decimal adjust for
subtraction

DAS

0 1

1/1

Negate A

NEGA

0 0

+ 1

1/1

Complement B

COMB

0 0

1/1

Rotate right A with carry

ROTR

0 0

1/1

Rotate left A with carry

ROTL

0 0

1/1

Set carry

SEC

0 1

1/1

Reset carry

REC

0 1

1/1

Test carry

0 1

1/1

Add A to memory

0 1

M + A

OVF

1/1

Add A to memory

AMD d

0 1

M + A

OVF

2/2

Add A to memory with
carry

AMC

1 1

M + A + CA

OVF

1/1

Add A to memory with
carry

AMCD d

1 1

M + A + CA

OVF

2/2

Subtract A from memory
with carry

SMC

1 1

M � A �

1/1

Subtract A from memory
with carry

SMCD d

1 1

M � A �

2/2

OR A and B

0 0

1/1

AND memory with A

ANM

1 1

1/1

AND memory with A

ANMD d

1 1

2/2

OR memory with A

ORM

0 1

1/1

OR memory with A

ORMD d

0 1

2/2

EOR memory with A

EORM

1 1

1/1

EOR memory with A

EORMD d

1 1

2/2

HD404374/HD404384/HD404389/HD404082/HD404084 Series

133

Table 35

Compare Instructions

Operation

Mnemonic

Operation Code

Function

Status

Words/
Cycles

Immediate not equal to
memory

INEM i

0 i

1/1

Immediate not equal to
memory

INEMD i,d

0 i

2/2

A not equal to memory

ANEM

0 0

1/1

A not equal to memory

ANEMD d

0 0

2/2

B not equal to memory

BNEM

0 0

1/1

Y not equal to immediate

YNEI i

1 i

1/1

Immediate less than or
equal to memory

ILEM i

1 i

1/1

Immediate less than or
equal to memory

ILEMD i,d

1 i

2/2

A less than or equal to
memory

ALEM

1 0

1/1

A less than or equal to
memory

ALEMD d

1 0

2/2

B less than or equal to
memory

BLEM

0 0

1/1

A less than or equal to
immediate

ALEI i

1 i

1/1

Table 36

RAM Bit Manipulation Instructions

Operation

Mnemonic

Operation Code

Function

Status

Words/
Cycles

Set memory bit

SEM n

0 0

M (n)

1/1

Set memory bit

SEMD n,d

0 0

M (n)

2/2

Reset memory bit

REM n

0 1

M (n)

1/1

Reset memory bit

REMD n,d

0 1

M (n)

2/2

Test memory bit

TM n

0 1

M (n)

1/1

Test memory bit

TM n,d

0 1

M (n)

2/2

HD404374/HD404384/HD404389/HD404082/HD404084 Series

134

Table 37

ROM Address Instructions

Operation

Mnemonic

Operation Code

Function

Status

Words/
Cycles

Branch on status 1

BR b

1/1

Long branch on status 1

BRL u

1 p

2/2

Long jump
unconditionally

JMPL u

1 p

2/2

Subroutine jump on
status 1

CAL a

1/2

Long subroutine jump
on status 1

CALL u

0 p

2/2

Table branch

TBR p

1 p

1/1

Return from subroutine

RTN

1 0

1/3

Return from interrupt

RTNI

1 0

IE,

carry restored

1/3

Table 38

Input/Output Instructions

Operation

Mnemonic

Operation Code

Function

Status

Words/
Cycles

Set discrete I/O latch

SED

0 0

D (Y)

1/1

Set discrete I/O latch
direct

SEDD m

0 m

D (m)

1/1

Reset discrete I/O latch

RED

0 0

D (Y)

1/1

Reset discrete I/O latch
direct

REDD m

0 m

D (m)

1/1

Test discrete I/O latch

0 0

D (Y)

1/1

Test discrete I/O latch
direct

TDD m

0 m

D (m)

1/1

Load A from R-port
register

LAR m

1 m

R (m)

1/1

Load B from R-port
register

LBR m

0 m

R (m)

1/1

Load R-port register
from A

LRA m

1 m

R (m)

1/1

Load R-port register
from B

LRB m

0 m

R (m)

1/1

Pattern generation

P p

1 p

1/2

HD404374/HD404384/HD404389/HD404082/HD404084 Series

136

Table 40

Opcode Map

LBI i(4)

LYI i(4)

LXI i(4)

LAI i(4)

LBR m(4)

LAR m(4)

REDD m(4)

LAMR m(4)

AI i(4)

LMIIY i(4)

TDD m(4)

ALEI i(4)

LRB m(4)

LRA m(4)

SEDD m(4)

XMRA m(4)

1-word/2-cycle
instruction

1-word/3-cycle
instruction

RAM direct address
instruction
(2-word/2-cycle)

2-word/2-cycle
instruction

NOP

XSPX

XSPY XSPXY ANEM

ORM

LBM(XY)

BNEM

LAB

LMAIY(X)

AYY

LASPY

RTN

RTNI

ALEM

AMC

EORM

NEGA

RED

LASPX

INEM i(4)

ILEM i(4)

YNEI i(4)

XMA(XY)

LAM(XY)

SEM n(2)

LMA(XY)

REM n(2)

SMC

TM n(2)

ANM

ROTR

DAA

DAS

LAY

ROTL

SEC

LBA

LYA

REC

LXA

BLEM

SYY

SED

XMB(XY)

LMADY(X)

LWI i(2)

TBR p(4)

HD404374/HD404384/HD404389/HD404082/HD404084 Series

138

Absolute Maximum Ratings

Item

Symbol

Value

Unit

Notes

Power supply voltage

�0.3 to +7.0

Programming voltage

�0.3 to +14.0

Pin voltage

�0.3 to V

+0.3

Allowable input current (total)

100

Allowable output current (total)

�

Allowable input current (per pin)

4,5

4,6

Allowable output current (per pin)

�l

7,8

7,9

Operating temperature

Topr

�20 to +75

�

10, 12

�40 to +85

�

11, 12

Storage temperature

Tstg

�55 to +125

�

Notes: Permanent damage may occur if these maximum ratings are exceeded. Normal operation must be

under the conditions stated in the electrical characteristics tables. If these conditions are exceeded,
the LSI may malfunction or its reliability may be affected.

1. Applies to the HD407A4374, HD407C4374, HD407A4384, HD407C4384, HD407A4389, and

HD407C4389 TEST (V

) pin.

2. The allowable input current (total) is the sum of all currents flowing from I/O pins to ground at the

same time.

3. The allowable output current (total) is the sum of all currents flowing from V

to I/O pins.

4. The allowable input current (per pin) is the maximum current allowed to flow from any one I/O pin

to ground.

5. Applies to pins D

to D

, D

and port R.

6. Applies to pins D

to D

7. The allowable output current (per pin) is the maximum current allowed to flow from V

to any

one I/O pin.

8. Applies to pins D

to D

and port R.

9. Applies to pins D

to D

10. Applies to Mask ROM

11. Applies to ZTAT

12. The operating temperature indicates the temperature range in which power can be supplied to

the LSI (voltage Vcc shown in the electrical characteristics tables can be applied).

13. In the case of chips, the storage specification differs from that of the package products. Please

consult your Hitachi sales representative for details.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

139

Electrical Characteristics

DC Characteristics (HD404372, HD40A4372, HD40C4372, HD404374, HD40A4374, HD40C4374,

HD404382, HD40A4382, HD40C4382, HD404384, HD40A4384, HD40C4384, HD404388,

HD40A4388, HD40C4388, HD404389, HD40A4389, HD40C4389, HD404081, HD40A4081,

HD40C4081, HD404082, HD40A4082, HD40C4082, HD404084, HD40A4084, HD40C4084: V

= 1.8

V to 5.5 V, GND = 0 V, T

= �20

�

C to +75

�

C; HCD404082, HCD40C4082, HCD404084,

HCD40C4084: V

= 1.8 V to 5.5 V, GND = 0 V, T

= +75

�

C; HD407A4374, HD407C4374,

HD407A4384, HD407C4384, HD407A4389, HD407C4389: V

= 2.0 V to 5.5 V, GND = 0 V, T

= �

�

C to +85

�

C, unless otherwise specified)

Item

Symbol Pins

min.

typ. max.

Unit

Test conditions

Notes

Input high voltage

RESET

SCK

SI,

INT

EVNB

0.90V

+0.3 V

OSC

�0.3

+0.3 V

External clock operation

Input low voltage

RESET

SCK

SI,

INT

EVNB

�0.3

0.10V

OSC

�0.3

0.3

External clock operation

Output high
voltage

SCK

,SO,

TOB, TOC

�0.5

�I

=0.3mA

Output low voltage V

SCK

,SO,

TOB, TOC

0.4

=0.4mA

I/O leakage
current

| I

RESET

SCK

SI,

INT

EVNB, OSC

TOB, TOC,
SO

�

=0V to V

Active mode

CC1

1.5

3.5

=5V, f

OSC

=4MHz

2, 7

current dissipation

1.2

2.5

2, 8

CC2

0.4

1.0

=3V, f

OSC

=800kHz

2, 7

0.3

0.7

2, 8

CC3

2.7

9.0

=5V, f

OSC

=8MHz

2, 9

2.2

4.5

2, 10

Standby mode

SBY1

1.0

1.5

=5V, f

OSC

=4MHz

3, 7

current dissipation

0.6

1.3

3, 8

SBY2

0.3

0.6

=3V, f

OSC

=800kHz

3, 7

0.2

0.5

3, 8

SBY3

1.4

4.0

=5V, f

OSC

=8MHz

3, 9

1.0

2.5

3, 10

HD404374/HD404384/HD404389/HD404082/HD404084 Series

140

Item

Symbol Pins

min.

typ. max.

Unit

Test Conditions

Notes

Subactive mode
current dissipation

SUB

�

= 3V,

32 kHz oscillator used

4, 5

Watch mode
current dissipation

WTC

�

= 3 V,

32 kHz oscillator used

4, 5

Stop mode current
dissipation

STOP

�

= 3 V, no 32 kHz

oscillator

Stop mode
retention voltage

STOP

1.5

no 32 kHz oscillator

Notes: 1. Excludes output buffer current.

2. Power supply current when the MCU is in the reset state and there are no I/O currents.

Test Conditions MCU State

�

Reset state

Pin States

�

RESET

, TEST: At ground

3. Power supply current when the on-chip timers are operating and there are no I/O currents.

Test Conditions MCU State

�

I/O: Same as reset state

�

Standby mode

�

cyc

= f

OSC

Pin States

�

RESET

: At V

�

TEST: At ground

�

D port, R port: At V

4. Power supply current when there are no I/O currents.

Test Conditions Pin States

�

RESET

: At V

�

TEST: At ground

�

D port, R port: At V

5. Applies to HD404374 Series.

6. Voltage needed to retain RAM data.

7. Applies to HD404374, HD404384, and HD404389 Series.

8. Applies to HD404082 and HD404084 Series.

9. Applies to HD40A4374/2, HD407A4374, HD40A4384/2, HD407A4384, HD40A4389/8 and

HD407A4389.

10. Applies to HD40A4082/1 and HD40A4084.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

141

I/O Characteristics for Standard Pins DC Characteristics (HD404372, HD40A4372, HD40C4372,

HD404374, HD40A4374, HD40C4374, HD404382, HD40A4382, HD40C4382, HD404384,

HD40A4384, HD40C4384, HD404388, HD40A4388, HD40C4388, HD404389, HD40A4389,

HD40C4389, HD404081, HD40A4081, HD40C4081, HD404082, HD40A4082, HD40C4082,

HD404084, HD40A4084, HD40C4084: V

= 1.8 V to 5.5 V, GND = 0 V, T

= �20

�

C to +75

�

HCD404082, HCD40C4082, HCD404084, HCD40C4084: V

= 1.8 V to 5.5 V, GND = 0 V, T

+75

�

C; HD407A4374, HD407C4374, HD407A4384, HD407C4384, HD407A4389, HD407C4389: V

2.0 V to 5.5 V, GND = 0 V, T

= �40

�

C to +85

�

C, unless otherwise specified)

Item

Symbol

Pins

min.

typ. max.

Unit

Test conditions

Notes

Input high voltage

R port, D

, D

0.7V

+0.3

Input low voltage

R port, D

, D

�0.3

0.3V

Output high voltage

R port, D

, D

�0.5

�I

=0.3mA

Output low voltage

R port, D

, D

0.4

=0.4mA

I/O leakage current

| I

R port, D

, D

�

=0V to V

MOS pull-up current

�I

R port, D

, D

150

�

=3V, V

=0V

Note:

1. Excludes output buffer current.

I/O Characteristics for High-Current Pins DC Characteristics (HD404372, HD40A4372,

HD40C4372, HD404374, HD40A4374, HD40C4374, HD404382, HD40A4382, HD40C4382,

HD404384, HD40A4384, HD40C4384, HD404388, HD40A4388, HD40C4388, HD404389,

HD40A4389, HD40C4389, HD404081, HD40A4081, HD40C4081, HD404082, HD40A4082,

HD40C4082, HD404084, HD40A4084, HD40C4084: V

= 1.8 V to 5.5 V, GND = 0 V, T

= �20

�

C to

+75

�

C; HCD404082, HCD40C4082, HCD404084, HCD40C4084: V

= 1.8 V to 5.5 V, GND = 0 V, T

= +75

�

C; HD407A4374, HD407C4374, HD407A4384, HD407C4384, HD407A4389, HD407C4389: V

= 2.0 V to 5.5 V, GND = 0 V, T

= �40

�

C to +85

�

C, unless otherwise specified)

Item

Symbol

Pins

min.

typ. max.

Unit

Test conditions

Notes

Input high voltage

to D

0.7V

+0.3

Input low voltage

to D

�0.3

0.3V

Output high voltage

to D

�0.5

�I

=0.3mA

to D

�2.0

�I

=10mA,

=4.5 to 5.5V

Output low voltage

to D

0.4

=0.4mA

to D

2.0

=15mA

=4.5V to 5.5V

I/O leakage current

| I

to D

�

=0V to V

MOS pull-up current

�I

to D

150

�

=3V, V

=0V

Note:

1. Excludes output buffer current.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

142

A/D Converter Characteristics (HD404374/HD404384/HD404389 Series) (Mask ROM: V

= 1.8 V to

5.5 V, GND = 0 V, T

= �20

�

C to +75

�

C; ZTAT

: V

= 2.0 V to 5.5 V, GND = 0 V, T

= �20

�

C to

+75

�

C, unless otherwise specified)

Item

Symbol

Pins

min.

typ. max.

Unit

Test conditions

Notes

Analog power supply
voltage

�0.3

+0.3

Analog input voltage

to AN

-AV

current

500

�

=AV

=5.0V

Analog input
capacitance

to AN

Resolution

bit

Number of inputs

channel

Absolute accuracy

�

4.0

LSB

=AV

=1.8V to

5.5V

=AV

=2.0V to

5.5V

Conversion time

125

cyc

=AV

=1.8V to

2.0V or less

cyc

=AV

=2.0V to

5.5V

Input impedance

to AN

Notes: 1. Connect to the V

pin when the A/D converter is not used. The AV

setting range is 1.8

5.5V (Mask ROM), 2.0V

5.5V (ZTAT

2. Applies to Mask ROM.

3. Applies to ZTAT

HD404374/HD404384/HD404389/HD404082/HD404084 Series

143

AC Characteristics DC Characteristics (HD404372, HD40A4372, HD40C4372, HD404374,

HD40A4374, HD40C4374, HD404382, HD40A4382, HD40C4382, HD404384, HD40A4384,

HD40C4384, HD404388, HD40A4388, HD40C4388, HD404389, HD40A4389, HD40C4389,

HD404081, HD40A4081, HD40C4081, HD404082, HD40A4082, HD40C4082, HD404084,

HD40A4084, HD40C4084: V

= 1.8 V to 5.5 V, GND = 0 V, T

= �20

�

C to +75

�

C; HCD404082,

HCD40C4082, HCD404084, HCD40C4084: V

= 1.8 V to 5.5 V, GND = 0 V, T

= +75

�

HD407A4374, HD407C4374, HD407A4384, HD407C4384, HD407A4389, HD407C4389: V

= 2.0 V

to 5.5 V, GND = 0 V, T

= �40

�

C to +85

�

C, unless otherwise specified)

Item

Symbol

Pins

min.

typ.

max.

Unit

Test conditions

Notes

Clock oscillation

OSC

, OSC

0.4

4.5

MHz

Division by 4

frequency

0.4

8.5

1, 3

(ceramic oscillator,
crystal oscillator)

X1,X2

32.768 --

kHz

Clock oscillation
frequency

OSC

, OSC

0.5

2.0

3.5

MHz

Division by 4
Rf=20 k

2, 13

(Resistance oscillation)

0.5

2.2

3.5

2, 12

Instruction cycle time

cyc

0.89

�

Division by 4

(external clock,

0.47

ceramic oscillator,
crystal oscillator)

subcyc

244.14 --

�

32 kHz oscillator used,
division by 8

122.07 --

�

32 kHz oscillator used,
division by 4

Instruction cycle time
(Resistance oscillation)

cyc

1.14

8.0

�

Division by 4
Rf=20 k

Oscillation settling time
(external clock input)

OSC

, OSC

7.5

Oscillation settling time
(ceramic oscillator)

OSC

, OSC

7.5

=2.0 to 5.5V

Oscillation settling

OSC

, OSC

=2.0 to 5.5V

time(crystal oscillator)

X1,X2

=�10 to +60

�

=2.0 to 5.5V

4, 6

Oscillation setting time
(Resistance oscillation)

OSC

, OSC

0.5

Rf=20 k

=2.0 to 5.5V

5, 6

External clock high-

CPH

OSC

105

OSC

=4MHz

level width

52.5

OSC

=8MHz

3, 7

External clock low-

CPL

OSC

105

OSC

=4MHz

level width

52.5

OSC

=8MHz

3, 7

External clock rise time t

CPr

OSC

=4MHz

OSC

=8MHz

3, 7

HD404374/HD404384/HD404389/HD404082/HD404084 Series

144

Item

Symbol

Pins

min.

typ.

max.

Unit

Test conditions

Notes

External clock fall time

CPf

OSC

=4MHz

OSC

=8MHz

3, 7

INT

, EVNB,

high-level width

INT

, EVNB,

cyc

subcyc

INT

, EVNB,

, low-level width

INT

, EVNB,

cyc

subcyc

RESET

low-level width t

RSTL

RESET

cyc

RESET

rise time

RSTr

RESET

Input capacitance

All input pins
except TEST

f=1MHz,V

=0V

TEST

Capacitance between
OSC

and OSC

(Resistance oscillation)

OSC

, OSC

Notes: 1. When the subsystem oscillator (32.768 kHz crystal oscillation) is used, use within the range

0.4 MHz

OSC

1.0 MHz or 1.6 MHz

OSC

8.5 MHz. The SSR1 bit of the system clock select

2. The typ. value is the value when V

= 3.5 V.

3. Applies to HD40A4372/4, HD40A4382/4, HD40A4388/9, HD40A4081/2, HD40A4084,

HD407A4374, HD407A4384 and HD407A4389 when V

= 4.0 to 5.5 V.

4. Applies to HD404374 Series.

5. Applies to HD40C4372/4, HD407C4374, HD40C4382/4, HD407C4384, HD40C4388/9,

HD407C4389, HD40C4081/2, HCD40C4082, HD40C4084, HCD40C4084.

6. The oscillation settling time is defined as follows:

(1)

The time required for the oscillation to settle after V

has reached standard minimum at

power-on.

(2)

The time required for the oscillation to settle after

RESET

input has gone low when stop

mode is cleared.

To ensure enough time for the oscillation to settle at power-on hold the

RESET

input low for at

least time t

. The oscillation settling time will depend on the circuit constants and stray

capacitance. The resonator should be determined in consultation with the resonator
manufacturer. With regard to the system clock (OSC

, OSC

), bits MIS1 and MIS0 in the

miscellaneous register (MIS) should be set according to the oscillation settling time of the
resonator used.

7. See figure 79.

8. See figure 80.

9. See figure 81.

10. Applies to Mask ROM.

11. Applies to ZTAT

12. Applies to HD40C4081/2, HCD40C4082, HD40C4084, HCD40C4084.

13. Applies to HD40C4372/4, HD407C4374, HD40C4382/4, HD407C4384, HD40C4388/9,

HD407C4389.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

145

Serial interface timing characteristics DC Characteristics (HD404372, HD40A4372, HD40C4372,

HD404374, HD40A4374, HD40C4374, HD404382, HD40A4382, HD40C4382, HD404384,

HD40A4384, HD40C4384, HD404388, HD40A4388, HD40C4388, HD404389, HD40A4389,

HD40C4389, HD404081, HD40A4081, HD40C4081, HD404082, HD40A4082, HD40C4082,

HD404084, HD40A4084, HD40C4084: V

= 1.8 V to 5.5 V, GND = 0 V, T

= �20

�

C to +75

�

HCD404082, HCD40C4082, HCD404084, HCD40C4084: V

= 1.8 V to 5.5 V, GND = 0 V, T

+75

�

C; HD407A4374, HD407C4374, HD407A4384, HD407C4384, HD407A4389, HD407C4389: V

2.0 V to 5.5 V, GND = 0 V, T

= �40

�

C to +85

�

C, unless otherwise specified)

Item

Symbol

Pins

min.

typ. max.

Unit

Test conditions

Notes

Serial clock cycle time

Scyc

SCK

cyc

See load in figure 83

Serial clock high-level
width

SCKH

SCK

0.4

Scyc

See load in figure 83

Serial clock low-level
width

SCKL

SCK

0.4

Scyc

See load in figure 83

Serial clock rise time

SC Kr

SCK

100

See load in figure 83

Serial clock fall time

SCKf

SCK

100

See load in figure 83

Serial output data
delay time

DSO

300

See load in figure 83

Serial input data setup
time

SSI

200

Serial input data hold
time

HSI

200

HD404374/HD404384/HD404389/HD404082/HD404084 Series

146

During Serial Clock Input

Item

Symbol

Pins

min.

typ. max.

Unit

Test conditions

Notes

Serial clock cycle time

Scyc

SCK

cyc

Serial clock high-level
width

SCKH

SCK

0.4

Scyc

Serial clock low-level
width

SCKL

SCK

0.4

Scyc

Serial clock rise time

SC Kr

SCK

100

Serial clock fall time

SCKf

SCK

100

Serial output data
delay time

DSO

300

See load in figure 83

Serial input data setup
time

SSI

200

Serial input data hold
time

HSI

200

Note:

1. See

figure

82.

1/f

0.3V

-0.3V

CPL

CPH

CPr

CPf

OSC

Figure 79 External Clock Input Waveform

0.9V

0.1V

INT

,EVNB,

Figure 80 Interrupt Timing

HD404374/HD404384/HD404389/HD404082/HD404084 Series

149

0.0

1.0

2.0

3.0

4.0

5.0

(mA)

(V)

fosc=8MHz

fosc=4MHz

fosc=2MHz

fosc=800kHz
fosc=400kHz

0.0

0.5

1.0

1.5

2.0

2.5

(mA)

(V)

1.0

1.5

2.0

2.5

fosc (MHz)

(V)

0.0

1.0

2.0

3.0

4.0

5.0

fosc (MHz)

Rf (k

)

0.0

0.5

1.0

1.5

2.0

2.5

(V)

(mA)

0.0

1.0

2.0

3.0

4.0

5.0

-VOH (V)

-I

(mA)

Ta=25

�

C fcyc=fosc/4 typ

Ta=25

�

C Rf=20k

typ

Ta=25

�

C typ

Ta=25

�

C typ

Ta=25

�

C typ

Ta=25

�

C Rf=20k

fcyc=fosc/4 typ

=5V

=3.5V

=4.5V

=5V

=5.5V

=4.5V

=5V

=5.5V

=2V

(a) I

vs. V

characteristic (ceramic oscillation, crystal

oscillation)

(b) I

vs. V

characteristic (resistance oscillation)

(c) f

OSC

vs. V

characteristic (resistance oscillation)

(d) f

OSC

vs. Rf characteristic (resistance oscillation)

(e) V

vs. I

characteristic (pins D4 to D7)

(f) V

- V

vs. I

characteristic (pins D0 to D3)

Figure 84 HD404374, HD404384, and HD404389 Series Characteristic Curves (Reference Values)

HD404374/HD404384/HD404389/HD404082/HD404084 Series

150

0.0

0.5

1.0

1.5

2.0

2.5

0.0

0.5

1.0

1.5

2.0

2.5

1.0

1.5

2.0

2.5

0.0

1.0

2.0

3.0

4.0

5.0

0.0

0.5

1.0

1.5

2.0

2.5

0.0

1.0

2.0

3.0

4.0

5.0

fosc=8MHz

fosc=4MHz

fosc=2MHz

fosc=800kHz

fosc=400kHz

Ta=25

�

C fcyc=fosc/4 typ

(mA)

(V)

(mA)

(V)

(a) I

vs. V

characteristic (ceramic oscillation, crystal

oscillation)

Ta=25

�

C Rf=20k

fcyc=fosc/4 typ

(b) I

vs. V

characteristic (resistance oscillation)

fosc (MHz)

Rf (k

)

Ta=25

�

C typ

=5V

=3.5V

=2V

(d) f

OSC

vs. Rf characteristic (resistance oscillation)

fosc (MHz)

(V)

Ta=25

�

C Rf=20k

typ

(c) f

OSC

vs. V

characteristic (resistance oscillation)

-VOH (V)

-I

(mA)

Ta=25

�

C typ

=4.5V

=5V

=5.5V

(f) V

- V

vs. I

characteristic (pins D0 to D3)

(V)

(mA)

Ta=25

�

C typ

=4.5V

=5V

=5.5V

(e) V

vs. I

characteristic (pins D4 to D7)

Figure 85 HD404082 and HD404084 Series Characteristic Curves (Reference Values)

HD404374/HD404384/HD404389/HD404082/HD404084 Series

153

Note on ROM Ordering

Please note the following when ordering HD404372, HD40A4372, HD40C4372, HD404382, HD40A4382
and HD40C4382 ROM.

When ordering ROM, please fill the "Not used" areas below with all-1 data, to give the same amount of
data as for the 4-kwords version (HD404374, HD40A4374, HD40C4372, HD404384, HD40A4384,
HD40C4384). The program that converts ROM data to mask drawing data is the same as that used for the
4-kwords version, and therefore the same amount of data is necessary. This applies both to orders using
EPROM and orders using data transmission.

Vector addresses

Program and pattern

area (2,048 words)

Zero page

subroutine area

(64 words)

Not used*

2-kword ROM
version: HD404372, HD40A4372, HD40C4372,
HD404382, HD40A4382, HD40C4382
Write all-1 data to addresses
$0800 to $0FFF.

$0000

$000F
$0010

$003F
$0040

$07FF
$0800

$0FFF

Note : Write all-1 data in not used area.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

154

Please note the following when ordering HD404388, HD40A4388 and HD40C4388 ROM.

When ordering ROM, please fill the "Not used" areas below with all-1 data, to give the same amount of
data as for the 16-kwords version (HD404389, HD40A4389, HD40C4389). The program that converts
ROM data to mask drawing data is the same as that used for the 16-kwords version, and therefore the same
amount of data is necessary. This applies both to orders using EPROM and orders using data transmission.

Vector addresses

Program and pattern

area (8,192 words)

Zero page

subroutine area

(64 words)

Not used*

8-kword ROM
version: HD404388, HD40A4388,
HD40C4388
Write all-1 data to addresses
$2000 to $3FFF.

$0000

$000F
$0010

$003F
$0040

$1FFF
$2000

$3FFF

Note : Write all-1 data in not used area.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

155

Please note the following when ordering HD404081, HD40A4081 and HD40C4081 ROM.

When ordering ROM, please fill the "Not used" areas below with all-1 data, to give the same amount of
data as for the 2-kwords version (HD404082, HD40A4082, HD40C4082). The program that converts ROM
data to mask drawing data is the same as that used for the 2-kwords version, and therefore the same amount
of data is necessary. This applies both to orders using EPROM and orders using data transmission.

Vector addresses

Program and pattern

area (1,024 words)

Zero page

subroutine area

(64 words)

Not used*

1-kword ROM
version: HD404081, HD40A081,
HD40C4081
Write all-1 data to addresses
$0400 to $07FF.

$0000

$000F
$0010

$003F
$0040

$03FF
$0400

$07FF

Note : Write all-1 data in not used area.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

156

Option List

HD404372, HD404374, HD40A4372, HD40A4374, HD40C4372,
HD40C4374

Please check off the appropriate applications and enter the necessary information.

Date of order

Year

Month

Day

Customer

Department

Name

ROM code name

LSI number (Hitachi entry)

1. ROM Size

Standard operation version: HD404372

2 kwords

High-speed operation version: HD40A4372

CR oscillation version: HD40C4372

Standard operation version: HD404374

4 kwords

High-speed operation version: HD40A4374

CR oscillation version: HD40C4374

2. Function Options

32 kHz CPU operation, realtime clock time base

No 32 kHz CPU operation, realtime clock time base

No 32 kHz CPU operation, no realtime clock time base

Note: When an asterisked item is selected, "crystal resonator" is necessary for subsystem oscillator (X1

X2).

3. ROM Code Data Organization

For a microcomputer with EPROM mounted (including a ZTATTM microcomputer), specify the combined upper/lower
type.

Combined lower/upper type

�

Both the lower 5 data bits (L) and the upper 5 data bits (U) are written to a single EPROM in the order LULULU...

Separate lower/upper type

�

The lower 5 data bits (L) and upper 5 data bits (U) are written to separate EPROMs respectively.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

158

Option List

HD404382, HD404384, HD40A4382, HD40A4384, HD40C4382,
HD40C4384

Please check off the appropriate applications and enter the necessary information.

Date of order

Year

Month

Day

Customer

Department

Name

ROM code name

LSI number (Hitachi entry)

1. ROM Size

Standard operation version: HD404382

2 kwords

High-speed operation version: HD40A4382

CR oscillation version: HD40C4382

Standard operation version: HD404384

4 kwords

High-speed operation version: HD40A4384

CR oscillation version: HD40C4384

2. ROM Code Data Organization

For a microcomputer with EPROM mounted (including a ZTATTM microcomputer), specify the combined upper/lower
type.

Combined lower/upper type

�

Both the lower 5 data bits (L) and the upper 5 data bits (U) are written to a single EPROM in the order LULULU...

Separate lower/upper type

�

The lower 5 data bits (L) and upper 5 data bits (U) are written to separate EPROMs respectively.

3. System Oscillator (OSC1-OSC2) (Shading means selection is not available)

HD404382/4, HD40A4382/4

HD40C4382/4

Crystal oscillator

f = MHz

Ceramic oscillator

f = MHz

External clock

f = MHz

Resistance oscillator

f = MHz

4. Stop Mode

5. Package

Yes (used)

FP-30D

No (not used)

DP-28S

FP-48B

Note:

The WS version will become available at the beginning of mass production.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

159

Option List

HD404388, HD404389, HD40A4388, HD40A4389, HD40C4388,
HD40C4389

Please check off the appropriate applications and enter the necessary information.

Date of order

Year

Month

Day

Customer

Department

Name

ROM code name

LSI number (Hitachi entry)

1. ROM Size

Standard operation version: HD404388

8 kwords

High-speed operation version: HD40A4388

CR oscillation version: HD40C4388

Standard operation version: HD404389

16 kwords

High-speed operation version: HD40A4389

CR oscillation version: HD40C4389

2. ROM Code Data Organization

For a microcomputer with EPROM mounted (including a ZTATTM microcomputer), specify the combined upper/lower
type.

Combined lower/upper type

�

Both the lower 5 data bits (L) and the upper 5 data bits (U) are written to a single EPROM in the order LULULU...

Separate lower/upper type

�

The lower 5 data bits (L) and upper 5 data bits (U) are written to separate EPROMs respectively.

3. System Oscillator (OSC1-OSC2) (Shading means selection is not available)

HD404388/9, HD40A4388/9

HD40C4388/9

Crystal oscillator

f = MHz

Ceramic oscillator

f = MHz

External clock

f = MHz

Resistance oscillator

f = MHz

4. Stop Mode

5. Package

Yes (used)

FP-30D

No (not used)

HD404374/HD404384/HD404389/HD404082/HD404084 Series

160

Option List

HD404081, HD404082, HCD404082, HD40A4081, HD40A4082,
HD40C4081, HD40C4082, HCD40C4082

Please check off the appropriate applications and enter the necessary information.

Date of order

Year

Month

Day

Customer

Department

Name

ROM code name

LSI number (Hitachi entry)

1. ROM Size

Standard operation version: HD404081

1 kwords

High-speed operation version: HD40A4081

CR oscillation version: HD40C4081

Standard operation version: HD404082

2 kwords

Standard operation version: HCD404082

High-speed operation version: HD40A4082

CR oscillation version: HD40C4082

CR oscillation version: HCD40C4082

2. System Oscillator (OSC1-OSC2) (Shading means selection is not available)

HD404081/2, HD40A4081/2,
HCD404082

HD40C4081/2, HCD40C4082

Crystal oscillator

f = MHz

Ceramic oscillator

f = MHz

External clock

f = MHz

Resistance oscillator

f = MHz

3. Stop Mode

4. Package

Yes (used)

FP-30D

No (not used)

DP-28S

Chip

Note: The specifications of shipped chips differ from those of the package product. Please contact our

sales staff for details.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

161

Option List

HD404084, HCD404084, HD40A4084, HD40C4084, HCD40C4084

Please check off the appropriate applications and enter the necessary information.

Date of order

Year

Month

Day

Customer

Department

Name

ROM code name

LSI number (Hitachi entry)

1. ROM Size

Standard operation version: HD404084

4 kwords

Standard operation version: HCD404084

High-speed operation version: HD40A4084

CR oscillation version: HD40C4084

CR oscillation version: HCD40C4084

2. System Oscillator (OSC1-OSC2) (Shading means selection is not available)

HD404084, HD40A4084, HCD404084 HD40C4084, HCD40C4084

Crystal oscillator

f = MHz

Ceramic oscillator

f = MHz

External clock

f = MHz

Resistance oscillator

3. Stop Mode

4. Package

Yes (used)

FP-30D

No (not used)

DP-28S

Chip

Note: The specifications of shipped chips differ from those of the package product. Please contact our

sales staff for details.

HD404374/HD404384/HD404389/HD404082/HD404084 Series

162

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent,

copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party's rights, including
intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi's sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor

products.

Электронный компонент: HD407C4374

Document Outline