Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.

The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas

Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)

Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand

names are mentioned in the document, these names have in fact all been changed to Renesas

Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and

corporate statement, no changes whatsoever have been made to the contents of the document, and

these changes do not constitute any alteration to the contents of the document itself.

Renesas Technology Home Page: http://www.renesas.com

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

To all our customers

Cautions

Keep safety first in your circuit designs!

1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better

and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas

Technology Corporation product best suited to the customer's application; they do not convey any
license under any intellectual property rights, or any other rights, belonging to Renesas Technology
Corporation or a third party.

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third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.

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algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corporation without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corporation
or an authorized Renesas Technology Corporation product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
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rising from these inaccuracies or errors.
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means, including the Renesas Technology Corporation Semiconductor home page
(http://www.renesas.com).

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information contained herein.

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or system that is used under circumstances in which human life is potentially at stake. Please contact
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when considering the use of a product contained herein for any specific purposes, such as apparatus or
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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
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8. Please contact Renesas Technology Corporation for further details on these materials or the products

contained therein.

HD404639R Series

4-Bit Single-Chip Microcomputer

Rev. 6.0

Sept. 1998

Description

The HD404639R Series is a member of the HMCS400-series microcomputers designed to increase
program productivity with large-capacity memory. The HD404639R Series, completely compatible with
the HD404639 Series, reduces current dissipation in half and includes a high-speed version. Each
microcomputer has a high-precision dual-tone multi frequency (DTMF) generator, four timers, two serial
interfaces, voltage comparator, input capture circuit, 32-kHz oscillator for clock, and four low-power
dissipation modes.

The HD404639R Series includes 5 chips: the HD404638R and HD40A4638R with 8-kword ROM; the
HD404639R and HD40A4639R with 16-kword ROM; the HD407A4639R with 16-kword PROM.

HD40A4638R, HD40A4639R, HD407A4639R are high-speed versions (minimum instruction cycle time:
0.5

s).

The HD407A4639R is a PROM version ZTAT

microcomputer. A program can be written to the PROM

by a PROM writer, which can dramatically shorten system development periods and smooth the process
from debugging to mass production. (The ZTAT

version is 27256-compatible.)

ZTAT

: Zero Turn Around Time. ZTAT is a trademark of Hitachi Ltd.

Features

8,192-word

10-bit ROM (HD404638R, HD40A4638R)

16,384-word

10-bit ROM (HD404639R, HD40A4639R, HD407A4639R)

1,152-digit

4-bit RAM

61 I/O pins and 7 dedicated input pins

12 high-current output pins: Eight 15-mA sinks (a maximum of 7 pins can be used at the same time)

and four 10-mA sources

Four timer/counters

Eight-bit input capture circuit

Three timer outputs (including two PWM outputs)

Two event counter inputs (including one double-edge function)

Two clock-synchronous 8-bit serial interfaces

HD404639R Series

Comparator (4 channels)

On-chip DTMF generator: f

OSC

= 400 kHz, 800 kHz, 2 MHz, 3.58 MHz, 4 MHz, 7.16 MHz, or 8 MHz

(7.16 MHz and 8 MHz are only available for HD40A4638R, HD40A4639R and HD407A4639R)

Built-in oscillators

Main clock: Ceramic oscillator or crystal (an external clock is also possible)

Subclock: 32.768-kHz crystal

Eleven interrupt sources

Five by external sources, including three double-edge function

Six by internal sources

Subroutine stack up to 16 levels, including interrupts

Four low-power dissipation modes

Subactive mode

Standby mode

Watch mode

Stop mode

One external input for transition from stop mode to active mode

Instruction cycle time: 1

s (f

OSC

= 4 MHz at 1/4 division ratio), 0.5

s (f

OSC

= 8 MHz at 1/4 division

ratio)

1/4, 1/8, 1/16, or 1/32 division ratio can be selected

Operation voltage

2.7 V to 6.0 V (HD404638R, HD404639R, HD40A4638R, HD40A4639R)

2.7 V to 5.5 V (HD407A4639R)

With V

= 2.2 V to 6.0 V, watch mode can be supported, and instructions can be executed in

subactive mode (not applicable to the HD407A4639R).

Two operating modes

MCU mode

MCU/PROM mode (HD407A4639R)

Ordering Information

Type

Instruction Cycle
Time (

Product Name

Model Name

ROM (Words)

Package

Mask ROM

1 (f

OSC

= 4 MHz at 1/4

division ratio)

HD404638R

HD404638RF

8,192

80-pin
plastic QFP
(FP-80B)

HD404639R

HD404639RF

16,384

0.5 (f

OSC

= 8 MHz at1/4

division ratio)

HD40A4638R

HD40A4638RF

8,192

HD40A4639R

HD40A4639RF

16,384

ZTAT

0.5 (f

OSC

= 8 MHz at 1/4

division ratio)

HD407A4639R

HD407A4639RF 16,384

HD404639R Series

Pin Arrangement

ref

1
2
3
4

17
18
19
20
21
22

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

25 2627 2829 303132333435 36373839 40

80 7978 7776 757473727170 69686766 65

R9
R9
R8
R8
R8
R8
R7
R7
R7
R7
R6
R6
R6
R6

5
6
7

12
13
14
15
16

23
24

(Top view)

R5
R5
R5
R5
R4
R4
R4
R4
R3
R3

RD /COMP
RD /COMP
RD /COMP
RD /COMP

OSC

D
D
D
D
D
D

RE /VC

TEST

OSC

RESET

GND

D
D
D
D

D
D

ref

TONER

TONEC

SEL

D /

STOPC

D /

INT

R0 /

INT

R0 /INT

R3 /TOB

R3 /TOC

/SO
/SI
/

SCK

/SO

/SI
/

SCK

/EVND
/

EVNB

/TOD

FP-80B

HD404639R Series

Pin Description

Item

Symbol

Pin Number I/O

Function

Power

Applies power voltage

supply

GND

Connected to ground

Test

TEST

Used for factory testing only: Connect this pin to V

Reset

RESET

Resets the MCU

Oscillator

OSC

Input/output pins for the internal oscillator circuit:
Connect them to a ceramic oscillator, crystal, or connect
OSC

to an external oscillator circuit

OSC

Used for a 32.768-kHz crystal for clock purposes. If not to
be used, fix the X1 pin to V

and leave the X2 pin open.

Port

1324

I/O

Input/output pins addressed by individual bits; pins D

are high-current sink pins that can each supply up to

15 mA, D

are high-current source pins that can each

supply up to 10 mA

, D

25, 26

Input pins addressable by individual bits

2775

I/O

Input/output pins addressable in 4-bit units

,RE

Input pins addressable in 4-bit units

Interrupt

INT

2630

Input pins for external interrupts

Stop clear

STOPC

Input pin for transition from stop mode to active mode

Serial

SCK

44, 48

I/O

Serial interface clock input/output pin

interface

, SI

45, 49

Serial interface receive data input pin

, SO

46, 50

Serial interface transmit data output pin

Timer

TOB, TOC, TOD 3941

Timer output pins

EVNB

, EVND

42, 43

Event count input pins

DTMF

TONER

Output pin for DTMF row signals

TONEC

Output pin for DTMF column signals.

ref

Reference voltage pin for DTMF signals.
Voltage conditions being V

ref

GND

Voltage
comparator

COMP

Analog input pins for voltage comparator

ref

Reference voltage pin for inputting the threshold voltage
of the analog input pin.

Division
rate

SEL

Input pin for selecting system clock division rate after
RESET input or after stop mode cancellation.
1/4 division rate: Connect it to V

1/32 division rate:

Connect it to GND

HD404639R Series

Block Diagram

System control

External
interrupt

Timer

Serial

interface

Serial

interface

Compa-

rator

DTMF

Internal data bus

Internal address bus

RAM

(1,152

4 bit)

(2 bit)

(4 bit)

SPX

(4 bit)

(1 bit)

(4 bit)

(10 bit)

(14 bit)

Insruction

decoder

CPU

R0
R1

R1
R2

R2
R3

R3
R4

R4
R5

R5
R6

R6
R7

R7
R8

R8
R9

R9
RA

RA
RB

RESET

TEST

STOPC

OSC

SEL

GND

TOC

EVND
TOD

INT
INT

INT
INT
INT

SI
SO

SCK

VCref
COMP

COMP

VTref
TONER
TONEC

R0 port

R1 port

R2 port

R3 port

R4 port

RD port

0
1
2
3

0
1
2
3
0
1
2
3

0
1
2
3

R5 port

R6 port

R7 port

R8 port

R9 port

RA port

RB port

RC port

RE port

SI
SO

SCK

ROM

(16,384

10 bit)

(8,192

10 bit)

D port

High-current
source pins

D
D
D
D
D
D
D
D
D
D
D
D
D
D

EVNB

TOB

High-current
sink pins

SPY

(4 bit)

ALU

HD404639R Series

Memory Map

ROM Memory Map

The ROM memory map is shown in figure 1 and described below.

4095

4096

16383

$000F

$0FFF

$1000

$3FFF

$0010

$003F

$0040

Vector address

Zero-page subroutine

(64 words)

Pattern

(4,096 words)

Program

(8,192 words)

2
3

4
5

6
7
8
9

10
11
12

13
14
15

$0000

$0000
$0001

$0002
$0003

$0004
$0005

$0006
$0007

$0008
$0009

$000A
$000B

$000C
$000D

$000E
$000F

JMPL instruction

(Jump to RESET,

STOPC

routine)

JMPL instruction

(Jump to

INT

routine)

JMPL instruction

(Jump to timer A routine)

JMPL instruction

(Jump to timer B, INT routine)

JMPL instruction

(Jump to timer C, INT routine)

JMPL instruction

(Jump to timer D, INT routine)

JMPL instruction

(Jump to

INT

routine)

JMPL instruction

(Jump to serial 1, serial 2 routine)

Program

(16,384 words)

For HD404638R, HD40A4638R

For HD404639R, HD40A4639R,

HD407A4639R

8191

8192

$1FFF

$2000

Figure 1 ROM Memory Map

Vector Address Area ($0000$000F): Reserved for JMPL instructions that branch to the start addresses
of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the
vector address.

Zero-Page Subroutine Area ($0000$003F): Reserved for subroutines. The program branches to a
subroutine in this area in response to the CAL instruction.

Pattern Area ($0000$0FFF): Contains ROM data that can be referenced with the P instruction.

Program Area ($0000$1FFF (HD404638R, HD40A4638R), $0000$3FFF (HD404639R,
HD40A4639R, HD407A4639R)): Used for program coding.

HD404639R Series

RAM Memory Map

The MCU contains a 1,152-digit

4-bit RAM area consisting of a memory register area, a data area, and a

stack area. In addition, an interrupt control bits area, special register area, and register flag area are mapped
onto the same RAM memory space as a RAM-mapped register area outside the above areas. The RAM
memory map is shown in figure 2 and described as follows.

RAM-Mapped Register Area ($000$03F):

Interrupt Control Bits Area ($000$003)

This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit
manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the
instructions can be used for each bit. Limitations on using the instructions are shown in figure 4.

Special Function Register Area ($004$01E, $024$03F)

This area is used as mode registers and data registers for external interrupts, serial interface 1, serial
interface 2, timer/counters, voltage comparator, and as data control registers for I/O ports. The
structure is shown in figures 2 and 5. These registers can be classified into three types: write-only (W),
read-only (R), and read/write (R/W). RAM bit manipulation instructions cannot be used for these
registers.

This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3).
These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and
TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using
the instructions are shown in figure 4.

Memory Register (MR) Area ($040$04F): Consisting of 16 addresses, this area (MR0MR15) can be
accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6.

Data Area ($090$2EF): Consists of 464 digits from $090 to $25F in two banks, which can be selected
by setting the bank register (V: $03F). Before accessing this area, set the bank register to the required
value (figure 7). The area from $260 to $2EF is accessed without setting the bank register.

Stack Area ($3C0$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and
carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a
16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save
conditions are shown in figure 6.

The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can
only be restored by the RTNI instruction. Any unused space in this area is used for data storage.

HD404639R Series

Compare control register

Data

(464 digits)

V = 1

(bank = 1)

$000

608

960

1023

$040
$050

4
5
6
7

12
13
14

8
9

10
11

16
17

18
19
20

$003

$004

$005

$006

$007

$008
$009

$00A
$00B

$00C

$00D

$00E
$00F

$010

$011
$012

$013
$014

$020
$023

$032
$033

$034
$035
$036
$037
$038

$03F

$00A

$00B

$00E

$00F

R/W

W
W

W
W
W
W

W
W
W

R/W

R/W
R/W

R/W

$090

$25F

54
55

$3C0

$260

RAM-mapped registers

Memory registers (MR)

Not used

Data (464 digits 2)
V = 0 (bank 0)
V = 1 (bank 1)

Data (144 digits)

Stack (64 digits)

Interrupt control bits area

Port mode register A
Serial mode register 1A
Serial data register 1 lower
Serial data register 1 upper
Timer mode register A
Timer mode register B1

Timer B

Miscellaneous register
Timer mode register C1

Timer C

Timer mode register B2

Timer mode register D2

Port R0 DCR
Port R1 DCR
Port R2 DCR
Port R3 DCR

Port D to D DCR
Port D to D DCR
Port D to D DCR

Not used

V register

Data

(464 digits)

V = 0

(bank = 0)

The data area has two banks:
bank 0 (V = 0) to bank 1 (V = 1)

Timer read register B lower

Timer read register B upper

Timer read register C lower

Timer read register C upper

Timer write register B lower

Timer write register B upper

Timer write register C lower

Timer write register C upper

R:
W:
R/W:

$090

Read only
Write only
Read/Write

Note:

$011

$012

17
18

Timer read register D lower

Timer read register D upper

Timer write register D lower

Timer write register D upper

144

Timer mode register D1

R/W
R/W

Timer D

Timer mode register C2

$015

$016

Compare data register

$017

$024

$025

$026

$027

$028

$029

$02A

$02B

24
25

28
29

30
31

$018

$019
$01A
$01B

$01C
$01D
$01E
$01F

$3FF

Compare enable register

Serial mode register 2A

Serial mode register 2B
Serial data register 2 lower
Serial data register 2 upper

W
W

44
45
46
47

Port mode register B
Port mode register C

Detection edge select register 1

Detection edge select register 2

Serial mode register 1B

System clock select register 1

Not used

Port R4 DCR
Port R5 DCR
Port R6 DCR
Port R7 DCR

W
W
W
W
W
W
W
W
W

W
W
W
W

$02C
$02D
$02E
$02F

$031

$030

48
49
50
51
52

Two registers are mapped
on the same area.

Not used

752

$2F0

R/W
R/W
R/W

(PMRA)

(SM1A)

(SR1L)

(SR1U)

(TMA)

(TMB1)

(TRBL/TWBL)

(TRBU/TWBU)

(MIS)

(TMC1)

(TRCL/TWCL)

(TRCU/TWCU)

(TMD1)

(TRDL/TWDL)

(TRDU/TWDU)

(TMB2)

(TMC2)
(TMD2)

(CCR)
(CDR)

(CER)

(TGM)

(TGC)

(SM2A)
(SM2B)

(SR2L)

(SR2U)

(PMRB)

(PMRC)

(SM1B)

(SSR1)
(SSR2)

(ESR1)

(ESR2)

(DCD0)
(DCD1)
(DCD2)

(DCR0)
(DCR1)
(DCR2)
(DCR3)
(DCR4)
(DCR5)
(DCR6)
(DCR7)
(DCR8)
(DCR9)

(DCRA)
(DCRB)

(DCRC)

R/W

Not used

Port R8 DCR
Port R9 DCR
Port RA DCR
Port RB DCR
Port RC DCR

$039
$03A
$03B
$03C

(TRBL)

(TRBU)

(TRCL)

(TRCU)

(TRDL)

(TRDU)

(TWBL)

(TWBU)

(TWCL)

(TWCU)

(TWDL)

(TWDU)

TG mode register

TG control register

System clock select register 2

Figure 2 RAM Memory Map

HD404639R Series

Bit 3

Bit 2

Bit 1

Bit 0

IMTA

(IM of timer A)

IFTA

(IF of timer A)

IM1

(IM of

INT

)

IF1

(IF of

INT

)

IMTC

(IM of timer C)

IFTC

(IF of timer C)

IMTB

(IM of timer B)

IFTB

(IF of timer B)

IMS1

(IM of serial

interface 1)

IFS1

(IF of serial

interface 1)

IMTD

(IM of timer D)

IFTD

(IF of timer D)

$000

$001

$002

$003

Interrupt control bits area

IM0

(IM of

INT

)

IF0

(IF of

INT

)

RSP

(Reset SP bit)

(Interrupt

enable flag)

ICSF

(Input capture

status flag)

IM3

(IM of INT

)

IF3

(IF of INT

)

IM2

(IM of INT

)

IF2

(IF of INT

)

IMS2

(IM of serial

interface 2)

IFS2

(IF of serial

interface 2)

IM4

(IM of INT )

IF4

(IF of INT )

$020

$021

$022

$023

DTON

(Direct transfer

on flag)

WDON

(Watchdog

on flag)

LSON

(Low speed

on flag)

ICEF

(Input capture

error flag)

RAME

(RAM enable

flag)

Not used

IF:
IM:
IE:
SP:

Interrupt request flag
Interrupt mask
Interrupt enable flag
Stack pointer

Bit 3

Bit 2

Bit 1

Bit 0

Not used

Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas

LSON

ICSF
ICEF

RAME

RSP

WDON

Not used

DTON

SEM/SEMD

REM/REMD

TM/TMD

Allowed

Not executed

Allowed

Not executed

Allowed

Inhibited

Allowed

Not executed

Inhibited

Not executed in active mode

Allowed

Used in subactive mode

Not executed

Inhibited

Note: WDON is reset by MCU reset or by

STOPC

enable for stop mode cancellation.

DTON is always reset in active mode.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.

Figure 4 Usage Limitations of RAM Bit Manipulation Instructions

HD404639R Series

$000

$003

PMRA $004

SM1A $005

SR1L $006

SR1U $007

TMA $008

TMB1 $009

TRBL/TWBL $00A

TRBU/TWBU $00B

MIS $00C

TMC1 $00D

TRCL/TWCL $00E

TRCU/TWCU $00F

TMD1 $010

TRDL/TWDL $011

TRDU/TWDU $012

TMB2 $013

TMC2 $014

TMD2 $015

CCR $016

CDR $017

CER $018

TGM $019

TGC $01A

SM2A $01B

SM2B $01C

SR2L $01D

SR2U $01E

$020

$023

PMRB $024

PMRC $025

ESR1 $026

ESR2 $027

SM1B $028

SSR1 $029

SSR2 $02A

DCD0 $02C

DCD1 $02D

DCD2 $02E

DCR0 $030

DCR1 $031

DCR2 $032

DCR3 $033

DCR4 $034

DCR5 $035

DCR6 $036

DCR7 $037

DCR8 $038

DCR9 $039

DCRA $03A

DCRB $03B

DCRC $03C

V $03F

Bit 3

Bit 2

Bit 1

Interrupt control bits area

/SI

/SO

/SI

/SO

Serial transmit clock speed selection 1

Serial data register 1 (lower digit)

Serial data register 1 (upper digit)

Clock source selection (timer A)

Clock source selection (timer B)

Timer B register (lower digit)

Timer B register (upper digit)

PMOS control Interrupt frame period selection

Clock source selection (timer C)

Timer C register (lower digit)

Timer C register (upper digit)

Clock source selection (timer D)

Timer D register (lower digit)

Timer D register (upper digit)

Not used

Timer-B output mode selection

Not used

Timer-C output mode selection

Timer-D output mode selection

Internal reference voltages level

Result of each analog input comparison

SCK

Serial transmit clock speed selection 2

/INT

/EVND

INT

detection edge selection

INT

detection edge selection

EVND detection edge selection

Not used

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Not used

Port R0

DCR

Port R1

DCR

Port R2

DCR

Port R3

DCR

Port R4

DCR

Port R5

DCR

Port R6

DCR

Port R7

DCR

Port R0

DCR

Port R1

DCR

Port R2

DCR

Port R3

DCR

Port R4

DCR

Port R5

DCR

Port R6

DCR

Port R7

DCR

Port R0

DCR

Port R1

DCR

Port R2

DCR

Port R3

DCR

Port R4

DCR

Port R5

DCR

Port R6

DCR

Port R7

DCR

Port R0

DCR

Port R1

DCR

Port R2

DCR

Port R3

DCR

Port R4

DCR

Port R5

DCR

Port R6

DCR

Port R7

DCR

Not used

5. Comparator switch
6. Reference voltage selection
7. Comparator selection
8. TONEC output control
9. TONER output control

10. SO output control in idle states
11. Serial clock source selection 2
12. SO output level control in idle states
13. Transmit clock source selection 1

/INT

STOPC

INT

EVNB

SCK

Bit 0

Not used

PMOS control

Serial data register 2 (lower digit)

Serial data register 2 (upper digit)

Not used

System clock selection

Port R8

DCR

Port R9

DCR

Port RA

DCR

Port RB

DCR

Port R8

DCR

Port R9

DCR

Port RA

DCR

Port RB

DCR

Port R8

DCR

Port R9

DCR

Port RA

DCR

Port RB

DCR

Port R8

DCR

Port R9

DCR

Port RA

DCR

Port RB

DCR

Port RC

DCR

TONEC output frequency

TONER output frequency

DTMF enable

Not used

System clock selection

System clock division rate

Not used

1. Timer-A/time-base
2. Auto-reload on/off
3. Pull-up MOS control
4. Input capture selection

Notes:

14. 32-kHz oscillation stop
15. 32-kHz oscillation division ratio
16. Bank 0 to bank 1 selection

/INT

INT

detection edge selection

Not used

Figure 5 Special Function Register Area

HD404639R Series

Memory registers

65
66
67
68
69
70
71

73
74
75
76
77
78
79

$040

$041
$042

$043

$044

$045
$046

$047
$048
$049

$04A
$04B
$04C
$04D
$04E
$04F

960

$3C0

1023

$3FF

MR(0)
MR(1)
MR(2)
MR(3)
MR(4)
MR(5)
MR(6)
MR(7)
MR(8)
MR(9)

Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1

MR(10)
MR(11)
MR(12)
MR(13)
MR(14)
MR(15)

Bit 3

Bit 2

Bit 1

Bit 0

$3FC

$3FD

$3FE

$3FF

1020

1021

1022

1023

PC PC :
ST: Status flag
CA: Carry flag

Program counter

Stack area

Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position

Bit

Initial value

Read/Write

Bit name

Not used

R/W

Not used

Bank area selection

Bank 0 is selected

Bank 1 is selected

Note: After reset, the value in the bank register is 0, and therefore bank 0 is

selected.

Bank register (V: $03F)

Figure 7 Bank Register (V)

HD404639R Series

Functional Description

Registers and Flags

The MCU has nine registers and two flags for CPU operations. They are shown in figure 8 and described
below.

(B)

(A)

(W)

(X)

(Y)

(SPX)

(SPY)

(CA)

(ST)

(PC)

(SP)

Accumulator

B register

W register

X register

Y register

SPX register

SPY register

Carry

Status

Program counter
Initial value: 0,
no R/W

Stack pointer
Initial value: $3FF, no R/W

Initial value: Undefined, R/W

Initial value: 1, no R/W

Figure 8 Registers and Flags

Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit
(ALU) and transfer data between memory, I/O, and other registers.

W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for
indirect RAM addressing. The Y register is also used for D-port addressing.

HD404639R Series

SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers.

Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is
affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an
interrupt and popped from the stack by the RTNI instruction--but not by the RTN instruction.

Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare
instruction, not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the
BR, BRL, CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic,
compare, or bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is
read, regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the
stack during an interrupt and popped from the stack by the RTNI instruction--but not by the RTN
instruction.

Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being
executed.

Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is
initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and
incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a
stack can be used up to 16 levels.

The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD
instruction.

Reset

The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is
cancelled, RESET must be high for at least one t

to enable the oscillator to stabilize. During operation,

RESET must be high for at least two instruction cycles.

Initial values after MCU reset are listed in table 1.

HD404639R Series

Table 1 Initial Values After MCU Reset

Item

Abbr.

Initial Value Contents

Program counter

(PC)

$0000

Indicates program execution point
from start address of ROM area

Status flag

(ST)

Enables conditional branching

Stack pointer

(SP)

$3FF

Stack level 0

Interrupt
flags/mask

Interrupt enable flag

(IE)

Inhibits all interrupts

Interrupt request flag

(IF)

Indicates there is no interrupt
request

Interrupt mask

(IM)

Prevents (masks) interrupt
requests

I/O

Port data register

(PDR)

All bits 1

Enables output at level 1

Data control register

(DCD0DCD2)

All bits 0

Turns output buffer off (to high
impedance)

(DCR0DCRC)

All bits 0

Port mode register A

(PMRA)

0000

Refer to description of port mode
register A

Port mode register B

(PMRB)

0000

Refer to description of port mode
register B

Port mode register C
bits 3, 1, 0

(PMRC3, PMRC1,
PMRC0)

000

Refer to description of port mode
register C

Detection edge select
register 1

(ESR1)

0000

Disables edge detection

Detection edge select
register 2

(ESR2)

0000

Disables edge detection

Timer/
counters,

Timer mode register A

(TMA)

0000

Refer to description of timer mode
register A

serial
interface

Timer mode register B1 (TMB1)

0000

Refer to description of timer mode
register B1

Timer mode register B2 (TMB2)

- - 00

Refer to description of timer mode
register B2

Timer mode register C1 (TMC1)

0000

Refer to description of timer mode
register C1

Timer mode register C2 (TMC2)

- 000

Refer to description of timer mode
register C2

Timer mode register D1 (TMD1)

0000

Refer to description of timer mode
register D1

Timer mode register D2 (TMD2)

0000

Refer to description of timer mode
register D2

Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table.

2. X indicates invalid value. indicates that the bit does not exist.

HD404639R Series

Item

Abbr.

Initial
Value

Contents

Timer/
counters,

Serial mode register 1A

(SM1A)

0000

Refer to description of serial mode
register 1A

serial
interface

Serial mode register 1B

(SM1B)

- - X0

Refer to description of serial mode
register 1B

Serial mode register 2A

(SM2A)

0000

Refer to description of serial mode
register 2A

Serial mode register 2B

(SM2B)

- 0X0

Refer to description of serial mode
register 2B

Prescaler S

(PSS)

$000

Prescaler W

(PSW)

$00

Timer counter A

(TCA)

$00

Timer counter B

(TCB)

$00

Timer counter C

(TCC)

$00

Timer counter D

(TCD)

$00

Timer write register B

(TWBU, TWBL)

$X0

Timer write register C

(TWCU, TWCL) $X0

Timer write register D

(TWDU, TWDL) $X0

Octal counter

000

Comparator Compare control register (CCR)

0000

Refer to description of voltage comparator

Compare enable register (CER)

0000

Refer to description of voltage comparator

Bit register

Low speed on flag

(LSON)

Refer to description of operating modes

Watchdog timer on flag

(WDON)

Refer to description of timer C

Direct transfer on flag

(DTON)

Refer to description of operating modes

Input capture status flag

(ICSF)

Refer to description of timer D

Input capture error flag

(ICEF)

Refer to description of timer D

Others

Miscellaneous register

(MIS)

0000

Refer to description of operating modes,
and oscillator circuit

System clock select
register 1 bits 20

(SSR12
SSR10)

000

Refer to description of operating modes,
and oscillator circuit

System clock select
register 2

(SSR2)

0000

Bank register

(V)

- - - 0

Refer to description of RAM memory map

Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table.

2. X indicates invalid value. indicates that the bit does not exist.

HD404639R Series

Item

Abbr.

Status After
Cancellation of Stop
Mode by

STOPC

Input

Status After
Cancellation of
Stop Mode by
MCU Reset

Status After all
Other Types of
Reset

Carry flag

(CA)

Pre-stop-mode values are not guaranteed;
values must be initialized by program

Pre-stop-mode
values are not
guaranteed; values
must be initialized by
program

Accumulator

(A)

B register

(B)

W register

(W)

X/SPX register

(X/SPX)

Y/SPY register

(Y/SPY)

Serial data register

(SRL, SRU)

RAM

Pre-stop-mode values are retained

RAM enable flag

(RAME)

Port mode register C bit 2 (PMRC2)

Pre-stop-mode values
are retained

System clock select
register 1 bit 3

(SSR13)

Interrupts

The MCU has 11 interrupt sources: five external signals (

I NT

INT

, INT

), four

timer/counters (timers A, B, C, and D), and two serial interfaces (serial interface 1, serial interface 2).

An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt
source, and an interrupt enable flag (IE) controls the entire interrupt process.

Some vector addresses are shared by two different interrupts. They are timer B and INT

, timer C and

INT

, timer D and INT

, and serial interface 1 and serial interface 2. So the type of request that has

occurred must be checked at the beginning of interrupt processing.

Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $022 to $023 in RAM are
reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions.

The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag
(IE) and the IF to 0 and the interrupt mask (IM) to 1.

A block diagram of the interrupt control circuit is shown in figure 9, interrupt priorities and vector
addresses are listed in table 2, and interrupt processing conditions for the 11 interrupt sources are listed in
table 3.

HD404639R Series

An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the
interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to
that interrupt source.

The interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in
figure 11. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The
IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack
during the second and third cycles, and the program jumps to the vector address to execute the instruction
in the third cycle.

Program the JMPL instruction at each vector address to branch the program to the start address of the
interrupt program, and reset the IF by a software instruction within the interrupt program.

Table 2 Vector Addresses and Interrupt Priorities

Reset/Interrupt

Priority

Vector Address

RESET,

STOPC*

$0000

INT

$0002

INT

$0004

Timer A

$0006

Timer B, INT

$0008

Timer C, INT

$000A

Timer D, INT

$000C

Serial 1 and 2

$000E

Note:

The

STOPC

interrupt request is valid only in stop mode

Table 3 Interrupt Processing and Activation Conditions

Interrupt Source

Interrupt Control Bit

INT

Timer A

Timer B
or INT

Timer C or
INT

Timer D or
INT

Serial 1 or
Serial 2

IF0

IM0

IF1

IM1

IFTA

IMTA

IFTB

IMTB

+ IF2

IM2

IFTC

IMTC

+ IF3

IM3

IFTD

IMTD

+ IF4

IM4

IFS1

IMS1

+ IFS2

IMS2

Note:

Can be either 0 or 1. Their values have no effect on operation.

HD404639R Series

Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt
processing and set by the RTNI instruction, as listed in table 4.

Table 4 Interrupt Enable Flag (IE: $000, Bit 0)

Interrupt Enabled/Disabled

Disabled

Enabled

External Interrupts (

INT

, INT

INT

): Five external interrupt signals.

External Interrupt Request Flags (IF0IF4: $000, $001, $022, $023): IF0 and IF1 are set at the falling
edge of signals input to

INT

and

INT

, and IF2IF4 are set at the rising or falling edge of signals input to

INT

, as listed in table 5. The INT

INT

interrupt edges are selected by the detection edge select

registers (ESR1, ESR2: $026, $027) as shown in figures 12 and 13.

Table 5 External Interrupt Request Flags (IF0IF4: $000, $001, $022, $023)

IF0IF4

Interrupt Request

Yes

Bit

Initial value

Read/Write

Bit name

ESR13

ESR12

ESR10

ESR11

Detection edge selection register 1 (ESR1: $026)

ESR11

ESR10

INT

detection edge

No detection

Falling-edge detection

Rising-edge detection

Double-edge detection

ESR13

ESR12

INT

detection edge

No detection

Falling-edge detection

Rising-edge detection

Double-edge detection

Note: Both falling and rising edges are detected.

Figure 12 Detection Edge Selection Register 1 (ESR1)

HD404639R Series

Bit

Initial value

Read/Write

Bit name

ESR23

ESR22

ESR21

Detection edge selection register 2 (ESR2: $027)

ESR23

ESR22

EVND detection edge

No detection

Falling-edge detection

Rising-edge detection

Double-edge detection

Note: Both falling and rising edges are detected.

ESR20

ESR21

ESR20

INT detection edge

No detection

Falling-edge detection

Rising-edge detection

Double-edge detection

Figure 13 detection Edge Selection Register 2 (ESR2)

External Interrupt Masks (IM0IM4: $000, $001, $022, $023): Prevent (mask) interrupt requests
caused by the corresponding external interrupt request flags, as listed in table 6.

Table 6 External Interrupt Masks (IM0IM4: $000, $001, $022, $023)

IM0IM4

Interrupt Request

Enabled

Disabled (masked)

Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in
table 7.

Table 7 Timer A Interrupt Request Flag (IFTA: $001, Bit 2)

IFTA

Interrupt Request

Yes

Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the
timer A interrupt request flag, as listed in table 8.

HD404639R Series

Table 8 Timer A Interrupt Mask (IMTA: $001, Bit 3)

IMTA

Interrupt Request

Enabled

Disabled (masked)

Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as listed in
table 9.

Table 9 Timer B Interrupt Request Flag (IFTB: $002, Bit 0)

IFTB

Interrupt Request

Yes

Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the
timer B interrupt request flag, as listed in table 10.

Table 10 Timer B Interrupt Mask (IMTB: $002, Bit 1)

IMTB

Interrupt Request

Enabled

Disabled (masked)

Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in
table 11.

Table 11 Timer C Interrupt Request Flag (IFTC: $002, Bit 2)

IFTC

Interrupt Request

Yes

Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the
timer C interrupt request flag, as listed in table 12.

Table 12 Timer C Interrupt Mask (IMTC: $002, Bit 3)

IMTC

Interrupt Request

Enabled

Disabled (masked)

HD404639R Series

Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the
rising or falling edge of signals input to EVND when the input capture function is used, as listed in table
13.

Table 13 Timer D Interrupt Request Flag (IFTD: $003, Bit 0)

IFTD

Interrupt Request

Yes

Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the
timer D interrupt request flag, as listed in table 14.

Table 14 Timer D Interrupt Mask (IMTD: $003, Bit 1)

IMTD

Interrupt Request

Enabled

Disabled (masked)

Serial Interrupt Request Flags (IFS1: $003, Bit 2; IFS2: $023, Bit 2): Set when data transfer is
completed or when data transfer is suspended, as listed in table 15.

Table 15 Serial Interrupt Request Flag (IFS1: $003, Bit 2; IFS2: $023, Bit 2)

IFS1, IFS2

Interrupt Request

Yes

Serial Interrupt Masks (IMS1: $003, Bit 3; IMS2: $023, Bit 3): Prevents (masks) an interrupt request
caused by the serial interrupt request flag, as listed in table 16.

Table 16 Serial Interrupt Mask (IMS1: $003, Bit 3; IMS2: $023, Bit 3)

IMS1, IMS2

Interrupt Request

Enabled

Disabled (masked)

HD404639R Series

Operating Modes

The MCU has five operating modes as shown in table 17. The operations in each mode are listed in tables
18 and 19. Transitions between operating modes are shown in figure 14.

Table 17 Operating Modes and Clock Status

Mode Name

Active

Standby

Stop

Watch

Subactive

Activation
method

RESET
cancellation,
interrupt
request

STOPC

cancellation in
stop mode,
STOP/SBY
instruction in
subactive
mode (when
direct transfer
is selected)

SBY
instruction

STOP
instruction when
TMA3 = 0

STOP
instruction when
TMA3 = 1

STOP/SBY
instruction in
subactive mode
(when direct
transfer is not
selected)

INT

or timer A

interrupt request
from watch
mode when
LSON = 1

Status

System
oscillator

Stopped

Subsystem
oscillator

Cancellation
method

RESET input,
STOP/SBY
instruction

RESET
input,
interrupt
request

RESET input,

STOPC

input in

stop mode

RESET input,

INT

or timer A

interrupt request

RESET input,
STOP/SBY
instruction

Notes: OP implies in operation

1. Operating or stopping the oscillator can be selected by setting bit 3 of system clock select

HD404639R Series

Table 18 Operations in Low-Power Dissipation Modes

Function

Stop Mode

Watch Mode

Standby Mode

Subactive Mode

CPU

Reset

Retained

RAM

Retained

Timer A

Reset

Timer B

Reset

Stopped

Timer C

Reset

Stopped

Timer D

Reset

Stopped

Serial interface 1, 2

Reset

Stopped

DTMF

Reset

Comparator

Reset

Stopped

I/O

Reset

Retained

Notes: OP implies in operation

1. Output pins are at high impedance.

2. Transmission/reception is activated if a clock is input in external clock mode. However, all

interrupts stop.

Table 19 I/O Status in Low-Power Dissipation Modes

Output

Input

Standby mode, watch
mode

Stop mode

Active mode, subactive
mode

Retained

High impedance

Input enabled

Retained or output of
peripheral functions

High impedance

Input enabled

HD404639R Series

Reset by

RESET input or

by watchdog timer

OSC

CPU

CLK

PER

Oscillate
Oscillate
Stop
f

cyc

OSC

CPU

CLK

PER

Oscillate
Oscillate
Stop
f

cyc

OSC

CPU

CLK

PER

Oscillate
Oscillate
f

cyc

OSC

CPU

CLK

PER

Oscillate
Oscillate
f

cyc

OSC

CPU

CLK

PER

Stop
Oscillate
f

SUB

OSC

CPU

CLK

PER

Stop
Stop
Stop
Stop
Stop

OSC

CPU

CLK

PER

Stop
Oscillate
Stop
f

Stop

OSC

CPU

CLK

PER

Stop
Oscillate
Stop
f

Stop

Standby mode

Stop mode

(TMA3 = 0, SSR13 = 1)

Watch mode

Subactive
mode

(TMA3 = 1)

(TMA3 = 1, LSON = 0)

(TMA3 = 1, LSON = 1)

SBY

Interrupt

SBY

Interrupt

STOP

INT

timer A

STOP

1. Interrupt source
2. STOP/SBY (DTON = 1, LSON = 0)
3. STOP/SBY (DTON = 0, LSON = 0)
4. STOP/SBY (DTON = Don't care, LSON = 1)

OSC

cyc

SUB

LSON:
DTON:

Main oscillation frequency
Suboscillation frequency
for time-base
f /4 or f /8 or
f /16 or f /32
(software selectable)

OSC

/8 or f

(software selectable)
f

System clock
Clock for time-base
Clock for other
peripheral functions
Low speed on flag
Direct transfer on flag

Active
mode

Notes:

CPU

CLK

PER

OSC

CPU

CLK

PER

Stop
Oscillate
Stop
Stop
Stop

(TMA3 = 0, SSR13 = 0)

RESET1

RESET2

RAME = 0

RAME = 1

INT

timer A

(TMA3 = 0)

STOP

STOPC

STOP

OSC

Figure 14 MCU Status Transitions

HD404639R Series

Active Mode: All MCU functions operate according to the clock generated by the system oscillators OSC

and OSC

Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction
execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the
D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and
serial interface continue to operate. The power dissipation in this mode is lower than in active mode
because the CPU stops.

The MCU enters standby mode when the SBY instruction is executed in active mode.

Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input,
the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next
instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is
0, the interrupt request is left pending and normal instruction execution continues. A flowchart of
operation in standby mode is shown in figure 15.

Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power
dissipation in this mode is the least of all modes. The OSC

and OSC

oscillator stops. For the X1 and X2

oscillator to operate or stop can be selected by setting bit 3 of system clock select register 1 (SSR1: $029;
operating: SSR13 = 0, stop: SSR13 = 1) (figure 24). The MCU enters stop mode if the STOP instruction is
executed in active mode when bit 3 of timer mode register A (TMA: $008) is set to 0 (TMA3 = 0) (figure
41).

Stop mode is terminated by a RESET input or a

STOPC input as shown in figure 16. RESET or STOPC

must be applied for at least one t

to stabilize oscillation (refer to the AC Characteristics section). When

the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained,
but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register,
carry flag, and serial data register cannot be guaranteed.

Watch Mode: In watch mode, the clock function (timer A) using the X1 and X2 oscillator operates but
other function operations stop. Therefore, the power dissipation in this mode is the second least to stop
mode, and this mode is convenient when only clock display is used. In this mode, the OSC

and OSC

oscillator stops, but the X1 and X2 oscillator operates. The MCU enters watch mode if the STOP
instruction is executed in active mode when TMA3 = 1, or if the STOP or SBY instruction is executed in
subactive mode.

Watch mode is terminated by a RESET input or a timer-A/

INT

interrupt request. For details of RESET

input, refer to the Stop Mode section. When terminated by a timer-A/

INT

interrupt request, the MCU

enters active mode if LSON is 0, or subactive mode if LSON is 1. After an interrupt request is generated,
the time required to enter active mode is t

for a timer A interrupt, and T

(where T + t

< T

< 2T + t

)

for an

INT

interrupt, as shown in figures 17 and 18.

Operation during mode transition is the same as that at standby mode cancellation (figure 15).

HD404639R Series

Standby

Oscillator: Active
Peripheral clocks: Active
All other clocks: Stop

Yes

(SBY
only)

Watch

Oscillator: Stop
Suboscillator: Active
Peripheral clocks: Stop
All other clocks: Stop

Restart

processor clocks

Reset MCU

Execute

next instruction

Accept interrupt

Restart

processor clocks

Yes

IF = 1,

IM = 0, and

IE = 1?

RESET = 1?

IF0 ·

IM0

= 1?

IF1 ·

IM1

= 1?

IFTA ·

IMTA

= 1?

IFTB ·

IMTB

+ IF2 ·

IM2

= 1?

IFTC ·

IMTC

+ IF3 ·

IM3

= 1?

IFTD ·

IMTD

+ IF4 ·

IM4

= 1?

Yes

IFS1 ·

IMS1

+ IFS2 ·

IMS2

= 1?

Stop

Oscillator: Stop
Suboscillator: Active/Stop
Peripheral clocks: Stop
All other clocks: Stop

RESET = 1?

STOPC

= 0?

RAME = 1

RAME = 0

Yes

Execute

next instruction

(SBY
only)

Figure 15 MCU Operation Flowchart

HD404639R Series

Stop mode

Oscillator

Internal

clock

STOP instruction execution

res

(stabilization period)

res

RESET

STOPC

Figure 16 Timing of Stop Mode Cancellation

Subactive Mode: The OSC

and OSC

oscillator stops and the MCU operates with a clock generated by

the X1 and X2 oscillator. In this mode, functions other than the DTMF generator operate. However,
because the operating clock is slow, the power dissipation becomes low, next to watch mode.

The CPU instruction execution speed can be selected as 244

s or 122

s by setting bit 2 (SSR12) of

system clock select register 1 (SSR1: $029). Note that the SSR12 value must be changed in active mode.
If the value is changed in subactive mode, the MCU may malfunction.

When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active
mode, depending on the statuses of the low speed on flag (LSON: $020, bit 0) and the direct transfer on
flag (DTON: $020, bit 3).

Subactive mode is an optional function that the user must specify on the function option list.

Interrupt Frame: In watch and subactive modes,

CLK

is applied to timer A and the

INT

circuit.

Prescaler W and timer A operate as the time-base and generate the timing clock for the interrupt frame.
Three interrupt frame lengths (T) can be selected by setting the miscellaneous register (MIS: $00C) (figure
18).

In watch and subactive modes, the timer-A/

INT

interrupt is generated synchronously with the interrupt

frame. The interrupt request is generated synchronously with the interrupt strobe timing except during
transition to active mode. The falling edge of the

INT

signal is input asynchronously with the interrupt

frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the
falling edge. An overflow and interrupt request in timer A is generated synchronously with t he interrupt
strobe timing.

Note on Use: When the MCU is in watch mode or sub-active mode and if the high level period before the
falling edge of

INT

is shorter than the interrupt frame or if the low level period after the falling edge of

INT

is shorter than the interrupt frame,

INT

is not detected. Therefore, the high or low level period of

INT

must be held longer than the interrupt frame when the MCU is in watch mode or subactive mode.

HD404639R Series

T:
t :

Interrupt frame length
Oscillation stabilization period

Note : If the time from the fall of the

INT

signal until the interrupt is accepted and

active mode is entered is T

, then T

will be in the following range :

T + t

2T + t

(During the transition
from watch mode to
active mode only)

Interrupt strobe

INT

Interrupt request
generation

Active mode

Watch mode

Active mode

Oscillation
stabilization period

Figure 17 Interrupt Frame

Bit

Initial value

Read/Write

Bit name

MIS3

MIS2

MIS0

MIS1

Miscellaneous register (MIS: $00C)

MIS1

MIS0

0.24414 ms

0.12207 ms

0.24414 ms

7.8125 ms

31.25 ms

Oscillation circuit conditions

External clock input

Ceramic oscillator

15.625 ms

62.5 ms

Not used

Notes: 1.

The values of T and t

are applied when a 32.768-kHz crystal oscillator is used.

The value is applied only when direct transfer operation is used.

Buffer control.

Refer to figure 38.

MIS3

MIS2

Crystal oscillator

Figure 18 Miscellaneous Register (MIS)

HD404639R Series

Direct Transition from Subactive Mode to Active Mode: Available by controlling the direct transfer on
flag (DTON: $020, bit 3) and the low speed on flag (LSON: $020, bit 0). The procedures are described
below:

Set LSON to 0 and DTON to 1 in subactive mode.

Execute the STOP or SBY instruction.

The MCU automatically enters active mode from subactive mode after waiting for the MCU internal
processing time and oscillation stabilization time (figure 19).

Notes: 1. The DTON flag ($020, bit 3) can be set only in subactive mode. It is always reset in active

mode.

2. The transition time (T

) from subactive mode to active mode:

< T

< T + t

Subactive mode

Interrupt strobe

Direct transfer
completion timing

MCU internal
processing period

Oscillation
stabilization
time

Active mode

T:
t

STOP/SBY instruction execution

(Set LSON = 0, DTON = 1)

Interrupt frame length
Oscillation stabilization period
Transition time

Figure 19 Direct Transition Timing

Stop Mode Cancellation by

STOPC: The MCU enters active mode from stop mode by a STOPC input as

well as by RESET. In either case, the MCU starts instruction execution from the starting address (address
0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs between
cancellation by

STOPC and by RESET. When stop mode is cancelled by RESET, RAME = 0; when

cancelled by

STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop mode;

STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop mode
has been cancelled by

STOPC (for example, when the RAM contents before entering stop mode are used

after transition to active mode), execute the TEST instruction on the RAM enable flag (RAME) at the
beginning of the program.

MCU Operation Sequence: The MCU operates in the sequences shown in figures 20 to 22. It is reset by
an asynchronous RESET input, regardless of its status.

The low-power mode operation sequence is shown in figure 22. With the IE flag cleared and an interrupt
flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is

HD404639R Series

Internal Oscillator Circuit

A block diagram of the clock generation circuit is shown in figure 23. As shown in table 20, a ceramic
oscillator or crystal oscillator can be connected to OSC

and OSC

, and a 32.768-kHz oscillator can be

connected to X1 and X2. The system oscillator can also be operated by an external clock. System clock
select register 1 (SSR1: $029) and system clock select register 2 (SSR2: $02A) must be selected according
to the frequency of the oscillator connected to OSC

and OSC

(figure 24).

Note:

If the SSR10, SSR11, SSR22 and SSR23 setting does not match the oscillator frequency, the
DTMF generator and subsystems using the 32.768-kHz oscillation will malfunction.

OSC

System

oscillator

Sub-

system

oscillator

1/4 or
1/8 or

1/16 or

1/32

division

circuit*

Timing

generator

circuit

System

clock

selection

CPU with ROM,

RAM, registers,

flags, and I/O

Peripheral

function

interrupt

Time-base

interrupt

Time-base

clock

selection

1/8 or 1/4

division

circuit*

Timing

generator

circuit

Timing

generator

circuit

1/8

division

circuit

SUB

subcyc

LSON

TMA3

cyc

OSC

Wcyc

CPU

PER

CLK

Notes: 1.

1/4, 1/8, 1/16 or 1/32 division ratio can be selected by setting bits 1 and 0 of
system clock select register 2 (SSR2: $02A).
1/8 or 1/4 division ratio can be selected by setting bit 2 of system clock select
register 1 (SSR1: $029).

Figure 23 Clock Generation Circuit

HD404639R Series

The division ratio of the system clock can be selected as 1/4, 1/8, 1/16, or 1/32 by setting bits 0 and 1
(SSR20, SSR21) of system clock select register 2 (SSR2: $02A).

The values of SSR20 and SSR21 are valid after the MCU enters watch mode (SSR22 and SSR23 are valid
directly). The system clock must be stopped when the division ratio is to be changed.

There are two ways for setting the division ratio of the system clock.

The division ratio is selected by setting SSR20 and SSR21 in active mode (at this time, the presetting
values of SSR20 and SSR21 are valid). This causes the MCU to enter watch mode (system clock is
stopped). When the MCU enters active mode from watch mode, the setting values of SSR20 and
SSR21 become valid.

The division ratio can also be selected by setting SSR20 and SSR21 in subactive mode. This causes the
MCU to enter active mode via watch mode, thus validating the setting values of SSR20 and SSR21 (so
does the case of direct transition).

After RESET input or after stop mode has been cancelled, the division ratio of the system clock can be
selected as 1/4 or 1/32 by setting the SEL pin level.

1/4 division ratio: Connect SEL to V

1/32 division ratio: Connect SEL to GND.

The division ratio of the subsystem clock can be selected as 1/4 or 1/8 by setting bit 2 (SSR12) of system
clock select register 1 (SSR1: $029).

SSR12 is valid directly after being set, but in order to change the value of SSR12, the MCU must be in
active mode. If SSR12 is changed in subactive mode, the MCU will malfunction.

HD404639R Series

Table 20 Oscillator Circuit Examples

Circuit
Configuration

Circuit Constants

External clock
operation

External
oscillator

OSC

Open

OSC

Ceramic oscillator
(OSC

, OSC

)

OSC

Ceramic
oscillator

GND

Ceramic oscillator: CSB400P22 (Murata),
CSB400P (Murata)
R

= 1 M

20%

= C

= 220 pF

Ceramic oscillator: CSB800J122 (Murata),
CSB800J (Murata)
R

= 1 M

20%

= C

= 220 pF

Ceramic oscillator: CSA2.00MG (Murata)
R

= 1 M

20%

= C

= 30 pF

20%

Ceramic oscillator: CSA4.00MG (Murata)
R

= 1 M

20%

= C

= 30 pF

20%

Ceramic oscillator: CSA3.58MG (Murata)
R

= 1 M

20%

= C

= 30 pF

20%

Ceramic oscillator: CSA8.00MT (Murata)
R

= 1 M

20%

= C

= 30 pF

20%

HD404639R Series

Circuit
Configuration

Circuit Constants

Crystal oscillator
(OSC

, OSC

)

Crystal
oscillator

GND

OSC

= 1 M

20%

= C

= 1022 pF

20%

Crystal: Equivalent to circuit shown below
C

= 7 pF max

= 100

max

f = 400 kHz, 800 kHz, 2 MHz, 3.58 MHz, 4
MHz, 7.16 MHz, 8 MHz

Crystal oscillator
(X1, X2)

Crystal
oscillator

GND

Crystal: 32.768 kHz: MX38T (Nippon
Denpa)
C

= C

= 20 pF

20%

: 14 k

: 1.5 pF

Notes: 1. Since the circuit constants change depending on the crystal or ceramic oscillator and stray

capacitance of the board, the user should consult with the crystal or ceramic oscillator
manufacturer to determine the circuit parameters.

2. Wiring among OSC

, OSC

, X1, X2,

and elements should be as short as possible, and must not

cross other wiring (see figure 25).

3. If the 32.768-kHz crystal oscillator is not used, the X1

pin must be fixed to V

and X2

must be

open.

HD404639R Series

Input/Output

The MCU has 61 input/output pins (D

, R0

) and 7 input pins (D

, D

13,

, RE

). The

features are described below.

A maximum current of 15 mA is allowed for each of the pins D

to D

with a total maximum current of

less than 105 mA. In addition, D

can each act as a 10-mA maximum current source.

Some input/output pins are multiplexed with peripheral function pins such as those for the timers or
serial interface. For these pins, the peripheral function setting is done prior to the D or R port setting.
Therefore, when a peripheral function is selected for a pin, the pin function and input/output selection
are automatically switched according to the setting.

Input or output selection for input/output pins and port or peripheral function selection for multiplexed
pins are set by software.

Peripheral function output pins are CMOS output pins. Only the R4

/SO

and R5

/SO

pins can be set to

NMOS open-drain output by software.

In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output
pins are in high-impedance state.

Pins D

have built-in pull-down MOS, and other input/output pins have built-in pull-up MOS, which

can be individually turned on or off by software.

I/O buffer configuration is shown in figure 27, programmable I/O circuits are listed in table 21, and I/O pin
circuit types are shown in table 22.

Table 21-1 Programmable I/O Circuits (with Pull-Up MOS)

MIS3 (Bit 3 of MIS)

DCD, DCR

PDR

CMOS buffer

PMOS

NMOS

Pull-up MOS

Note:

-- indicates off status.

HD404639R Series

Table 22 Circuit Configurations of I/O Pins

I/O Pin Type

Circuit

Pins

Input/output
pins

Pull-up control signal

Buffer control

signal

Output data

Input data

HLT

MIS3

DCD, DCR

PDR

Input control signal

, R0

DCD

PDR

Pull-down control
signal

Buffer control signal

Output data

MIS3

HLT

Input data

Input control signal

Pull-up control signal

Buffer control

signal

Output data

Input data

HLT

MIS3

DCR

PDR

Input control signal

MIS2, SM2B2

Input pins

Input data

Input control signal

, D

, RE

HD404639R Series

I/O Pin Type

Circuit

Pins

Peripheral
function pins

Input/
output
pins

Pull-up control signal

Output data

Input data

HLT

MIS3

SCK

, SCK

SCK

, SCK

SCK

Peripheral
function pins

Output
pins

Pull-up control signal

PMOS control

signal

Output data

HLT

MIS3

, SO

MIS2, SM2B2

, SO

Pull-up control signal

Output data

HLT

MIS3

TOB, TOC, TOD

Input
pins

Input data

HLT

MIS3

, SI

INT

, etc

PDR

, SI

INT

, INT

INT

, INT

EVNB

EVND

INT

STOPC

Input data

INT

STOPC

Notes: 1. The MCU is reset in stop mode, and peripheral function selection is cancelled. The

HLT

signal

becomes low, and input/output pins enter high-impedance state.

2. The

HLT

signal is 1 in watch and subactive modes.

D Port (D

): Consist of 12 input/output pins and 2 input pins addressed by one bit. D

are high-

current sources, D

are high-current sinks, and D

and D

are input-only pins.

Pins D

are set by the SED and SEDD instructions, and reset by the RED and REDD instructions.

Output data is stored in the port data register (PDR) for each pin. All pins D

are tested by the TD and

TDD instructions.

The on/off statuses of the output buffers are controlled by D-port data control registers (DCD0DCD2:
$02C$02E) that are mapped to memory addresses (figure 28).

HD404639R Series

Pins D

and D

are multiplexed with peripheral function pins

STOPC and I

, respectively. The

peripheral function modes of these pins are selected by bits 2 and 3 (PMRC2, PMRC3) of port mode
register C (PMRC: $025) (figure 29).

R Ports (R0

RC

, RD

RE

): 49 input/output pins and 5 input pins addressed in 4-bit units. Data is input

to these ports by the LAR and LBR instructions, and output from them by the LRA and LRB instructions.
Output data is stored in the port data register (PDR) for each pin. The on/off statuses of the output buffers
of the R ports are controlled by R-port data control registers (DCR0DCRC: $030$03C) that are mapped
to memory addresses (figure 28).

Pins R0

are multiplexed with peripheral pins

I NT

INT

, respectively. The peripheral function modes

of these pins are selected by bits 03 (PMRB0PMRB3) of port mode register B (PMRB: $024) (figure
30).

Pins R3

are multiplexed with peripheral pins TOB, TOC, and TOD, respectively. The peripheral

function modes of these pins are selected by bits 0 and 1 (TMB20, TMB21) of timer mode register B2
(TMB2: $013), bits 02 (TMC20TMC22) of timer mode register C2 (TMC2: $014), and bits 03
(TMD20TMD23) of timer mode register D2 (TMD2: $015) (figures 31, 32, and 33).

Pins R3

and R4

are multiplexed with peripheral pins

EVNB and EVND, respectively. The peripheral

function modes of these pins are selected by bits 0 and 1 (PMRC0, PMRC1) of port mode register C
(PMRC: $025) (figure 29).

Pins R4

are multiplexed with peripheral pins

SCK

, SI

, and SO

, respectively. The peripheral

function modes of these pins are selected by bit 3 (SM1A3) of serial mode register 1A (SM1A: $005), and
bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004), as shown in figures 34 and 36.

Ports R5

are multiplexed with peripheral function pins

SCK

, SO

, respectively. The function

modes of these pins can be selected by individual pins, by setting bit 3 (SM2A3) of serial mode register 2A
(SM2A: $01B), and bits 2 and 3 (PMRA2, PMRA3) of port mode register A (PMRA: $004) (figures 35 and
36).

Ports RD

are multiplexed with peripheral function pins COMP

COMP

, respectively. The function

modes of these pins are selected by bit 3 (CER3) of the compare enable register (CER: $018).

Port RE

is multiplexed with peripheral function pin VC

ref

. While functioning as VC

ref

, do not use this pin

as an R port at the same time, otherwise, the MCU may malfunction.

Pull-Up or Pull-Down MOS Transistor Control: A program-controlled pull-up or pull-down MOS
transistor is provided for each input/output pin other than input-only pins D

and D

. The on/off status of

all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off
status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding
pin--enabling on/off control of that pin alone (table 21 and figure 38).

The on/off status of each transistor and the peripheral function mode of each pin can be set independently.

How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be
connected to V

to prevent LSI malfunctions due to noise. These pins must either be pulled up to V

their pull-up MOS transistors or by resistors of about 100 k

or pulled down to GND by their pull-down

MOS transistors.

HD404639R Series

Bit

Initial value

Read/Write

Bit name

DCD0 to DCD2

Data control register

(DCD0 to 2: $02C to $02E)
(DCR0 to C: $030 to $03C)

Bit

Initial value

Read/Write

Bit name

DCRC0

Not used

DCRC

Bit

Initial value

Read/Write

Bit name

Correspondence between ports and DCD/DCR bits

DCR03

Register Name

DCD0

DCD1

DCD2

DCR0

DCR1

DCR2

DCR3

DCR4

DCR5

DCR6

DCR7

DCR8

DCR9

DCRA

DCRB

DCRC

Bit 3

Bit 2

Bit 1

Bit 0

DCR02

DCR00

DCR01

DCR0 to DCRB

DCRB3

DCRB2

DCRB0

DCRB1

Not used

DCD03
DCD23

DCD02
DCD22

DCD01
DCD21

DCD00
DCD20

Off (high-impedance)

All Bits

CMOS Buffer On/Off Selection

Figure 28 Data Control Registers (DCD, DCR)

HD404639R Series

Bit

Initial value

Read/Write

Bit name

PMRB3

PMRB2

PMRB0

PMRB1

/INT

mode selection

INT

Port mode register B (PMRB: $024)

PMRB0

INT

mode selection

INT

PMRB2

/INT

mode selection

INT

PMRB3

/INT

mode selection

INT

Figure 30 Port Mode Register B (PMRB)

Bit

Initial value

Read/Write

Bit name

Not used

R/W

TMB20

R/W

TMB21

Timer mode register B2 (TMB2: $013)

TMB21

TMB20

/TOB mode selection

TOB

port

Toggle output

0 output

1 output

Figure 31 Timer Mode Register B2 (TMB2)

HD404639R Series

Bit

Initial value

Read/Write

Bit name

CER3

CER2

CER0

CER1

Compare enable register (CER: $018)

CER1

Analog input pin selection

COMP

CER3

Digital input mode:
RD /COMP RD /COMP
operate as an R port.

Digital/Analog selection

Analog input mode:
RD /COMP RD /COMP
operate as analog input.

CER0

CER2

Reference voltage selection

External input voltage

Internal voltage

Figure 37 Compare Enable Register (CER)

Bit

Initial value

Read/Write

Bit name

MIS3

MIS2

MIS0

MIS1

MIS2

PMOS transistor
on/off selection
for pin R4

/SO

Miscellaneous register (MIS: $00C)

Off

Refer to figure 18 in the
operation modes section.

selection.

MIS3

Pull-up and
pull-down MOS
on/off selection

Off

MIS1

MIS0

Figure 38 Miscellaneous Register (MIS)

HD404639R Series

Prescalers

The MCU has the following two prescalers, S and W.

The prescalers operating conditions are listed in table 23, and the prescalers output supply is shown in
figure 39. The timers AD input clocks except external events and the serial transmit clock except the
external clock are selected from the prescaler outputs, depending on corresponding mode registers.

Prescaler Operation

Prescaler S: 11-bit counter that inputs a system clock signal. After being reset to $000 by MCU reset,
prescaler S divides the system clock. Prescaler S keeps counting, except in watch and stop modes and at
MCU reset.

Prescaler W: Five-bit counter that inputs the X1 input clock signal (32-kHz crystal oscillation) divided by
eight. After being reset to $00 by MCU reset, prescaler W divides the input clock. Prescaler W can be
reset by software.

Table 23 Prescaler Operating Conditions

Prescaler

Input Clock

Reset Conditions

Stop Conditions

Prescaler S

System clock (in active and standby mode),
Subsystem clock (in subactive mode)

MCU reset

MCU reset,
stop mode,
watch mode

Prescaler W

32-kHz crystal oscillation

MCU reset, software

MCU reset,
stop mode

Subsystem

clock

Prescaler W

System

clock

Prescaler S

Clock

selector

Timer A

Timer B

Timer C

Timer D

Serial

interface 1

Serial

interface 2

/4 or f

Figure 39 Prescaler Output Supply

HD404639R Series

Timers

The MCU has four timer/counters (A to D).

Timer A: Free-running timer

Timer B: Multifunction timer

Timer C: Multifunction timer

Timer D: Multifunction timer

Timer A is an 8-bit free-running timer. Timers BD are 8-bit multifunction timers, whose functions are
listed in table 24. The operating modes are selected by software.

Table 24 Timer Functions

Functions

Timer A

Timer B

Timer C

Timer D

Clock source

Prescaler S

Available

Prescaler W

Available

External event

Available

Timer functions

Free-running

Available

Time-base

Available

Event counter

Available

Reload

Available

Watchdog

Available

Input capture

Available

Timer outputs

Toggle

Available

0 output

Available

1 output

Available

PWM

Available

Note:

-- means not available.

Timer A

Timer A Functions: Timer A has the following functions.

Free-running timer

Clock time-base

The block diagram of timer A is shown in figure 40.

HD404639R Series

1/4

1/2

32.768-kHz
oscillator

System
clock

Prescaler W

(PSW)

Selector

Prescaler S (PSS)

Selector

Internal data bus

Timer A interrupt

request flag

(IFTA)

Clock

Overflow

Timer

counter A

(TCA)

Timer mode

(TMA)

2 f

1/2 t

Wcyc

PER

128

512

1024

2048

÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷

÷ ÷ ÷ ÷

Figure 40 Block Diagram of Timer A

Timer A Operations:

Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA:
$008).

Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied
to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow
sets the timer A interrupt request flag (IFTA: $001, bit 2). Timer A continues to be incremented after
reset to $00, and therefore it generates regular interrupts every 256 clocks.

Clock time-base operation: Timer A is used as a clock time-base by setting bit 3 (TMA3) of timer
mode register A (TMA: $008) to 1. The prescaler W output is applied to timer A, and timer A
generates interrupts at the correct timing based on the 32.768-kHz crystal oscillation. In this case,
prescaler W and timer A can be reset to $00 by software.

Registers for Timer A Operation: Timer A operating modes are set by the following registers.

Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A's operating mode
and input clock source as shown in figure 41.

HD404639R Series

Bit

Initial value

Read/Write

Bit name

TMA3

TMA2

TMA0

TMA1

Timer mode register A (TMA: $008)

PSS

PSW

Operating mode

Timer A mode

TMA3

TMA1

TMA2

TMA0

Source
prescaler

2048t

cyc

1024t

cyc

512t

cyc

128t

cyc

32t

cyc

Input clock
frequency

32t

Wcyc

16t

Wcyc

1/2t

Wcyc

Time-base
mode

Inhibited

PSW and TCA reset

Don't
care

Notes: 1.

2.
3.

Wcyc

= 244.14

s (when a 32.768-kHz crystal oscillator is used)

Timer counter overflow output period (seconds) = input clock period (seconds) 256.
The division ratio must not be modified during time-base mode operation, otherwise
an overflow cycle error will occur.

Figure 41 Timer Mode Register A (TMA)

HD404639R Series

Timer B

Timer B Functions: Timer B has the following functions.

Free-running/reload timer

External event counter

Timer output operation (toggle, 0, and 1 outputs)

The block diagram of timer B is shown in figure 42.

System
clock

EVNB

TOB

Timer output control

Selector

Prescaler S (PSS)

Clock

Timer read register BU (TRBU)

Timer read
register BL

(TRBL)

Timer counter B

(TCB)

Timer write
register BU

(TWBU)

Timer write

(TWBL)

Timer mode

(TMB1)

Timer mode

(TMB2)

Timer B interrupt

request flag

(IFTB)

PER

Internal data bus

128

512

2048

÷ ÷ ÷ ÷ ÷ ÷

Free-running/
Reload control

Overflow

Timer output

control logic

Figure 42 Block Diagram of Timer B

HD404639R Series

Timer B Operations:

Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register B1 (TMB1: $009).

Timer B is initialized to the value set in timer write register B (TWBL: $00A, TWBU: $00B) by
software and incremented by one at each clock input. If an input clock is applied to timer B after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer B is
initialized to its initial value set in timer write register B; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.

The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0). IFTB is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.

External event counter operation: Timer B is used as an external event counter by selecting external
event input as the input clock source. In this case, pin R3

EVNB must be set to EVNB by port mode

Timer B is incremented by one at each falling edge of signals input to pin

EVNB. The other operations

are basically the same as the free-running/reload timer operation.

Timer output operation: The following three output modes can be selected for timer B by setting timer
mode register B2 (TMB2: $013).

Toggle

0 output

1 output

By selecting the timer output mode, pin R3

/TOB is set to TOB. The output from TOB is reset low by

MCU reset.

Toggle output: When toggle output mode is selected, the output level is inverted if a clock is input

after timer B has reached $FF. By using this function and reload timer function, clock signals can
be output at a required frequency for the buzzer. The output waveform is shown in figure 43.

0 output: When 0 output mode is selected, the output level is pulled low if a clock is input after

timer B has reached $FF. Note that this function must be used only when the output level is high.

1 output: When 1 output mode is selected, the output level is set high if a clock is input after timer

B has reached $FF. Note that this function must be used only when the output level is low.

HD404639R Series

T (N + 1)

T 256

T (256 N)

TMC13 = 0

The waveform is always fixed low when N = $FF.
T:
N:

TMC13 = 1

Input clock period to counter (figures 52 and 59)
The value of the timer write register

Note:

TMD13 = 0

TMD13 = 1

256 clock cycles

Free-running timer

Toggle output waveform (timers B, C, and D)

PWM output waveform (timers C and D)

(256 N) clock cycles (256 N) clock cycles

Reload timer

Figure 43 Timer Output Waveform

Registers for Timer B Operation: By using the following registers, timer B operation modes are selected
and the timer B count is read and written.

Timer mode register B1 (TMB1: $009)

Timer mode register B2 (TMB2: $013)

Timer write register B (TWBL: $00A, TWBU: $00B)

Timer read register B (TRBL: $00A, TRBU: $00B)

Port mode register C (PMRC: $025)

Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the free-
running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 44.
It is reset to $0 by MCU reset.

HD404639R Series

Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register B1 write instruction. Setting timer B's initialization by writing to timer
write register B (TWBL: $00A, TWBU: $00B) must be done after a mode change becomes valid.

Bit

Initial value

Read/Write

Bit name

TMB13

TMB12

TMB10

TMB11

Timer mode register B1 (TMB1: $009)

2048t

cyc

512t

cyc

128t

cyc

32t

cyc

TMB12

TMB10

TMB11

Input clock period and input
clock source

EVNB

(external event input)

TMB13

Free-running/reload
timer selection

Free-running timer

Reload timer

Figure 44 Timer Mode Register B1 (TMB1)

Timer mode register B2 (TMB2: $013): Two-bit read/write register that selects the timer B output
mode as shown in figure 45. It is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

Not used

R/W

TMB20

R/W

TMB21

Timer mode register B2 (TMB2: $013)

TMB21

TMB20

/TOB mode selection

TOB

port

Toggle output

0 output

1 output

Figure 45 Timer Mode Register B2 (TMB2)

HD404639R Series

Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of the lower digit
(TWBL) and the upper digit (TWBU) as shown in figures 46 and 47. The lower digit is reset to $0 by
MCU reset, but the upper digit value is invalid.

Timer B is initialized by writing to timer write register B. In this case, the lower digit (TWBL) must be
written to first, but writing only to the lower digit does not change the timer B value. Timer B is
initialized to the value in timer write register B at the same time the upper digit (TWBU) is written to.
When timer write register B is written to again and if the lower digit value needs no change, writing
only to the upper digit initializes timer B.

Bit

Initial value

Read/Write

Bit name

TWBL3

TWBL2

TWBL0

TWBL1

Timer write register B (lower digit) (TWBL: $00A)

Figure 46 Timer Write Register B Lower Digit (TWBL)

Bit

Initial value

Read/Write

Bit name

Undefined

TWBU3

Undefined

TWBU2

Undefined

TWBU0

Undefined

TWBU1

Timer write register B (upper digit) (TWBU: $00B)

Figure 47 Timer Write Register B Upper Digit (TWBU)

Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of the lower digit
(TRBL) and the upper digit (TRBU) that holds the count of the timer B upper digit (figures 48 and 49).

The upper digit (TRBU) must be read first. At this time, the count of the timer B upper digit is
obtained, and the count of the timer B lower digit is latched to the lower digit (TRBL). After this, by
reading TRBL, the count of timer B when TRBU is read can be obtained.

Bit

Initial value

Read/Write

Bit name

Undefined

TRBL3

Undefined

TRBL2

Undefined

TRBL0

Undefined

TRBL1

Timer read register B (lower digit) (TRBL: $00A)

Figure 48 Timer Read Register B Lower Digit (TRBL)

HD404639R Series

Bit

Initial value

Read/Write

Bit name

Undefined

TRBU3

Undefined

TRBU2

Undefined

TRBU0

Undefined

TRBU1

Timer read register B (upper digit) (TRBU: $00B)

Figure 49 Timer Read Register B Upper Digit (TRBU)

Port mode register C (PMRC: $025): Write-only register that selects R3

EVNB pin function as shown

in figure 50. It is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

PMRC3

PMRC2

PMRC0

PMRC1

/EVND mode selection

EVND

Port mode register C (PMRC: $025)

PMRC0

EVNB

mode selection

EVNB

PMRC3

INT

mode selection

INT

PMRC2

STOPC

mode selection

STOPC

Figure 50 Port Mode Register C (PMRC)

HD404639R Series

Timer C

Timer C Functions: Timer C has the following functions.

Free-running/reload timer

Watchdog timer

Timer output operation (toggle, 0, 1, and PWM outputs)

The block diagram of timer C is shown in figure 51.

Watchdog on

flag (WDON)

System
reset signal

Timer C interrupt

request flag

(IFTC)

Timer output

control logic

Timer read register CU (TRCU)

Timer output
control

Timer read
register CL

(TRCL)

Clock

Timer counter C

(TCC)

Selector

System
clock

Prescaler S (PSS)

Overflow

Internal data bus

Timer write

(TWCU)

Timer write
register CL

(TWCL)

Timer mode

(TMC1)

Timer mode

(TMC2)

Free-running
/Reload control

Watchdog timer

control logic

TOC

PER

128

512

1024

2048

Figure 51 Block Diagram of Timer C

HD404639R Series

Timer C Operations:

Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register C1 (TMC1: $00D).

Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by
software and incremented by one at each clock input. If an input clock is applied to timer C after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is
initialized to its initial value set in timer write register C; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.

The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.

Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program
routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of
control and an overflow is generated, the MCU is reset. Program run can be controlled by initializing
timer C by software before it reaches $FF.

Timer output operation: The following four output modes can be selected for timer C by setting timer
mode register C2 (TMC2: $014).

Toggle

0 output

1 output

PWM output

By selecting the timer output mode, pin R3

/TOC is set to TOC. The output from TOC is reset low by

MCU reset.

Toggle output: The operation is basically the same as that of timer-B's toggle output.

0 output: The operation is basically the same as that of timer-B's 0 output.

1 output: The operation is basically the same as that of timer-B's 1 output.

PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output

function. The output waveform differs depending on the contents of timer mode register C1
(TMC1: $00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is
shown in figure 43.

Registers for Timer C Operation: By using the following registers, timer C operation modes are selected
and the timer C count is read and written.

Timer mode register C1 (TMC1: $00D)

Timer mode register C2 (TMC2: $014)

Timer write register C (TWCL: $00E, TWCU: $00F)

Timer read register C (TRCL: $00E, TRCU: $00F)

HD404639R Series

Timer mode register C1 (TMC1: $00D): Four-bit write-only register that selects the free-
running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 52.
It is reset to $0 by MCU reset.

Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register C1 write instruction. Setting timer C's initialization by writing to timer
write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid.

Bit

Initial value

Read/Write

Bit name

TMC13

TMC12

TMC10

TMC11

Timer mode register C1 (TMC1: $00D)

2048t

cyc

1024t

cyc

512t

cyc

128t

cyc

32t

cyc

TMC12

TMC10

TMC11

TMC13

Free-running/reload timer selection

Free-running timer

Reload timer

Input clock period

Figure 52 Timer Mode Register C1 (TMC1)

Timer mode register C2 (TMC2: $014): Three-bit read/write register that selects the timer C output
mode as shown in figure 53. It is reset to $0 by MCU reset.

HD404639R Series

Bit

Initial value

Read/Write

Bit name

Not used

R/W

TMC22

R/W

TMC20

R/W

TMC21

Timer mode register C2 (TMC2: $014)

TMC22

TMC21

/TOC mode selection

TOC

port

Toggle output

0 output

1 output

Inhibited

PWM output

TMC20

Figure 53 Timer Mode Register C2 (TMC2)

Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of a lower digit
(TWCL) and an upper digit (TWCU) as shown in figures 54 and 55. The operation of timer write
register C is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B).

Bit

Initial value

Read/Write

Bit name

TWCL3

TWCL2

TWCL0

TWCL1

Timer write register C (lower digit) (TWCL: $00E)

Figure 54 Timer Write Register C Lower Digit (TWCL)

Bit

Initial value

Read/Write

Bit name

Undefined

TWCU3

Undefined

TWCU2

Undefined

TWCU0

Undefined

TWCU1

Timer write register C (upper digit) (TWCU: $00F)

Figure 55 Timer Write Register C Upper Digit (TWCU)

HD404639R Series

Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of a lower digit
(TRCL) and an upper digit (TRCU) that holds the count of the timer C upper digit as shown in figures
56 and 57. The operation of timer read register C is basically the same as that of timer read register B
(TRBL: $00A, TRBU: $00B).

Bit

Initial value

Read/Write

Bit name

Undefined

TRCL3

Undefined

TRCL2

Undefined

TRCL0

Undefined

TRCL1

Timer read register C (lower digit) (TRCL: $00E)

Figure 56 Timer Read Register C Lower Digit (TRCL)

Bit

Initial value

Read/Write

Bit name

Undefined

TRCU3

Undefined

TRCU2

Undefined

TRCU0

Undefined

TRCU1

Timer read register C (upper digit) (TRCU: $00F)

Figure 57 Timer Read Register C Upper Digit (TRCU)

Timer D

Timer D Functions: Timer D has the following functions.

Free-running/reload timer

External event counter

Timer output operation (toggle, 0, 1, and PWM outputs)

Input capture timer

The block diagram for each operation mode of timer D is shown in figures 58 (A) and (B).

HD404639R Series

Selector

128

512

2048

PER

Input capture

status flag (ICSF)

Input capture

error flag (ICEF)

Timer D interrupt

request flag (IFTD)

Error

control

logic

Edge

detection

logic

Timer read

(TRDU)

Timer read
register DL

(TRDL)

Read signal

Clock

Timer counter D

(TCD)

Overflow

System
clock

Edge detection control

Prescaler S (PSS)

Input capture

timer control

Timer mode

(TMD1)

Timer mode

(TMD2)

Edge detection

selection register

2 (ESR2)

EVND

Internal data bus

Figure 58 (B) Block Diagram of Timer D (Input Capture Timer)

Timer D Operations:

Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register D1 (TMD1: $010).

HD404639R Series

Timer D is initialized to the value set in timer write register D (TWDL: $011, TWDU: $012) by
software and incremented by one at each clock input. If an input clock is applied to timer D after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer D is
initialized to its initial value set in timer write register D; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.

The overflow sets the timer D interrupt request flag (IFTD: $003, bit 0). IFTD is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.

External event counter operation: Timer D is used as an external event counter by selecting the
external event input as an input clock source. In this case, pin R4

/EVND must be set to EVND by port

mode register C (PMRC: $025).

Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
external event detection edge by detection edge select register 2 (ESR2: $027). When both rising and
falling edges detection is selected, the time between the falling edge and rising edge of input signals
must be 2t

cyc

or longer.

Timer D is incremented by one at each detection edge selected by detection edge select register 2
(ESR2: $027). The other operations are basi cally the same as the free-running/reload timer operation.

Timer output operation: The following four output modes can be selected for timer D by setting timer
mode register D2 (TMD2: $015).

Toggle

0 output

1 output

PWM output

By selecting the timer output mode, pin R3

/TOD is set to TOD. The output from TOD is reset low by

MCU reset.

Toggle output: The operation is basically the same as that of timer-B's toggle output.

0 output: The operation is basically the same as that of timer-B's 0 output.

1 output: The operation is basically the same as that of timer-B's 1 output.

PWM output: The operation is basically the same as that of timer-C's PWM output.

Input capture timer operation: The input capture timer counts the clock cycles between trigger edges
input to pin EVND.

Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
trigger input edge by detection edge select register 2 (ESR2: $027).

When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL:
$011, TRDU: $012), and the timer D interrupt request flag (IFTD: $003, bit 0) and the input capture
status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While
ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input
capture error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing
0.

By selecting the input capture operation, pin R3

/TOD is set to R3

and timer D is reset to $00.

HD404639R Series

Registers for Timer D Operation: By using the following registers, timer D operation modes are selected
and the timer D count is read and written.

Timer mode register D1 (TMD1: $010)

Timer mode register D2 (TMD2: $015)

Timer write register D (TWDL: $011, TWDU: $012)

Timer read register D (TRDL: $011, TRDU: $012)

Port mode register C (PMRC: $025)

Detection edge select register 2 (ESR2: $027)

Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the free-
running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 59.
It is reset to $0 by MCU reset.

Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register D1 (TMD1: $010) write instruction. Setting timer D's initialization by
writing to timer write register D (TWDL: $011, TWDU: $012) must be done after a mode change
becomes valid.

When selecting the input capture timer operation, select the internal clock as the input clock source.

Bit

Initial value

Read/Write

Bit name

TMD13

TMD12

TMD10

TMD11

Timer mode register D1 (TMD1: $010)

2048t

cyc

512t

cyc

128t

cyc

32t

cyc

TMD12

TMD10

TMD11

Input clock period and

input clock source

/EVND (External event input)

TMD13

Free-running/reload timer selection

Free-running timer

Reload timer

Figure 59 Timer Mode Register D1 (TMD1)

HD404639R Series

Timer mode register D2 (TMD2: $015): Four-bit read/write register that selects the timer D output
mode and input capture operation as shown in figure 60. It is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

R/W

TMD23

R/W

TMD22

R/W

TMD20

R/W

TMD21

Timer mode register D2 (TMD2: $015)

TMD22

TMD20

TMD21

/TOD mode selection

TOD

port

Toggle output

0 output

1 output

Inhibited

PWM output

Input capture (R3

port)

TMD23

Don't care

Figure 60 Timer Mode Register D2 (TMD2)

Timer write register D (TWDL: $011, TWDU: $012): Write-only register consisting of a lower digit
(TWDL) and an upper digit (TWDU) as shown in figures 61 and 62. The operation of timer write
register D is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B).

Bit

Initial value

Read/Write

Bit name

TWDL3

TWDL2

TWDL0

TWDL1

Timer write register D (lower digit) (TWDL: $011)

Figure 61 Timer Write Register D Lower Digit (TWDL)

HD404639R Series

Bit

Initial value

Read/Write

Bit name

Undefined

TWDU3

Undefined

TWDU2

Undefined

TWDU0

Undefined

TWDU1

Timer write register D (upper digit) (TWDU: $012)

Figure 62 Timer Write Register D Upper Digit (TWDU)

Timer read register D (TRDL: $011, TRDU: $012): Read-only register consisting of a lower digit
(TRDL) and an upper digit (TRDU) as shown in figures 63 and 64. The operation of timer read register
D is basically the same as that of timer read register B (TRBL: $00A, TRBU: $00B).

When the input capture timer operation is selected and if the count of timer D is read after a trigger is
input, either the lower or upper digit can be read first.

Bit

Initial value

Read/Write

Bit name

Undefined

TRDL3

Undefined

TRDL2

Undefined

TRDL0

Undefined

TRDL1

Timer read register D (lower digit) (TRDL: $011)

Figure 63 Timer Read Register D Lower Digit (TRDL)

Bit

Initial value

Read/Write

Bit name

Undefined

TRDU3

Undefined

TRDU2

Undefined

TRDU0

Timer read register D (upper digit) (TRDU: $012)

Undefined

TRDU1

Figure 64 Timer Read Register D Upper Digit (TRDU)

Port mode register C (PMRC: $025): Write-only register that selects R4

/EVND pin function as shown

in figure 50. It is reset to $0 by MCU reset.

Detection edge select register 2 (ESR2: $027): Write-only register that selects the detection edge of
signals input to pin EVND as shown in figure 65. It is reset to $0 by MCU reset.

HD404639R Series

Bit

Initial value

Read/Write

Bit name

ESR23

ESR22

ESR21

Detection edge selection register 2 (ESR2: $027)

ESR23

ESR22

EVND detection edge

No detection

Falling-edge detection

Rising-edge detection

Double-edge detection

Note: Both falling and rising edges are detected.

ESR20

ESR21

ESR20

INT detection edge

No detection

Falling-edge detection

Rising-edge detection

Double-edge detection

Figure 65 Detection Edge Select Register 2 (ESR2)

Notes on Use

When using the timer output as PWM output, note the following point. From the update of the timer write
register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty
settings, as shown in table 25. The PWM output should therefore not be used until after the overflow
interrupt following the update of the timer write register. After the overflow, the PWM output will have the
set period and duty cycle.

HD404639R Series

Serial Communications Interface

The MCU has two channels of serial interface. The transfer and receive start instructions differ according to
the serial interface channel, but other functions are the same. The serial interface serially transfers or
receives 8-bit data, and includes the following features.

Multiple transmit clock sources

External clock

Internal prescaler output clock

System clock

Output level control in idle states

Five registers, an octal counter, and a multiplexer are also configured for serial interfaces 1 and 2 as
follows.

Serial interface 1

Serial data register 1 (SR1L: $006, SR1U: $007)

Serial mode register 1A (SM1A: $005)

Serial mode register 1B (SM1B: $028)

Port mode register A (PMRA: $004)

Miscellaneous register (MIS: $00C)

Octal counter (OC1)

Selector

Serial interface 2

Serial data register 2 (SR2L: $01D, SR2U: $01E)

Serial mode register 2A (SM2A: $01B)

Serial mode register 2B (SM2B: $01C)

Port mode register A (PMRA: $004)

Octal counter (OC2)

Selector

The block diagram of the serial interface is shown in figure 66.

HD404639R Series

Selector

Prescaler S (PSS)

128

512

2048

Selector

I/O control

logic

Idle control

logic

Octal counter

(OC1, OC2)

Serial interrupt

request flag

(IFS1, IFS2)

Clock

Serial data

SR2L/U)

Serial mode register

1A, 2A (SM1A,

SM2A)

Serial mode register

1B, 2B (SM1B,

SM2B)

Transfer
control

SO , SO

SCK

SI , SI

System
clock

Internal data bus

PER

1/2

Figure 66 Block Diagram of Serial Interface Serial Interface Operation

Serial Interface Operation

Selecting and Changing the Operating Mode: Tables 26 (A) and 26 (B) list the serial interfaces'
operating modes. To select an operating mode, use one of these combinations of port mode register A
(PMRA: $004), serial mode register 1A (SM1A: $005), and serial mode register 2A (SM2A: $01B)
settings; to change the operating mode of serial interface 1, always initialize the serial interface internally
by writing data to serial mode register 1A; and to change the operating mode of serial interface 2, always
initialize the serial interface internally by writing data to serial mode register 2A. Note that serial interface

HD404639R Series

1 is initialized by writing data to serial mode register 1A, and serial interface 2 is initialized by writing data
to serial mode register 2A. Refer to the following section Registers for Serial Interface for details.

Pin Setting: The R4

SCK

pin is controlled by writing data to serial mode register 1A (SM1A: $005). The

SCK

pin is controlled by writing data to serial mode register 2A (SM2A: $01B). Pins R4

/SI

/SO

, R5

/SI

, and R5

/SO

are controlled by writing data to port mode register A (PMRA: $004). Refer

to the following section Registers for Serial Interface for details.

Transmit Clock Source Setting: The transmit clock source of serial interface 1 is set by writing data to
serial mode register 1A (SM1A: $005) and serial mode register 1B (SM1B: $028). The transmit clock
source of serial interface 2 is set by writing data to serial mode register 2A (SM2A: $01B) and serial mode
register 2B (SM2B: $01C). Refer to the following section Registers for Serial Interface for details.

Data Setting: Transmit data of serial interface 1 is set by writing data to serial data register 1 (SR1L: $006,
SR1U: $007). Transmit data of serial interface 2 is set by writing data to serial data register 2 (SR2L: $01D,
SR2U: $01E). Receive data of serial interface 1 is obtained by reading the contents of serial data register 1.
Receive data of serial interface 2 is obtained by reading the contents of serial data register 2. The serial data
is shifted by each serial interface transmit clock and is input from or output to an external system.

The output level of the SO

and SO

pins is invalid until the first data of each serial interface is output after

MCU reset, or until the output level control in idle states is performed.

Transfer Control: Serial interface 1 is activated by the STS instruction. Serial interface 2 is activated by a
dummy read of serial mode register 2A (SM2A: $01B), which will be referred to as SM2A read. The octal
counter is reset to 000 by the STS instruction (serial interface 2 is SM2A read), and it increments at the
rising edge of the transmit clock for each serial interface. When the eighth transmit clock signal is input or
when serial transmission/reception is discontinued, the octal counter is reset to 000, the serial interface 1
interrupt request flag (IFS1: $003, bit 2) for serial interface 1 and serial interface 2 interrupt request flag
(IFS2: $023, bit 2) for serial interface 2 are set, and the transfer stops.

When the prescaler output is selected as the transmit clock of serial interface 1, the transmit clock
frequency is selected as 4t

cyc

to 8192t

cyc

by setting bits 0 to 2 (SM1A0SM1A2) of serial mode register 1A

(SM1A: $005) and bit 0 (SM1B0) of serial mode register 1B (SM1B: $028) as listed in table 27. When the
prescaler output is selected as the transmit clock of serial interface 2, the transmit clock frequency is
selected as 4t

cyc

to 8192t

cyc

by setting bits 0 to 2 (SM2A0SM2A2) of serial mode register 2A (SM2A:

$01B) and bit 0 (SM2B0) of serial mode register 2B (SM2B: $01C).

Note: To start serial interface 2, simply read serial mode register 2A by using the instruction that compares
serial mode register 2A with the accumulator.

Serial mode register 2A is a read-only register, so $0 can be read.

HD404639R Series

Table 26 (A) Serial Interface 1 Operating Modes

SM1A

PMRA

Bit 3

Bit 1

Bit 0

Operating Mode

Continuous clock output mode

Transmit mode

Receive mode

Transmit/receive mode

Table 26 (B) Serial Interface 2 Operating Modes

SM2A

PMRA

Bit 3

Bit 1

Bit 0

Operating Mode

Continuous clock output mode

Transmit mode

Receive mode

Transmit/receive mode

Table 27 Transmit Clock (Prescaler Output)

SM1B/
SM2B

SM1A/ SM2A

Bit 0

Bit 2

Bit 1

Bit 0

Prescaler Division Ratio

Transmit Clock Frequency

2048

4096t

cyc

512

1024t

cyc

128

256t

cyc

64t

cyc

16t

cyc

4096

8192t

cyc

1024

2048t

cyc

256

512t

cyc

128t

cyc

32t

cyc

HD404639R Series

Operating States: Serial interface 1 has the following operating states; transitions between them are shown
in figure 67.

STS wait state (serial interface 2 is in SM2A read wait state)

Transmit clock wait state

Transfer state

Continuous clock output state (only in internal clock mode)

System reset

SM1A write

STS instruction

Transmit clock

Eight transmit clock cycles

STS instruction

(IFS1 1)

SM1A write
(IFS1 1)

STS instruction wait state

(with octal counter = 000,

transmit clock disabled)

Transmit clock wait state

(octal counter = 000)

Transfer state

(octal counter 000)

System reset

SM1A write

Transmit clock

STS instruction

STS instruction
(IFS1 1)

Eight transmit clock cycles
STS instruction
(IFS1 1)

Transmit clock

continuous output state

(PMRA 0, 1 = 00)

Transmit clock wait state

(octal counter = 000)

STS instruction wait state

(with octal counter = 000,

transmit clock disabled)

Transfer state

(octal counter 000)

Note:

Internal Clock Mode

External Clock Mode

For serial interface 2, this is accomplished by reading the SM2A register.
Circled numbers are referred to in the text.

Transmit clock

Figure 67 Serial Interface State Transition Diagram

The operation state of serial interface 2 is the same as serial interface 1 except that the STS instruction of
serial interface 1 changes to SM2A read. The following shows the operation state of serial interface 1.

STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 67). In STS
wait state, serial interface 1 is initialized and the transmit clock is ignored. If the STS instruction is then
executed (01, 11), serial interface 1 enters transmit clock wait state.

HD404639R Series

Transmit clock wait state: Transmit clock wait state is the period between the STS execution and the
falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12)
increments the octal counter, shifts serial data register 1 (SR1L: $006, SR1U: $007), and puts the serial
interface in transfer state. However, note that if continuous clock output mode is selected in internal
clock mode, the serial interface does not enter transfer state but enters continuous clock output state
(17).

The serial interface enters STS wait state by writing data to serial mode register 1A (SM1A: $005) (04,
14) in transmit clock wait state.

Transfer state: Transfer state is the period between the falling edge of the first clock and the rising edge
of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction
sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is
executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait
state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In
internal clock mode, the transmit clock stops after outputting eight clocks.

In transfer state, writing data to serial mode register 1A (SM1A: $005) (06, 16) initializes serial
interface 1, and STS wait state is entered.

If the state changes from transfer to another state, the serial 1 interrupt request flag (IFS1: $003, bit 2) is
set by the octal counter that is reset to 000.

Continuous clock output state (only in internal clock mode): Continuous clock output state is entered
only in internal clock mode. In this state, the serial interface does not transmit/receive data but only
outputs the transmit clock from the

SCK

pin.

When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock
wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state.
If serial mode register 1A (SM1A: $005) is written to in continuous clock output mode (18), STS wait
state is entered.

Output Level Control in Idle States: When serial interface 1 is in STS instruction wait state and when
serial interface 2 is in SM2A read wait state and transmit clock state, the output of each serial output pin,
SO

and SO

can be controlled by setting bit 1 (SM1B1) of serial mode register 1B (SM1B: $028) to 0 or

1, or bit 1 (SM2B1) of serial mode register 2B (SM2B: $01C) to 0 or 1. The output level control example
of serial interface 1 is shown in figure 68. Note that the output level cannot be controlled in transfer state.

HD404639R Series

State

MCU reset

PMRA write

SM1A write

SM1B write

SR1L, SR1U
write

STS instruction

SCK

pin (input)

IFS1

STS wait state

Transmit clock
wait state

Transfer state

Transmit clock
wait state

STS wait state

Port selection

External clock selection

Output level control in

idle states

Dummy write for
state transition

Output level control in

idle states

Data write for transmission

LSB

MSB

Flag reset at transfer completion

External clock mode

State

MCU reset

PMRA write

SM1A write

SM1B write

SR1L, SR1U
write

STS instruction

SCK

pin (output)

IFS1

STS wait state

Transfer state

Transmit clock
wait state

STS wait state

Port selection

Internal clock selection

Output level control in

idle states

Data write for transmission

Output level control in

idle states

LSB

MSB

Flag reset at transfer completion

Internal clock mode

Undefined

Figure 68 Example of Serial Interface 1 Operation Sequence

HD404639R Series

Transmit Clock Error Detection (In External Clock Mode): Each serial interface will malfunction if a
spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit
clock error of this type can be detected as shown in figure 69.

If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse
by noise, the octal counter reaches 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set, and
transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is
entered. After the transfer is completed and IFS1 is reset, writing to serial mode register 1A (SM1A: $005)
changes the state from transfer to STS wait. At this time serial interface 1 is in the transfer state, and the
serial 1 interrupt request flag is set again, and therefore the error can be detected. The same applies to serial
interface 2.

HD404639R Series

Notes on Use:

Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit
clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode
register 1A (SM1A: $005) and serial mode register 2A (SM2A: $01B) again.

Serial 1 interrupt request flag (IFS1: $003, bit 2) and serial 2 interrupt request flag (IFS2: $023, bit 2)
set: For serial interface 1, if the state is changed from transfer state to another by writing to serial mode
register 1A (SM1A: $005) or executing the STS instruction during the first low pulse of the transmit
clock, the serial 1 interrupt request flag (IFS1: $003, bit 2) is not set. In the same way for serial interface
2, if the state is changed from transfer state to another by writing to serial mode register 2A (SM2A:
$01B) or by executing the STS instruction during the first low pulse of the transmit clock, the serial 2
interrupt request flag is not set. To set the serial 1 interrupt request flag, a serial mode register 1A write
or STS instruction execution must be programmed to be executed after confirming that the

SCK

pin is

at 1, that is, after executing the input instruction to port R4. To set the serial 2 interrupt request flag, a
serial mode register 2A write or SM2A instruction execution must be programmed to be executed after
confirming that the

SCK

pin is at 1, that is, after executing the input instruction to port R5.

Registers for Serial Interface

When serial interface operation is selected, serial data is read and written by the following registers.

For serial interface 1

Serial mode register 1A (SM1A: $005)

Serial mode register 1B (SM1B: $028)

Serial data register 1 (SR1L: $006, SR1U: $007)

Port mode register A (PMRA: $004)

Miscellaneous register (MIS: $00C)

For serial interface 2

Serial mode register 2A (SM2A: $01B)

Serial mode register 2B (SM2B: $01C)

Serial data register 2 (SR2L: $01D, SR2U: $01E)

Port mode register A (PMRA: $004)

Serial Mode Register 1A (SM1A: $005): This register has the following functions (figure 70).

SCK

pin function selection

Serial interface 1 transmit clock selection

Serial interface 1 prescaler division ratio selection

Serial interface 1 initialization

Serial mode register 1A is a 4-bit write-only register. It is reset to $0 by MCU reset.

HD404639R Series

A write signal input to serial mode register 1A discontinues the input of the transmit clock to serial data
register 1 (SR1L: $006, SR1U: $007) and the octal counter, and the octal counter is reset to 000. Therefore,
if a write is performed during data transfer, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set.

Written data is valid from the second instruction execution cycle after the write operation, so the STS
instruction must be executed at least two cycles after that.

Bit

Initial value

Read/Write

Bit name

SM1A3

SM1A2

SM1A0

SM1A1

Serial mode register 1A (SM1A: $005)

SM1A2

SM1A0

SM1A1

SM1A3

SCK

mode selection

SCK

Output

Input

Clock source

Prescaler

System clock

External clock

Prescaler
division ratio

Refer to
table 27

Figure 70 Serial Mode Register 1A (SM1A)

Serial Mode Register 1B (SM1B: $028): This register has the following functions (figure 71).

Serial interface 1 prescaler division ratio selection

Serial interface 1 output level control in idle states

Serial mode register 1B (SM1B: $028) is a 2-bit write-only register. It cannot be written during data
transfer.

By setting bit 0 (SM1B0) of this register, the serial interface 1 prescaler division ratio is selected. Only bit 0
(SM1B0) can be reset to 0 by MCU reset. By setting bit 1 (SM1B1), the output level of the SO

pin is

controlled in idle states of serial interface 1. The output level changes at the same time that SM1B1 is
written to.

HD404639R Series

Bit

Initial value

Read/Write

Bit name

Not used

SM1B0

Undefined

SM1B1

SM1B0

Transmit clock division ratio

Prescaler output divided by 2

Prescaler output divided by 4

Serial mode register 1B (SM1B: $028)

SM1B1

Output level control in idle states

Low level

High level

Figure 71 Serial Mode Register 1B (SM1B)

Serial Data Register 1 (SR1L: $006, SR1U: $007): This register has the following functions (figures 72
and 73)

Serial interface 1 transmission data write and shift

Serial interface 1 receive data shift and read

Writing data in this register is output from the SO

pin, LSB first, synchronously with the falling edge of

the transmit clock; data is input, LSB first, through the SI

pin at the rising edge of the transmit clock.

Input/output timing is shown in figure 74.

Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the
accuracy of the resultant data cannot be guaranteed.

Bit

Initial value

Read/Write

Bit name

Undefined

R/W

SR13

Undefined

R/W

SR12

Undefined

R/W

SR10

Undefined

R/W

SR11

Serial data register 1 (lower digit) (SR1L: $006)

Figure 72 Serial Data Register 1 (SR1L)

Bit

Initial value

Read/Write

Bit name

Undefined

R/W

SR17

Undefined

R/W

SR16

Undefined

R/W

SR14

Undefined

R/W

SR15

Serial data register 1 (upper digit) (SR1U: $007)

Figure 73 Serial Data Register 1 (SR1U)

HD404639R Series

Port Mode Register A (PMRA: $004): This register has the following functions (figure 75).

/SI

pin function selection

/SO

pin function selection

/SI

pin function selection

/SO

pin function selection

Port mode register A (PMRA: $004) is a 4-bit write-only register, and is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

PMRA3

PMRA2

PMRA0

PMRA1

Port mode register A (PMRA: $004)

PMRA2

/SO

mode selection

PMRA3

/SI

mode selection

PMRA0

/SO

mode selection

PMRA1

/SI

mode selection

Figure 75 Port Mode Register A (PMRA)

Miscellaneous Register (MIS: $00C): This register has the following functions (figure 76).

/SO

pin PMOS control

Miscellaneous register (MIS: $00C) is a 4-bit write-only register and is reset to $0 by MCU reset.

HD404639R Series

7.8125 ms

31.25 ms

Not used

MIS2

/SO

PMOS on/off selection

Off

Bit

Initial value

Read/Write

Bit name

MIS3

MIS2

MIS0

MIS1

Miscellaneous register (MIS: $00C)

MIS1

MIS0

0.12207 ms

0.24414 ms

MIS3

Pull-up MOS on/off selection

Off

Note:

This value is valid only for direct transfer operation.

Figure 76 Miscellaneous Register (MIS)

Serial Mode Register 2A (SM2A: $01B): This register has the following functions (figure 77).

SCK

pin function selection

Serial interface 2 transmit clock selection

Serial interface 2 prescaler division ratio selection

Serial interface 2 initialization

Serial mode register 2A (SM2A: $01B) is a 4-bit write-only register. It is reset to $0 by MCU reset.

A write signal input to serial mode register 2A discontinues the input of the transmit clock to serial data
register 2 (SR2L: $01D, SR2U: $01E) and the octal counter, and the octal counter is reset to 000.
Therefore, if a write is performed during data transfer, the serial 2 interrupt request flag (IFS2: $023, bit 2)
is set.

Written data is valid from the second instruction execution cycle after the write operation, so the SM2A
read instruction must be executed at least two cycles after that.

HD404639R Series

Bit

Initial value

Read/Write

Bit name

SM2A3

SM2A2

SM2A0

SM2A1

Serial mode register 2A (SM2A: $01B)

SM2A2

SM2A0

SM2A1

SM2A3

SCK

mode selection

SCK

Output

Input

Clock source

Prescaler

System clock

External clock

Prescaler
division ratio

Refer to
table 27

Figure 77 Serial Mode Register 2A (SM2A)

Serial Mode Register 2B (SM2B: $01C): This register has the following functions (figure 78).

Serial interface 2 prescaler division ratio selection

Serial interface 2 output level control in idle states

/SO

pin PMOS control

Serial mode register 2B is a 3-bit write-only register. It cannot be written during serial interface 2 data
transfer. Bit 0 (SM2B0) and bit 2 (SM2B2) are reset to $0 by MCU reset.

By setting bit 0 (SM2B0) of this register, the serial interface 2 prescaler division ratio of serial interface 2 is
selected. By resetting bit 1 (SM2B1), the output level of the SO

pin is controlled in idle states of serial

interface 2. The output level changes at the same time that SM2B1 is written to.

HD404639R Series

Bit

Initial value

Read/Write

Bit name

Not used

SM2B2

SM2B0

Undefined

SM2B1

SM2B2

R5 /SO PMOS

Serial mode register 2B (SM2B: $01C)

SM2B1

Output level control in idle states

Low level

High level

SM2B0

Transmit clock division ratio

Prescaler output divided by 2

Prescaler output divided by 4

3 2

Off

Figure 78 Serial Mode Register 2B (SM2B)

Serial Data Register 2 (SR2L: $01D, SR2U: $01E): This register has the following functions (figures 79
and 80).

Serial interface 2 transmission data write and shift

Serial interface 2 receive data shift and read

Writing data in this register is output from the SO

pin, LSB first, synchronously with the falling edge of

the transmit clock; data is input, LSB first, through the SI

pin at the rising edge of the transmit clock.

Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the
accuracy of the resultant data cannot be guaranteed.

Bit

Initial value

Read/Write

Bit name

Undefined

R/W

SR23

Undefined

R/W

SR22

Undefined

R/W

SR20

Undefined

R/W

SR21

Serial data register 2 (lower digit) (SR2L: $01D)

Figure 79 Serial Data Register 2 (SR2L)

HD404639R Series

DTMF Generator Circuit

The MCU provides a dual-tone multifrequency (DTMF) generator circuit. The DTMF signal consists of
two sine waves to access the switching system.

Figure 81 shows the DTMF keypad and frequencies. Each key enables tones to be generated corresponding
to each frequency. Figure 82 shows a block diagram of the DTMF circuit.

The OSC clock (400 kHz, 800 kHz, 2 MHz, 3.58 MHz, 4 MHz, 7.16 MHz or 8 MHz) is changed into six
clock signals through the division circuit (1/2, 1/5, 1/9, 1/10, 1/18 and 1/20). The DTMF circuit uses one
of the six clock signals, which is selected by system clock select register 1 (SSR1: $029) and system clock
select register 2 (SSR2: $02A) depending on the OSC clock frequency. The DTMF circuit has
transformed programmable dividers, sine wave counters, and control registers.

The DTMF generator circuit is controlled by the following three registers.

R1 (697 Hz)

R2 (770 Hz)

R3 (852 Hz)

R4 (941 Hz)

C1 (1,209 Hz)

C2 (1,336 Hz)

C3 (1,477 Hz)

C4 (1,633 Hz)

Figure 81 DTMF Keypad and Frequencies

HD404639R Series

Sine wave

counter D/A

Transforma-

tion program

divider

Feedback

Sine wave

counter D/A

Transforma-

tion program

divider

Feedback

TONER

ref

TONEC

TONER output control

TONEC output control

OSC

Tone generator

control register

(TGC)

System clock

selection register 1

(SSR1)

System clock

selection register 2

(SSR2)

400 kHz

Selector

Tone generator

mode register

(TGM)

Notes: 1.

2.
3.

System clock selection register 2 (SSR2) is used to specify the divide-by-9 or divide-by-18 operation
when a 3.58-MHz or 7.16 MHz system clock oscillator is used.
Applies to HD40A4638R, HD40A4639R and HD407A4639R.
This is 397.8 kHz when f

OSC

is 3.58 MHz and 7.16 MHz.

Internal data bus

1/2

1/5

1/9

1/10

1/18

1/20

400 kHz

800 kHz

2 MHz

3.58 MHz

4 MHz

7.16 MHz

8 MHz

Figure 82 Block Diagram of DTMF Generator Circuit

HD404639R Series

100

Tone Generator Mode Register (TGM: $019): Four-bit write-only register, which controls output
frequencies as shown in figure 83, and is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

TGM3

TGM2

TGM0

TGM1

Tone generator mode register (TGM: $019)

TGM3

TGM2

TONEC output frequencies

f (1,209 Hz)

f (1,336 Hz)

f (1,477 Hz)

f (1,633 Hz)

TGM1

TGM0

TONER output frequencies

f (697 Hz)

f (770 Hz)

f (852 Hz)

f (941 Hz)

Figure 83 Tone Generator Mode Register (TGM)

Tone Generator Control Register (TGC: $01A): Three-bit write-only register, which controls the
start/stop of the DTMF signal output as shown in figure 84, and is reset to $0 by MCU reset. TONER and
TONEC output can be independently controlled by bits 2 and 3 (TGC2, TGC3), and the DTMF circuit is
controlled by bit 1 (TGC1) of this register.

Bit

Initial value

Read/Write

Bit name

TGC3

TGC2

Not used

TGC1

Tone generator control register (TGC: $01A)

TGC1

DTMF enable bit

DTMF disable

DTMF enable

TGC3

TONEC output control (column)

No output

TONEC output (active)

TGC2

TONER output control (row)

No output

TONER output (active)

Figure 84 Tone Generator Control Register (TGC)

HD404639R Series

101

System Clock Select Registers 1 and 2 (SSR1: $029, SSR2: $02A): Four-bit write-only registers.
These registers must be set to the value specified in figures 85 and 86 depending on the frequency of the
oscillator connected to the OSC

and OSC

pins. Note that if the combination of the oscillation frequency

and the values in these registers is different from that specified in figures 85 and 86, the DTMF output
frequencies will differ from the correct frequencies as listed in table 28.

Bit

Initial value

Read/Write

Bit name

SSR13

SSR12

SSR10

SSR11

System clock select register 1 (SSR1: $029)

SSR13

32-kHz oscillation stop

Oscillation operates in stop mode

Oscillation stops in stop mode

SSR12

32-kHz oscillation division
ratio selection

f = f /8

f = f /4

SUB X

SSR22

400 kHz

800 kHz

2 MHz

4 MHz

3.58 MHz

8 MHz

7.16 MHz

SSR11

Don't care

SSR10

Don't care

System clock
selection

SSR23

Figure 85 System Clock Select Register 1(SSR1)

HD404639R Series

102

Bit

Initial value

Read/Write

Bit name

SSR23

SSR22

SSR20

SSR21

SSR22

Serial clock select register 2 (SSR2: $02A)

SSR21

System clock division ratio

1/4 division

1/8 division

1/16 division

1/32 division

System clock selection

Selected from 400 kHz, 800 kHz,
2 MHz, 4 MHz

3.58 MHz

8 MHz

7.16 MHz

SSR20

Notes:

1. Refer to system clock select register 1 (SSR1) of figure 85.
2. The DTMF frequencies are not affected by the setting of the system clock division ratio.

SSR23

Figure 86 System Clock Select Register 2(SSR2)

Table 28 Frequency Deviation of the MCU from Standard DTMF

OSC

= 400 kHz, 800 kHz, 2 MHz, 4 MHz,

8 MHz

OSC

= 3.58 MHz, 7.16 MHz

Standard
DTMF (Hz)

MCU (Hz)

Deviation from
Standard (%)

MCU (Hz)

Deviation from
Standard (%)

697

694.44

0.37

690.58

0.92

770

769.23

0.10

764.96

0.65

852

851.06

0.11

846.33

0.67

941

938.97

0.22

933.75

0.77

1,209

1,212.12

0.26

1,205.39

0.30

1,336

1,333.33

0.20

1,325.92

0.75

1,477

1,481.48

0.30

1,473.25

0.25

1,633

1,639.34

0.39

1,630.23

0.17

Note:

This frequency deviation value does not include the frequency deviation due to the oscillator
element. Also note that in this case the ratio of the high level and low level widths in the oscillator
waveform due to the oscillator element will be 50%:50%.

HD404639R Series

103

DTMF Output: The sine waves of the row-group and column-group are individually converted in the D/A
conversion circuit which provides a high-precision ladder resistance. The DTMF output pins (TONER,
TONEC) transmit the sine waves of the row-group and column-group, respectively. Figure 87 shows the
tone output equivalent circuit. Figure 88 shows the output waveform. One cycle of this wave consists of 32
slots. Therefore, the output waveform is stable with little distortion. Table 28 lists the frequency deviation
of the MCU from standard DTMF signals.

Switch control

GND

ref

TONER

TONEC

Figure 87 Tone Output Equivalent Circuit

ref

GND

Time slots

1 2 3 4 5 6 7 8 9 10 1112 13 14 15 16 17 18 19 20 2122 23 24 25 26 27 28 29 30 31 32

Figure 88 Waveform of Tone Output

HD404639R Series

104

Comparator

The block diagram of the comparator is shown in figure 89. The comparator compares input voltage with
the reference voltage. Internal voltage or external input voltage can be selected as the reference. Internal
reference voltage is selected from sixteen levels.

Setting bit 3 (CER3) of the compare enable register (CER: $018) to 1 executes a voltage comparison.
When an input voltage at COMP

COMP

is higher than the reference voltage, the TM or TMD command

sets the status flag (ST) high for the corresponding bits of the compare data register (CDR: $017) to
COMP

COMP

. On the other hand, when an input voltage at COMP

COMP

is lower, the TM or TMD

command clears the ST to 0.

Selector

Com-
parator

Comparator data

Comparator enable

Comparator control

Internal data bus

COMP

ref

Figure 89 Block Diagram of Comparator

Compare Enable Register (CER: $018): Four-bit write-only register which enables comparator
operation, and selects the reference voltage and the analog input pin.

Compare Control Register (CCR: $016): Four-bit write-only register which selects the internal reference
voltage from sixteen levels.

Compare Data Register (CDR: $017): Four-bit read-only register which latches the result of the
comparison between the analog input pins and the reference voltage. Bits 0 to 3 show the results of
comparison with COMP

COMP

, respectively. This register can be read only by the TM or TMD

HD404639R Series

105

command. Only bit CER3 corresponds to the analog input pin selected with bits CER0 and CER1. After a
compare operation, the data in this register is not retained.

Note on Use: During the compare operation pins RD

/COMP

operate as analog inputs and

cannot operate as R ports.

The comparator can operate in active mode and subactive mode but is disabled in other modes.

The switch for the internal reference voltage is on only when the internal reference voltage is selected by
CER2.

/VC

ref

cannot operate as an R port when the external input voltage is selected as the reference.

CER2

Reference voltage selection

External input voltage

Internal voltage

Bit

Initial value

Read/Write

Bit name

CER3

CER2

CER0

CER1

Compare enable register (CER: $018)

CER3

Digital/Analog selection

Digital input mode:
RD /COMP

RD /COMP

operate as R port

Analog input mode:
RD /COMP

RD /COMP

operate as analog input

CER1

Analog input pin selection

COMP

CER0

Figure 90 Compare Enable Register (CER)

HD404639R Series

108

Programmable ROM (HD407A4639R)

The HD407A4639R is a ZTAT

microcomputer with built-in PROM that can be programmed in PROM

mode.

PROM Mode Pin Description

MCU Mode

PROM Mode

MCU Mode

PROM Mode

Pin No.

Pin Name

I/O

Pin Name

I/O Pin No.

Pin Name

I/O

Pin Name

I/O

/COMP0

INT

/COMP1

INT

I/O

/COMP2

/INT

I/O

/COMP3

/INT

I/O

/VC

ref

GND

/INT

I/O

TEST

I/O

OSC

I/O

OSC

I/O

RESET

I/O

GND

I/O

GND

I/O

/TOB

I/O

/TOC

I/O

/TOD

I/O

EVNB

I/O

/EVND

I/O

SCK

I/O

/SI

I/O

/SO

I/O

SCK

I/O

/SI

I/O

STOPC

/SO

I/O

HD404639R Series

109

MCU Mode

PROM Mode

MCU Mode

PROM Mode

Pin No.

Pin Name

I/O

Pin Name

I/O Pin No.

Pin Name

I/O

Pin Name

I/O

I/O

I/O 70

I/O

I/O 71

I/O

I/O 72

I/O

I/O 73

I/O

I/O 74

I/O

I/O 75

I/O

I/O 76

SEL

I/O

I/O 77

TONEC

I/O

I/O 78

TONER

I/O

I/O 79

I/O

I/O 80

ref

Notes: 1. I/O: Input/output pin, I: Input pin, O: Output pin

2. Each of O

has two pins; before using, each pair must be connected together.

Programming the Built-In PROM

The MCU's built-in PROM is programmed in PROM mode. PROM mode is set by pulling

TEST, M

, and

low, and RESET high as shown in figure 93. In PROM mode, the MCU does not operate, but it can be

programmed in the same way as any other commercial 27256-type EPROM using a standard PROM
programmer and an 80-to-28-pin socket adapter. Recommended PROM programmers and socket adapters
of the HD407A4639 are listed in table 30.

Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion
circuit to enable the use of a general-purpose PROM programmer. This circuit splits each instruction into
five lower bits and five upper bits that are read from or written to consecutive addresses. This means that
if, for example, 16 kwords of built-in PROM are to be programmed by a general-purpose PROM
programmer, a 32-kbyte address space ($0000$7FFF) must be specified.

Warnings

1. Always specify addresses $0000 to $7FFF when programming with a PROM programmer. If address

$8000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in
unused addresses to $FF.

Note that the plastic-package version cannot be erased or reprogrammed.

HD404639R Series

110

2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1

positions match), otherwise overcurrents may damage the LSI. Before starting programming, make
sure that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the
programmer.

3. PROM programmers have two voltages (V

): 12.5 V and 21 V. Remember that ZTAT

devices

require a V

of 12.5 V--the 21-V setting will damage them. 12.5 V is the Intel 27256 setting.

Programming and Verification

The built-in PROM of the MCU can be programmed at high speed without risk of voltage stress or damage
to data reliability.

Programming and verification modes are selected as listed in table 29.

Table 29 PROM Mode Selection

Pin

Mode

Programming

Low

High

Data input

Verification

High

Low

Data output

Programming inhibited

High

High impedance

Table 30 Recommended PROM Programmers and Socket Adapters

PROM Programmer

Socket Adapter

Manufacturer

Model Name

Package

Manufacturer

Model Name

DATA I/O Corp.

121B

FP-80B

Hitachi

HS463ESF01H

AVAL Corp.

PKW-1000

HD404639R Series

112

Addressing Modes

RAM Addressing Modes

The MCU has three RAM addressing modes, as shown in figure 94 and described below.

Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used
as a RAM address. When the area from $090 to $25F is used, a bank must be selected by the bank register
(V: $03F).

Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains
the opcode, and the contents of the second word (10 bits) are used as a RAM address.

Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses
from $040 to $04F, are accessed with the LAMR and XMRA instructions.

W register

X register

Y register

RAM address

Register Direct Addressing

RAM address

Direct Addressing

2nd word of Instruction

Opcode

1st word of Instruction

RAM address

Memory Register Addressing

Opcode

Instruction

Figure 94 RAM Addressing Modes

HD404639R Series

113

ROM Addressing Modes and the P Instruction

The MCU has four ROM addressing modes, as shown in figure 95 and described below.

Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing
the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits
(PC

) with 14-bit immediate data.

Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program
can branch to any address in the current page by executing the BR instruction. This instruction replaces the
eight low-order bits of the program counter (PC

) with eight-bit immediate data. If the BR instruction

is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next
physical page, as shown in figure 97. This means that the execution of the BR instruction on a page
boundary will make the program branch to the next page.

Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages.

Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000
$003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data
are placed in the six low-order bits of the program counter (PC

), and 0s are placed in the eight high-

order bits (PC

Table Data Addressing Mode: A program can branch to an address determined by the contents of four-
bit immediate data, the accumulator, and the B register by executing the TBR instruction.

P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction
as shown in figure 96. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator
and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers.
If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and
R2 port output registers at the same time.

The P instruction has no effect on the program counter.

HD404639R Series

114

2nd word of instruction

Opcode

1st word of instruction

[JMPL]
[BRL]
[CALL]

Program counter

Direct Addressing

Zero Page Addressing

Instruction

[CAL]

Opcode

Program counter

Accumulator

Program counter

Table Data Addressing

B register

[TBR]

Instruction

Opcode

Instruction

Program counter

Current Page Addressing

[BR]

Figure 95 ROM Addressing Modes

HD404639R Series

117

Absolute Maximum Ratings

Item

Symbol

Value

Unit

Note

Supply voltage

0.3 to +7.0

Programming voltage

0.3 to +14.0

Pin voltage

0.3 to V

+ 0.3

Total permissible input current

105

Total permissible output current

Maximum input current

4, 5

4, 6

Maximum output current

7, 8

7, 9

Operating temperature

opr

20 to +75

Storage temperature

stg

55 to +125

Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation

must be under the conditions stated in the electrical characteristics tables. If these conditions are
exceeded, the LSI may malfunction or its reliability may be affected.

1. Applies to D

) of HD407A4639R.

2. The total permissible input current is the total of input currents simultaneously flowing in from all

the I/O pins to GND.

3. The total permissible output current is the total of output currents simultaneously flowing out from

to all I/O pins.

4. The maximum input current is the maximum current flowing from each I/O pin to GND.

5. Applies to D

, and

R0RC.

6. Applies to D

7. The maximum output current is the maximum current flowing out from V

to each I/O pin.

8. Applies to D

and R0RC.

9. Applies to D

HD404639R Series

118

Electrical Characteristics

DC Characteristics (HD404638R, HD404639R, HD40A4638R, HD40A4639R: V

= 2.7 to 6.0 V,

GND = 0 V, T

= 20 to +75

C; HD407A4639R: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20 to +75

unless otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

Input high
voltage

RESET,

STOPC

INT

SCK

, SI

EVNB

, EVND

0.9V

+ 0.3

OSC

0.3

+ 0.3

External clock

Input low
voltage

RESET,

STOPC

INT

SCK

, SI

EVNB

, EVND

0.3

0.10 V

OSC

0.3

External clock

Output high
voltage

SCK

, SO

SCK

, SO

TOB, TOC, TOD

1.0

= 0.5 mA

Output low
voltage

SCK

, SO

SCK

, SO

TOB, TOC, TOD

0.4

= 0.4 mA

I/O leakage
current

RESET,

STOPC

INT

SCK

, SI

, SO

EVNB

EVND, OSC

TOB, TOC, TOD

= 0 V to V

Current
dissipation
in active
mode

CC1

2.5

= 5 V,

OSC

= 4 MHz,

digital input mode

CC2

0.3

1.0

= 3 V,

OSC

= 800 kHz,

digital input mode

CC3

= 5 V,

OSC

= 8 MHz,

digital input mode

2, 8

CMP1

6.5

= 5 V,

OSC

= 4 MHz,

analog comp.
mode

HD404639R Series

119

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

Current
dissipation
in active
mode

CMP2

2.8

3.5

= 3 V,

OSC

= 800 kHz,

analog comp.
mode

CMP3

= 5 V,

OSC

= 8 MHz,

analog comp.
mode

3, 8

Current
dissipation
in standby
mode

SBY1

1.0

= 5 V,

OSC

= 4 MHz

SBY2

0.1

0.3

= 3 V,

OSC

= 800 kHz

SBY3

2.0

4.0

= 5 V,

OSC

= 8 MHz

4, 8

Current
dissipation
in subactive
mode

SUB

= 3 V,

32 kHz oscillator

Current
dissipation
in watch
mode

WTC

7.5

= 3 V,

32 kHz oscillator

Current
dissipation
in stop
mode

STOP

0.5

= 3 V,

no 32 kHz
oscillator

Stop mode
retaining
voltage

STOP

No 32 kHz
oscillator

Comparator
input
reference
voltage
scope

ref

1.2

Allowable
error of
internal
reference
voltage

OFS

100

OFS

= reference

voltage VC

ref

Notes: 1. Output buffer current is excluded.

2. I

CC1

, I

CC2

and I

CC3

are the source currents when no I/O current is flowing while the MCU is in reset

state.

Test conditions: MCU: Reset

Pins:

RESET at V

0.3 to V

)

TEST

at V

0.3 to V

)

HD404639R Series

120

3. RD

pins are in analog input mode when no I/O current is flowing.

Test conditions: MCU: DTMF does not operate

Pins:

/COMP

at GND (0 V to 0.3 V)

/COMP

at GND (0 V to 0.3 V)

/COMP

at GND (0 V to 0.3 V)

/COMP

at GND (0 V to 0.3 V)

/VC

ref

at GND (0 V to 0.3 V)

4. I

SBY1

, I

SBY2

and I

SBY3

are the source currents when no I/O current is flowing while the MCU timer is

operating.

Test conditions: MCU: I/O reset

Serial interface stopped

DTMF does not operate

Standby mode

Pins:

RESET at GND (0 V to 0.3 V)

TEST

at V

0.3 to V

)

5. These are the source currents when no I/O current is flowing.

Test conditions: Pins:

RESET at GND (0 V to 0.3 V)

TEST

at V

0.3 to V

)

at V

0.3 to V

)

Applies to HD407A4639R.

6. RAM data retention.

7. The reference voltage is the expected internal VC

ref

voltage selected by the compare control

Example: when CCR = $2, reference voltage is 4/22 x V

CC.

8. Applies to HD40A4638R, HD40A4639R, HD407A4639R.

HD404639R Series

121

I/O Characteristics for Standard Pins (HD404638R, HD404639R, HD40A4638R, HD40A4639R: V

= 2.7 to 6.0 V, GND = 0 V, T

= 20 to +75

C; HD407A4639R: V

= 2.7 to 5.5 V, GND = 0 V, T

= 

20 to +75

C, unless otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

Input high
voltage

R0RD, RE

0.7 V

+ 0.3

Input low
voltage

R0RD, RE

0.3

0.3V

Output high
voltage

R0RC

1.0

= 0.5 mA

Output low
voltage

R0RC

0.4

= 0.4 mA

I/O leakage
current

, R0RD

= 0 V to V

= 0 V

1, 2

= V

0.3 V to V

1, 3

= 0 V to 0.3 V

1, 3

Pull-up MOS
current

R0RC

= 3 V,

= 0 V

Input high
voltage

IHA

COMP

ref

+0.1 --

Analog compare mode

Input low
voltage

ILA

COMP

ref

0.1

Analog compare mode

Notes: 1. Output buffer current is excluded.

2. Applies to HD404638R, HD404639R, HD40A4638R and HD40A4639R.

3. Apples to HD407A4639R.

HD404639R Series

122

I/O Characteristics for High-Current Pins (HD404638R, HD404639R, HD40A4638R, HD40A4639R:

= 2.7 to 6.0 V, GND = 0 V, T

= 20 to +75

C; HD407A4639R: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20 to +75

C, unless otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

Input high
voltage

0.7 V

+ 0.3

Input low
voltage

0.3

0.3 V

Output high
voltage

1.0 --

= 0.5 mA,

2.0

= 10 mA,

= 4.5 V to 6.0 V

Output low
voltage

0.4

= 0.4 mA

2.0

= 15 mA,

= 4.5 V to 6.0 V

I/O leakage
current

= 0 V to V

Pull-up MOS
current

= 3 V, V

= 0 V

Pull-down
MOS current

= 3 V, V

= 3 V

Notes: 1. HD407A4639R; V

= 4.5 V to 5.5 V

2. Output buffer current is excluded.

HD404639R Series

123

DTMF Characteristics (HD404638R, HD404639R, HD40A4638R, HD40A4639R: V

= 2.7 to 6.0 V,

GND = 0 V, T

= 20 to +75

C; HD407A4639R: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20 to +75

unless otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

Tone output
voltage (1)

TONER

500

660

rms

ref

GND = 2.0 V,

= 100 k

Tone output
voltage (2)

TONEC

520

690

rms

ref

GND = 2.0 V,

= 100 k

Tone output
distortion

%DIS

Short circuit between
TONER and TONEC
R

= 100 k

Tone output
ratio

2.5

Short circuit between
TONER and TONEC
R

= 100 k

Notes: 400 kHz, 800 kHz, 2 MHz, 3.58 MHz, 4MHz, 7.16 MHz, or 8 MHz can be used as the operating

trequency (f

OSC

1. See figure 98.

2. See figure 99.

HD404639R Series

124

AC Characteristics (HD404638R, HD404639R, HD40A4638R, HD40A4639R: V

= 2.7 to 6.0 V,

GND = 0 V, T

= 20 to +75

C; HD407A4639R: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20 to +75

unless otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

Clock oscillation
frequency

OSC

400

kHz

800

kHz

MHz

3.58

MHz

7.16

MHz

1, 12

MHz

1, 12

X1, X2

32.768

kHz

Instruction cycle
time

cyc

OSC

= 4 MHz,

1/32 division

OSC

= 4 MHz,

1/16 division

OSC

= 4 MHz,

1/8 division

OSC

= 4 MHz,

1/4 division

subcyc

244.14

32 kHz oscillator,
1/8 division

122.07

32 kHz oscillator,
1/4 division

Oscillation
stabilization time
(ceramic)

OSC

7.5

4, 5

Oscillation
stabilization time
(crystal)

OSC

= 3.5 V to 6.0 V

4, 5, 6

4, 5

X1, X2

= 10

C to +60

External clock
high width

CPH

OSC

1100

OSC

= 400 kHz

550

OSC

= 800 kHz

215

OSC

= 2 MHz

115

OSC

= 3.58 MHz

105

OSC

= 4 MHz

57.5

OSC

= 7.16 MHz

7, 12

52.5

OSC

= 8 MHz

7, 12

HD404639R Series

125

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

External clock
low width

CPL

OSC

1100

OSC

= 400 kHz

550

OSC

= 800 kHz

215

OSC

= 2 MHz

115

OSC

= 3.58 MHz

105

OSC

= 4 MHz

57.5

OSC

= 7.16 MHz

7, 12

52.5

OSC

= 8 MHz

7, 12

External clock
rise time

CPr

OSC

150

OSC

= 400 kHz

OSC

= 800 kHz

OSC

= 2 MHz

OSC

= 3.58 MHz

OSC

= 4 MHz

12.5

OSC

= 7.16 MHz

7, 12

OSC

= 8 MHz

7, 12

External clock
fall time

CPf

OSC

150

OSC

= 400 kHz

OSC

= 800 kHz

OSC

= 2 MHz

OSC

= 3.58 MHz

OSC

= 4 MHz

12.5

OSC

= 7.16 MHz

7, 12

OSC

= 8 MHz

7, 12

INT

EVNB

, EVND

high width

INT

EVNB

EVND

cyc

subcyc

INT

EVNB

, EVND

low width

INT

EVNB

EVND

cyc

subcyc

RESET high
width

RSTH

RESET

cyc

STOPC

low

width

STPL

STOPC

RESET fall time

RSTf

RESET

STOPC

rise time t

STPr

STOPC

HD404639R Series

126

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

Input
capacitance

All pins
except
D

f = 1 MHz, V

= 0 V

f = 1 MHz, V

= 0 V

180

f = 1 MHz, V

= 0 V

Analog
comparator
stabilization time

CSTB

COMP

cyc

Notes: Except for the HD407A4639R, when V

is between 2.2 V and 6.0 V, watch mode can be supported,

and instruction execution is possible in active mode.

1. Bits 0 and 1 (SSR10, SSR11) of system clock select register 1 (SSR1: $029) and bits 2 and 3

(SSR22, SSR23) of system clock select register 2 (SSR2: $02A) must be set according to the
system clock frequency.

2. Bits 0 and 1 (SSR20, SSR21) of system clock select register 2 (SSR2: $02A) must be set

according to the division ratio of the system clock frequency.

3. Bit 2 (SSR12) of system clock select register 1 (SSR1: $029) must be set according to the

division ratio of the subsystem clock frequency.

4. The oscillation stabilization time is the period required for the oscillator to stabilize after V

reaches 2.7 V at power-on, or after RESET input goes high or

STOPC

input goes low when stop

mode is cancelled. At power-on or when stop mode is cancelled, RESET or

STOPC

must be

input for at least t

to ensure the oscillation stabilization time. If using a ceramic oscillator,

contact its manufacturer to determine what stabilization time is required, since it will depend on
the circuit constants and stray capacitance. Set bits 0 and 1 (MIS0, MIS1) of the miscellaneous
register (MIS: $00C) according to the system oscillation of the oscillation stabilization time.

5. Bits 0 and 1 (MIS0, MIS1) of the miscellaneous register (MIS: $00C) must be set according to

the oscillation stabilization time of the system clock oscillator.

6. HD407A4639R: V

= 3.5 V to 5.5 V.

7. Refer to figure 100.

8. Refer to figure 101. The t

cyc

unit applies when the MCU is in standby or active mode. The t

subcyc

unit applies when the MCU is in watch or subactive mode.

9. Refer to figure 102.

10. Refer to figure 103.

11. Analog comparator stabilization time is the period for the analog comparator to stabilize and for

correct data to be read after entering RD

/COMP

into analog input mode.

12. Applies to HD40A4638R, HD40A4639R and HD407A4639R.

HD40A4638R, HD40A4639R: V

= 4.5 V to 6.0 V

HD407A4639R: V

= 4.5 V to 5.5 V

13. Applies to HD404638R, HD404639R, HD40A4638R and HD40A4639R.

14. Applies to HD407A4639R.

HD404639R Series

127

Serial Interface Timing Characteristics (HD404638R, HD404639R, HD40A4638R, HD40A4639R:

= 2.7 to 6.0 V, GND = 0 V, T

= 20 to +75

C; HD407A4639R: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20 to +75

C, unless otherwise specified)

During Transmit Clock Output

Item

Symbol

Pin(s)

Test Condition

Min

Typ

Max

Unit

Notes

Transmit
clock cycle
time

Scyc

SCK

Load shown in figure 105

cyc

Transmit
clock high
width

SCKH

SCK

Load shown in figure 105

0.5

Scyc

Transmit
clock low
width

SCKL

SCK

Load shown in figure 105

0.5

Scyc

Transmit
clock rise
time

SCKr

SCK

Load shown in figure 105

200

Transmit
clock fall time

SCKf

SCK

Load shown in figure 105

200

Serial output
data delay
time

DSO

Load shown in figure 105

500

Serial input
data setup
time

SSI

300

Serial input
data hold
time

HSI

300

HD404639R Series

128

During Transmit Clock Input

Item

Symbol

Pin(s)

Test Condition

Min

Typ

Max

Unit

Notes

Transmit
clock cycle
time

Scyc

SCK

cyc

Transmit
clock high
width

SCKH

SCK

0.5

Scyc

Transmit
clock low
width

SCKL

SCK

0.5

Scyc

Transmit
clock rise
time

SCKr

SCK

200

Transmit
clock fall time

SCKf

SCK

200

Serial output
data delay
time

DSO

Load shown in figure 105

500

Serial input
data setup
time

SSI

300

Serial input
data hold
time

HSI

300

Note:

1. Refer to figure 104.

R = 100 k

TONEC

TONER

GND

Figure 98 TONE Output Load Circuit

HD404639R Series

132

HD404638/HD404639/HD404638R/HD404639R/HD40A4638R/HD40A4639R Option List

1. ROM Size

Please check off the appropriate applications and
enter the necessary information.

Please specify the first type listed below (the upper bits and lower bits are mixed together) when using
the EPROM on-package microcomputer type (including ZTAT

version).

Standaed version : HD404638

Standard version : HD404638R

High-speed version : HD40A4638R

Standard version : HD404639

Standard version : HD404639R

High-speed version : HD40A4639R

ROM
8-kword

ROM
16-kword

Date of order

Customer

Department

Name

ROM code name

LSI number

2. Optional Functions

Note:

Options marked with an asterisk require a subsystem crystal oscillator (X1, X2).

With 32-kHz CPU operation, with time-base for clock

Without 32-kHz CPU operation, with time-base for clock

Without 32-kHz CPU operation, without time-base

4. Oscillator for OSC1 and OSC2

Ceramic oscillator

Crystal oscillator

External clock

f =

MHz

3. ROM Code Media

EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are

programmed to the same EPROM in alternating order (i.e., LULULU...).

EPROM: The upper bits and lower bits are separated. The upper bits and lower five bits are

programmed to different EPROMs.

5. Stop Mode

Used

Not used

6. Package

FP-80B

HD404639R Series

133

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent,

copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party's rights, including
intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi's sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor

products.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HD407A4639R

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HD407A4639R