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Электронный компонент: HB28B512IA2

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Rev.2.00, Jun.5.2003, page 1 of 50
HB28B1700IA2
HB28B1000IA2
HB28B512IA2
IDE Card
REJ03C0041-0200Z
(Previous ADE-203-1370B (Z) Rev.1.0)
Rev. 2.00
Jun. 5, 2003
Description
HB28B1700IA2, HB28B1000IA2, HB28B512IA2 are IDE cards. These cards comply with ATA-5
specification standard, and are suitable for the usage of data storage memory medium for PC or any other
electric equipment. These cards are equipped with Renesas 512 Mega bit Flash memory. By using these
cards it is possible to operate good performance for a system which has ATA interface.
Features
Conform to ANSI AT Attachment-5 (ATA-5) specification standard
5 V power supplies are used
Card density is 1.7 Giga bytes maximum
This card is equipped with Renesas 512 Mega bit Flash memory
Data write is 300,000 cycle/block
Data reliability is less than 1 error in 10
14
bits read
High reliability based on internal ECC (Error Correcting Code) function
High reliability based on CRC (Cyclic Redundancy Code) on Ultra DMA mode transfer
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Rev.2.00, Jun.5.2003, page 2 of 46
Card Line Up*
1

Type No.

Card density

Capacity*
4
Total sectors/
card*
3
Sectors/
track*
2
Number of
head
Number of
cylinder
HB28B1700IA2 1.7 GB
1,794,465,792 byte 3,504,816
63
16
3,477
HB28B1000IA2 1.0 GB
1,025,482,752 byte 2,002,896
63
16
1,987
HB28B512IA2
512 MB
512,483,328 byte
1,000,944
63
16
993
Notes: 1. These data are written in ID.
2. Total tracks = number of head
number of cylinder.
3. Total sectors/card = sectors/track
number of head
number of cylinder.
4. It is the logical address capacity including the area which is used for file system.
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Rev.2.00, Jun.5.2003, page 3 of 46
Card Pin Assignment
Pin No.
Signal name
Pin No.
Signal name
Pin No.
Signal name
1 GND
24
47
2 D3
25
48
3 D4
26
49
4 D5
27
A2
50
5 D6
28
A1
51
VCC
6 D7
29
A0
52
7 -CS0
30
D0
53
8
31
D1 54
9
32
D2 55
10
33
-IOIS16
56
-CSEL
11
34
GND
57
*
1
12
35
GND
58
-RESET
13
36
*
1
59
IORDY
14
37
D11
60
DMARQ
15
38
D12
61
-DMACK
16 INTRQ
39 D13
62 -DASP
17 V
CC
40
D14 63
-PDIAG
18
41
D15
64
D8
19
42
-CS1
65
D9
20
43
*
1
66
D10
21
44
-DIOR
67
*
1
22
45
-DIOW
68
GND
23
46
Note: 1. Host system should not connect these pin.
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Rev.2.00, Jun.5.2003, page 4 of 46
Card Pin Explanation
Host Interface Pin Explanation
Signal name
Direction Pin No.
Description
-RESET
I
58
This signal is active low host reset pin. Once the host asserts
-RESET, the host must keep -RESET asserting for at least 25
s.
A2 to A0
I
27, 28, 29 Address bus of Host I/F is A2 to A0. A2 is MSB and A0 is
LSB.
D15 to D0
I/O
41, 40, 39
38, 37, 66
65, 64, 6
5, 4, 3
2, 32, 31
30
Data bus of Host I/F is D15 to D0. D0 is the LSB of the even
byte of the word. D8 is the LSB of the odd byte of the word.
-CS0
-CS1
I
7, 42
-CS1 is used for selecting the Alternate Status register and the
Device Control register. -CS0 is used for the other task file
registers.
-DIOW
I
45
-DIOW is used for control of write data in I/O task file area.
STOP
(Ultra DMA mode)
This signal must be negated prior to initiation of an Ultra DMA
burst. And this signal must be negated before data is
transferred in an Ultra DMA burst. Assertion during an Ultra
DMA burst flowing indicates the termination of the Ultra DMA
burst.
-DIOR
I
44
-DIOR is used for control of read data in I/O task file area.
-HDMARDY
(Ultra DMA data-in)
-HDMARDY is a data flow control signal. The host shall assert
this signal to indicate that the host is ready to receive Ultra
DMA data-in bursts. The host may negate this signal to
indicate that the host pauses an Ultra DMA data-in burst.
HSTROBE
(Ultra DMA data-out)
HSTROBE is a data strobe signal. Both the rising and falling
edges of HSTROBE latch the data of D15 to D0 into this card.
Stopping generating HSTROBE edges indicates that the host
pauses an Ultra DMA data-out burst.
-DMACK
I
61
This signal is used for response to asserting DMARQ to initiate
DMA transfers.
-IOIS16
O
33
This output signal is asserted low when the 16-bit wide data
register is addressed and the card is prepared to send or
receive a 16-bit wide data.
INTRQ
O
16
This signal is the active high Interrupt Request to the host.
DMARQ
O
60
This signal is asserted high when the card is ready to DMA
data transfers.
-PDIAG
I/O
63
-PDIAG is the Pass Diagnostic signal in Master/Slave
handshake protocol.
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Rev.2.00, Jun.5.2003, page 5 of 46
Signal name
Direction Pin No.
Description
IORDY
O
59
IORDY is used at PIO modes 3 and above. IORDY is negated
to extend the host transfer cycle of any host register access
(Read or Write) when the card is not ready to respond to a
data transfer request.
DSTROBE
(Ultra DMA data-in)
DSTROBE is a data strobe signal. The host latches the data
of D15 to D0 at both the rising and falling edge of DSTROBE.
Stopping generating DSTROBE edges indicates that the card
pauses an Ultra DMA data-in burst.
-DDMARDY
(Ultra DMA data-out)
-DDMARDY is a data flow control signal. The card asserts this
signal to indicate that the card is ready to receive Ultra DMA
data-out bursts. The card negates this signal to indicate that
the card pauses an Ultra DMA data-out burst.
-DASP
I/O
62
-DASP is the Device Active/Slave Present signal in the
Master/Slave handshake protocol.
-CSEL
I
56
This signal is used to configure this card as a Master or a
Slave. When this pin is grounded, this card is configured as a
Master. When the pin is open, this card is configured as a
Slave.