2001/2/27 Realtek
Semiconductor
Corp. Confidential Page 1
RTL8308B
8-port 10/100 Ethernet Switch
Controller with Embedded Memory
RTL8308B
8-Port 10/100 Ethernet Switch Controller
with Embedded Memory
The RTL8308B chip is a 128-pin low cost and ultra low power consumption 8-port
10/100M Ethernet switch controller integrated both with a 2M bits embedded DRAM as
packet buffer and a 8K entries of address table. The RTL8308B supports reduced MII (RMII)
interface. Only single 50MHz oscillator is needed and the EEPROM is optional, so as to
save your Bill Of Material. In addition, the RTL8308B provides a LED display specially to
indicate a network loop existence.
1. Features
Supports eight 10/100Mbps Ethernet ports
with RMII interface
Provides non-blocking and
non-head-of-line-blocking forwarding
2M bits DRAM is built in as packet storage
buffer. Page based buffer management to
efficiently utilize the internal packet buffer
Ultra low power consumption with less
than 160mA at 3.3V operating voltage
Embedded 8K entries of look-up table and
128 entries of CAM
Supports address hashing or direct mapping
for look-up table. 128-entry CAM is used to
eliminate the hash collision problem
Supports full and half duplex operations
Link, speed and duplex status are
auto-detected via MDIO
Flow control fully supported:
Half-duplex: back pressure
Full-duplex: IEEE 802.3X
Auto-negotiated Full-duplex flow control
by writing the ability via MDIO to external
PHY
Supports Store-and-forward and
cut-through operation
Provides a LED display especially to
indicate a network loop existence
Broadcast storm control
Reversible PHYAD order for diverse PHY
3.3V 24LC02 interface
Optional EEPROM 24LC02 for Loop
detect configuration
128-pin PQFP, 0.35 um, 3.3V CMOS
technology
2001/2/27 Realtek
Semiconductor
Corp. Confidential Page 2
RTL8308B
8-port 10/100 Ethernet Switch
Controller with Embedded Memory
2. General Description
The RTL8308B provides eight 10/100 Mbps RMII Ethernet ports. Each port can operate in 10 Mbps
or 100 Mbps data rate, and in full or half duplex mode. Speed, duplex, link status and flow control
can be acquired by periodically polling the status of the PHY devices via MDIO.
Address look-up table consists of 8K entries of hash table and a 128 entries of CAM. The RTL8308B
uses address hashing algorithm or direct mapping method to search destination MAC address and
record source MAC address from and to the hash table.
The RTL8308B supports IEEE 802.3x full duplex flow control and half duplex back pressure control.
The ability of IEEE 802.3x flow control is auto-negotiated by writing the flow control ability via
MDIO. The reversible PHYAD order feature is provided to connect diverse external PHY devices for
PCB layout.
The RTL8308B provides loop detect LED for visual diagnostic when detecting the network loop.
And the Broadcast storm filtering function is provided for unusual broadcast storm.
The RTL8308B supports non-blocking 148800 packets/second wire speed forwarding rate and
special design to resolve the head-of-line-blocking problem. The RTL8308B uses 2-wire 24LC02
interface to access external serial EEPROM. If without 24LC02, RTL8308B is in default
configuration. Only one 50MHz OSC is needed.
Realtek
RTL8308B
Quad-HY
50MHz
OSC
EEPROM24LC02
Quad-PHY
10/100 Mbps x 8
Example of 8-port Switch System diagram
2001/2/27 Realtek
Semiconductor
Corp. Confidential Page 3
RTL8308B
8-port 10/100 Ethernet Switch
Controller with Embedded Memory
Table of Content
1. FEATURES ................................................................................................................................................................. 1
2. GENERAL
DESCRIPTION ...................................................................................................................................... 2
3. BLOCK
DIAGRAM ................................................................................................................................................... 5
4. FUNCTIONAL
DESCRIPTION ............................................................................................................................... 6
Reset............................................................................................................................................................................................ 6
RMII interface ........................................................................................................................................................................... 6
Serial Management Interface MDC/MDIO ................................................................................................................................. 6
Reversible PHYAD Order......................................................................................................................................................... 7
Address Search and Learning................................................................................................................................................... 7
Address Hashing Mode ............................................................................................................................................................. 7
Address Direct Mapping Mode................................................................................................................................................. 7
Illegal Frame .............................................................................................................................................................................. 7
Back off Algorithm .................................................................................................................................................................... 8
Inter-Frame Gap........................................................................................................................................................................ 8
Buffer Management................................................................................................................................................................... 8
Buffer Manager ......................................................................................................................................................................... 8
Data Reception........................................................................................................................................................................... 9
Data Forwarding ....................................................................................................................................................................... 9
Flow Control .............................................................................................................................................................................. 9
Cut Through............................................................................................................................................................................... 9
Broadcast Storm Control ........................................................................................................................................................ 10
Loop Detection......................................................................................................................................................................... 10
Head-Of-Line Blocking ........................................................................................................................................................... 10
24LC02 Interface ..................................................................................................................................................................... 10
24LC02 Device Operation........................................................................................................................................................11
5. PIN ASSIGNMENT................................................................................................................................................... 13
6. PIN
DESCRIPTIONS............................................................................................................................................... 14
7.
SERIAL EEPROM 24LC02 FORMAT................................................................................................................... 15
2001/2/27 Realtek
Semiconductor
Corp. Confidential Page 4
RTL8308B
8-port 10/100 Ethernet Switch
Controller with Embedded Memory
8. ELECTRICAL
CHARACTERISTICS................................................................................................................... 16
8.1
T
EMPERATURE
L
IMIT
R
ATINGS
: .................................................................................................................................. 16
8.2
DC
C
HARACTERISTICS
................................................................................................................................................ 16
8.3
AC
C
HARACTERISTICS
................................................................................................................................................ 16
8.3.1 Reset and Clock Timing ................................................................................................................................................. 16
8.3.2 RMII Timing ................................................................................................................................................................... 17
8.3.3 PHY Management Timing ............................................................................................................................................. 18
8.3.4 Serial EEPROM 24LC02 Timing .................................................................................................................................. 19
9. MECHANICAL
INFORMATION .......................................................................................................................... 20
2001/2/27 Realtek
Semiconductor
Corp. Confidential Page 5
RTL8308B
8-port 10/100 Ethernet Switch
Controller with Embedded Memory
3. Block Diagram
8 Ports
R
MII RMII PHY EEPROM LED
Management I/F I/F
10/100 10/100 I/F
MAC MAC
EDORAM Packet
I/F Buffer
RXFIFO TXFIFO
Space
FIFOs,
QUEUE, DMA
Flow Engine
TX Start Addr. Control,
Queue
RX/TX Page
RX/TX F.P.P. F.P.P. Pointer
FIFOs
FIFO
Switching Space
Logic
Flow control
8K-entry
Address
Table
Address-Lookup
128-entry Address CAM Engine
F.P.P Buffer
FIFO
Manager
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