This product conforms to specifications per the terms of the Ramtron
Ramtron International Corporation
standard warranty. Production processing does not necessarily in-
1850 Ramtron Drive, Colorado Springs, CO 80921
clude testing of all parameters.
(800) 545-FRAM, (719) 481-7000, Fax (719) 481-7058
www.ramtron.com
Rev. 2.1
Aug. 2003
Page 1 of 14
FM25C160
16Kb FRAM Serial Memory
Features
16K bit Ferroelectric Nonvolatile RAM
Organized as 2,048 x 8 bits
High Endurance 1 Trillion (10
12
) Read/Writes
10 year Data Retention
NoDelayTM Writes
Advanced High-Reliability Ferroelectric Process
Very Fast Serial Peripheral Interface - SPI
Up to 5 MHz maximum Bus Frequency
Direct hardware replacement for EEPROM
SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
Sophisticated Write Protection Scheme
Hardware Protection
Software Protection
Low Power Consumption
10
A Standby Current
Industry Standard Configuration
Industrial Temperature -40
C to +85
C
8-pin SOIC
Description
The FM25C160 is a 16-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile but operates in other respects as a RAM.
It provides reliable data retention for 10 years while
eliminating the complexities, overhead, and system
level reliability problems caused by EEPROM and
other nonvolatile memories.
Unlike serial EEPROMs, the FM25C160 performs
write operations at bus speed. No write delays are
incurred. Data is written to the memory array mere
hundreds of nanoseconds after it has been
successfully transferred to the device. The next bus
cycle may commence immediately. In addition, the
product offers substantial write endurance compared
with other nonvolatile memories. The FM25C160 is
capable of supporting up to 10
12
read/write cycles --
far more than most systems will require from a serial
memory.
These capabilities make the FM25C160 ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection,
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss.
The FM25C160 provides substantial benefits to users
of serial EEPROM, in a hardware drop-in
replacement. The FM25C160 uses the high-speed SPI
bus, which enhances the high-speed write capability
of FRAM technology. The specifications are
guaranteed over an industrial temperature range of
-40C to +85C.
Pin Configuration
Pin Name
Function
/CS Chip
Select
/WP Write
Protect
/HOLD Hold
SCK Serial
Clock
SI
Serial Data Input
SO
Serial Data Output
VDD 5V
VSS Ground
Ordering Information
FM25C160-S 8-pin
SOIC
CS
SO
WP
VSS
VDD
HOLD
SCK
SI
1
2
3
4
8
7
6
5
FM25C160
Rev. 2.1
Aug. 2003
Page 2 of 14
Instruction Decode
Clock Generator
Control Logic
Write Protect
Instruction Register
Address Register
Counter
512 x 32
FRAM Array
11
Data I/O Register
8
Nonvolatile Status
Register
3
WP
CS
HOLD
SCK
SO
SI
Figure 1. Block Diagram
Pin Description
Pin Name
I/O
Pin Description
/CS
Input
Chip Select: This active low input activates the device. When high, the device enters
low-power standby mode, ignores other inputs, and all outputs are tri-stated. When
low, the device internally activates the SCK signal. A falling edge on /CS must occur
prior to every op-code.
SCK
Input
Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on
the rising edge and outputs occur on the falling edge. Since the device is static, the
clock frequency may be any value between 0 and 5 MHz and may be interrupted at
any time.
/HOLD
Input
Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation
for another task. When /HOLD is low, the current operation is suspended. The device
ignores any transition on SCK or /CS. All transitions on /HOLD must occur while
SCK is low.
/WP
Input
Write Protect: This active low pin prevents write operations to the status register. This
is critical since other write protection features are controlled through the status
register. A complete explanation of write protection is provided on page 6. *Note that
the function of /WP is different from the FM25160.
SI
Input
Serial Input: All data is input to the device on this pin. The pin is sampled on the rising
edge of SCK and is ignored at other times. It should always be driven to a valid logic
level to meet IDD specifications.
* SI may be connected to SO for a single pin data interface.
SO
Output
Serial Output. SO is the data output pin. It is driven actively during a read and remains
tri-state at all other times including when /HOLD is low. Data transitions are driven on
the falling edge of the serial clock.
* SO may be connected to SI for a single pin data interface.
VDD
Supply
Supply Voltage. 5V
VSS Supply
Ground
FM25C160
Rev. 2.1
Aug. 2003
Page 3 of 14
Overview
The FM25C160 is a serial FRAM memory. The
memory array is logically organized as 2,048 x 8 and
is accessed using an industry standard Serial
Peripheral Interface or SPI bus. Functional operation
of the FRAM is similar to serial EEPROMs. The
major difference between the FM25C160 and a serial
EEPROM with the same pin-out relates to its
superior write performance. It also differs from
Ramtron's 25160 by supporting SPI mode 3 and the
industry standard 16-bit addressing protocol. This
makes the FM25C160 a drop-in replacement for most
16Kb SPI EEPROMs that support modes 0 & 3.
Memory Architecture
When accessing the FM25C160, the user addresses
2,048 locations each with 8 data bits. These data bits
are shifted serially. The addresses are accessed using
the SPI protocol, which includes a chip select (to
permit multiple devices on the bus), an op-code and a
two-byte address. The upper 5 bits of the address
range are `don't care' values. The complete address
of 11-bits specifies each byte address uniquely.
Most functions of the FM25C160 either are
controlled by the SPI interface or are handled
automatically by on-board circuitry. The access time
for memory operation essentially is zero, beyond the
time needed for the serial protocol. That is, the
memory is read or written at the speed of the SPI bus.
Unlike an EEPROM, it is not necessary to poll the
device for a ready condition since writes occur at bus
speed. That is, by the time a new bus transaction can
be shifted into the part, a write operation will be
complete. This is explained in more detail in the
interface section below.
Users expect several obvious system benefits from
the FM25C160 due to its fast write cycle and high
endurance as compared with EEPROM. However
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than an EEPROM
since it is completed quickly. By contrast, an
EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.
Note that the FM25C160 contains no power
management circuits other than a simple internal
power-on reset. It is the user's responsibility to
ensure that VDD is within data sheet tolerances to
prevent incorrect operation.
Serial Peripheral Interface SPI Bus
The FM25C160 employs a Serial Peripheral Interface
(SPI) bus. It is specified to operate at speeds up to 5
MHz. This high-speed serial bus provides high
performance serial communication to a host
microcontroller. Many common microcontrollers
have hardware SPI ports allowing a direct interface.
It is quite simple to emulate the port using ordinary
port pins for microcontrollers that do not. The
FM25C160 operates in SPI Mode 0 and 3.
The SPI interface uses a total of four pins: clock,
data-in, data-out, and chip select. It is possible to
connect the two data lines together. Figure 2
illustrates a typical system configuration using the
FM25C160 with a microcontroller that offers an SPI
port. Figure 3 shows a similar configuration for a
microcontroller that has no hardware support for the
SPI bus.
Protocol Overview
The SPI interface is a synchronous serial interface
using clock and data lines. It is intended to support
multiple devices on the bus. Each device is activated
using a chip select. Once chip select is activated by
the bus master, the FM25C160 will begin monitoring
the clock and data lines. The relationship between the
falling edge of /CS, the clock and data is dictated by
the SPI mode. The device will make a determination
of the SPI mode on the falling edge of each chip
select. While there are four such modes, the
FM25C160 supports modes 0 and 3. Figure 4 shows
the required signal relationships for modes 0 and 3.
For both modes, data is clocked into the FM25C160
on the rising edge of SCK and data is expected on the
first rising edge after /CS goes active. If the clock
begins from a high state, it will fall prior to beginning
data transfer in order to create the first rising edge.
The SPI protocol is controlled by op-codes. These
op-codes specify the commands to the part. After /CS
is activated the first byte transferred from the bus
master is the op-code. Following the op-code, any
addresses and data are then transferred.
Certain op-codes are commands with no subsequent
data transfer. The /CS must go inactive after an
operation is complete and before a new op-code can
be issued. There is one valid op-code only per active
chip select.
FM25C160
Rev. 2.1
Aug. 2003
Page 4 of 14
Figure 2. System Configuration with SPI port
Figure 3. System Configuration without SPI port
SPI Mode 0: CPOL=0, CPHA=0
0
1
2
3
4
5
6
7
SPI Mode 3: CPOL=1, CPHA=1
0
1
2
3
4
5
6
7
Figure 4. SPI Modes 0 & 3
FM25C160
Rev. 2.1
Aug 2003
Page 5 of 14
Data Transfer
All data transfers to and from the FM25C160 occur
in 8-bit groups. They are synchronized to the clock
signal (SCK) and they transfer most significant bit
(MSB) first. Serial inputs are clocked in on the rising
edge of SCK. Outputs are driven on the falling edge
of SCK.
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25C160. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, are commands
that have no subsequent operations. They perform a
single function such as to enable a write operation.
Second are commands followed by one byte, either in
or out. They operate on the status register. Last are
commands for memory transactions followed by
address and one or more bytes of data.
Table 1. Op-code Commands
Name Description
Op-code
value
WREN
Set Write Enable Latch
00000110b
WRDI Write
Disable
00000100b
RDSR
Read Status Register
00000101b
WRSR Write
Status
Register
00000001b
READ
Read Memory Data
00000011b
WRITE
Write Memory Data
00000010b
WREN - Set Write Enable Latch
The FM25C160 will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for
write operations. These include writing the status
register and writing the memory.
Sending the WREN op-code causes the internal
Write Enable Latch to be set. A flag bit in the status
register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted. A write
to the status register has no effect on the WEL bit.
Completing any write operation will automatically
clear the write-enable latch and prevent further
writes without another WREN command. Figure 5
below illustrates the WREN command bus
configuration.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the status register and verifying that WEL=0. Figure
6 illustrates the WRDI command bus configuration.
Figure 5. WREN Bus Configuration
Figure 6. WRDI Bus Configuration
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