55490-580-00 A
FibreFAS490
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Features
s
Compliant with the following Fibre Channel (FC)
technology:
Fibre Channel - Arbitrated Loop -2 (FC-AL-2),
T11/Project 1133D/Rev 6.4
Fibre Channel - Private Loop Direct Attach
(FC-PLDA), X3T11/Project 1162DT/Rev. 2.1
Fibre Channel - Fabric Loop Attachment
(FC-FLA), T11/Project 1235-DT/Rev. 2.7
Fibre Channel - Tape (FC-TAPE), NCITS
TR-xx/Project 1315-DT/Rev. 1.07
s
Fibre Channel data rate of 106.25 or 212.5 MBps
s
Full-duplex FC-AL interface manager per port
s
On-chip 8B/10B encode and decode
s
10-bit interface to external transceivers
s
DMA interface data rate of 160 MBps, 200 MBps
using DMACLKO
s
16-bit DMA data path
s
SDRAM buffer sustained bandwidth 350 MBps
(estimated)
s
Table search tool to support sophisticated caching
operations
s
Data protection with buffer CRC (BCRC)
s
Enhanced data streaming support
s
Hardware XOR function at DMA speeds
s
LBA seeder and checker
s
Programmable microcontrollers to automate Fibre
Channel operations
Product Description
The FibreFAS490 controller is part of the QLogic
family of high-performance, low-cost, single-chip
controllers for use in host and peripheral applications. The
FibreFAS490 is designed for use in high-performance
embedded Fibre Channel designs. The FibreFAS490
provides a state of the art high-speed buffer controller, a
direct Fibre Channel interface controller, and a DMA
interface controller
(see figure 1)
.
The FibreFAS490 includes two microcontrollers to
provide users with a flexible, programmable means to
coordinate Fibre Channel sequences.
QLogic Corporation
FibreFAS490 Dual Port Fibre Channel Controller
with Internal Transceivers
Data Sheet
page 4 of 5
FibreFAS490
55490-580-00 A
QLogic Corporation
Product Architecture
Fibre Channel Interface Manager
The Fibre Channel interface manager (FCIM)
implements the FC-AL-2 protocol, including the FC-1 and
FC-2 layers of the signaling interface. The FC-0 layer is
implemented for each port by external serial link
transmitter and receiver modules that connect to the FCIM
through two 10-bit interfaces.
The FCIM includes an 8B/10B encoder and decoder,
an elasticity buffer for clock skew management, and an
FC-AL state machine. The FCIM transmits and receives at
the full Fibre Channel rate of 106.25 MBps.
As specified in the FC-AL protocol, the FCIM uses the
alternate buffer-to-buffer credit model to pace frames. The
FCIM receive path validates and routes frames received
from the Fibre Channel to the appropriate area in the frame
buffer. The transmit path transmits frames from the frame
buffer to the Fibre Channel. The FCIM automatically
handles frame delimiters and frame control.
The FCIM has two onboard transceivers to support
dual-loop configuration; the transceivers connect directly
to the Fibre Channel loop.
Microcontroller
The FibreFAS490 microcontroller supports the
following:
s
Maximum of 26 MIPS (50-ns instruction cycle
except for branch)
s
64 single-word instructions
s
16-bit wide instructions
s
Eight-bit wide data path
s
1024 instruction locations
s
32 general purpose registers
s
32 dual-port mailboxes
s
Five-level deep hardware stack
s
Direct, indirect, absolute, and immediate
addressing modes
s
Two firmware interrupt sources: I0 and I1
s
Two hardware interrupts, one with four-bit
autointerrupt vector and status
s
Full chip access through the microprocessor bus
The microcontroller allows users to automate the
FC-AL and SCSI protocol.
The microcontroller's Harvard architecture improves
performance and flexibility by separating instruction and
data memory. Its pipelined architecture overlaps
instruction fetch and result storage with instruction decode
and execution cycles to provide two-clock instruction
execution and four-clock branch execution. The
microcontroller supports direct, indirect, absolute, and
immediate addressing modes.
The microcontroller has a 16-byte register file,
32 mailbox registers, a five-level deep stack, an integer
ALU, and other special-purpose registers. The
microcontroller has access to its internal registers, the
FC-AL command FIFO, the DRAM buffer, and all registers
within the FibreFAS490. This access provides flexibility
in automating the FibreFAS490 to respond to SCSI
commands.
The microcontroller supports two types of interrupt
schemes: firmware and hardware. The firmware interrupt
allows the external microprocessor to initiate an operation
within the microcontroller without stopping the
microcontroller's current operation. The firmware
interrupt vector can be modified by the microprocessor
while a microcontroller program is running.
Hardware interrupts come directly from the Fibre
Channel module. The microcontroller can be configured to
deliver these interrupts to the microprocessor or to intercept
these interrupts and act on them as part of command
automation. Hardware interrupts handled through the
microcontroller are based on the values of the FCIM
module interrupt and status vector inputs.
Buffer Controller
The FibreFAS490 buffer controller supports the
following:
s
350 MBps total, sustained 32-bit DMA bandwidth
(estimated)
s
Data protection with 32-bit buffer CRC (BCRC)
s
Enhanced data streaming support
s
32-bit, 80-MHz synchronous DRAM (SDRAM)
support
s
Maximum buffer size of 16 MB
s
High-speed buffer memory initialization and
verification to reduce power up initialization
FibreFAS490 buffer management is provided by a
multichannel, high-speed, bursting DMA controller. The
buffer controller provides the connection between the
buffer DRAM and the DMA channel, Fibre Channel, and
microprocessor bus. The buffer controller regulates all data
movement into and out of DRAM buffer memory. Each
DMA channel supports DMA bursting, which allows the
optimal bandwidth to be maintained. Each DMA channel
has associated control, configuration, and buffer memory
address registers.
The buffer controller also provides microprocessor
address decoding, priority arbitration for the buffer
resource, BCRC, and automatic DRAM refresh control.
DMA Interface
The FibreFAS490 has a 16-bit external DMA interface
that supports burst transfer rates greater than 100 MBps.
55490-580-00 A
FibreFAS490
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QLogic Corporation
Microprocessor Interface
The FibreFAS490 samples the DRAM buffer address
signals during power-up reset to configure the
microprocessor operating mode. Power-down (low-power)
mode is controlled by the microprocessor.
The FibreFAS490 connects to the microprocessor as
described below:
s
Multiplexed address/data
10-bit address bus
16-bit data bus
s
Programmable byte ordering
Big endian
Little endian
s
Two interrupts
s
Support for numerous microprocessors, including:
Intel 80186, 80188, 80196
Motorola 68000, 68300, 68020, 68008
TMS320C5X
Hitachi SH1, SH2, SH3
2001 QLogic Corporation. All rights reserved worldwide.
QLogic is a trademark of QLogic Corporation.
Hitachi is a trademark of Hitachi, Ltd.
Intel is a trademark of Intel Corporation.
Motorola is a trademark of Motorola, Inc.
TMS is a trademark of Texas Instruments Incorporated.
All other brand and product names are trademarks or registered trademarks of their respective owners.
QLogic Corporation, 26600 Laguna Hills Drive, Aliso Viejo, CA 92656, (800) 867-7274 or (949) 389-6000
Specifications are subject to change without notice.
April 13, 2001
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