MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

PS11017

FLAT-BASE TYPE

INSULATED TYPE

May 2001

Some parametric limits are subject to change.

LABEL

Terminals Assignment:

115

8.5

15.5

2.5

105

0.5

63.5

0.8

17.5

(102)

(22)

0.5

12.7

0.3

0.5

0.3

0.8

20.4

0.8

0.5

0.8

0.3

15.5

0.3

4-R2

4-R5

4.5

3.2

MOUNTING
HOLE

1 CBU+
2 CBU
3 CBV+
4 CBV
5 CBW+
6 CBW
7 GND
8 NC
9 VDH
10 CL
11 FO1
12 FO2
13 FO3
14 CU
15 CV
16 CW
17 UP
18 VP
19 WP
20 UN
21 VN
22 WN
23 Br

31 P
32 Br
33 N
34 U
35 V
36 W

PS11017

INTEGRATED FUNCTIONS AND FEATURES

· 3-phase IGBT inver ter bridge configured by the latest 3rd.

generation IGBT and diode technologies.

· Circuit for dynamic braking of motor regenerative energy.
· Inverter output current capability I

(Note 1):

PACKAGE OUTLINES

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

PS11017

FLAT-BASE TYPE

INSULATED TYPE

(Note 1) : The inverter output current is assumed to be sinu-

soidal and the peak current value of each of the
above loading cases is defined as : I

= I

(Fig. 1)

Type Name

PS11017

100% load

17.0A (rms)

150% over load

25.5A (rms), 1min

APPLICATION
Acoustic noise-less 3.7kW/AC200V class 3 phase inverter and other motor control applica-
tions.

INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS:

· For P-Side IGBTs : Drive circuit, High voltage isolated high-speed level shifting, Short-circuit protection (SC),

Bootstrap circuit supply scheme (Single drive-power-supply) and Under voltage protection (UV).

· For N-Side IGBTs : Drive circuit, Short circuit protection (SC), Control-supply Under voltage and Over voltage protection (OV/UV), Sys-

tem Over-temperature protection (OT), Fault output (F

) signaling circuit, and Current-Limit warning signal output

(CL)

· For Brake circuit IGBT : Drive circuit
· Warning and Fault signaling :

: Short circuit protection for lower-leg IGBTs and Input interlocking against spurious arm shoot-through.

: N-side control supply abnormality locking (OV/UV)

: System over-temperature protection (OT).

CL : Warning for inverter current overload condition

· For system feedback control : Analogue signal feedback reproducing actual inverter phase current (3

· Input Interface : 5V CMOS/TTL compatible, Schmitt trigger input, and Arm-Shoot-Through interlock protection.

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

PS11017

FLAT-BASE TYPE

INSULATED TYPE

May 2001

Each output IGBT collector current

Brake IGBT collector current

Brake diode anode current

INTERNAL FUNCTIONS BLOCK DIAGRAM

(Fig. 2)

450

500

Applied between P-N

Applied between P-N, Surge-value

Applied between P-U, V, W, Br or U, V, W,
Br-N

= 25

Note: "( )" means I

peak value

Supply voltage

Supply voltage (surge)

CC(surge)

Condition

Symbol

Item

Ratings

Unit

MAXIMUM RATINGS

(Tj = 25

INVERTER PART (Including Brake Part)

or V

P(S)

or V

N(S)

(

)

Each output IGBT collector-emitter static voltage

Each output IGBT collector-emitter
switching surge voltage

600

50 (

100)

15 (30)

VDH

GND

CBU

CBU+

CBV

CBV+

CBW

CBW+

Application Specific Intelligent

Power Module

CU CV CW

CL, FO

, FO

Protection

circuit

Control supply

fault sense

Fo Logic

Drive Circuit

Input signal conditioning

Z : Surge absorber.
C : AC filter (Ceramic condenser 2.2~6.5nF)
[Note : Additionally an appropriate Line-to line
surge absorber circuit may become necessary
depending on the application environment].

AC 200V line
output

AC 200V line input

Brake resistor connection,
Inrush prevention circuit,
etc.

Protection

Circuit

Level shifter

Drive Circuit

Current sensing

circuit

Note 1) To prevent chances of signal oscillation, a series resistor (1k

) coupling at each output is recommended.

Note 2) By virtue of integrating an photo-coupler inside the module, direct coupling to CPU, without any external opto or transformer isolation is possible.
Note 3) All outputs are open collector type. Each signal line should be pulled up to plus side of the 5V power supply with approximately 5.1k

resistance.

Note 4) The wiring between power DC link capacitor and P/N terminals should be as short as possible to protect the ASIPM against catastrophic high surge voltage.
For extra precaution, a small film snubber capacitor (0.1~0.22

F, high voltage type) is recommended to be mounted close to these P and N DC power input pins.

Analogue signal output corresponding to

each phase current (5V line) Note 1)

PWM input

(5V line) Note 2)

Fault output

(5V line) Note 3)

T
S

Applied between V

-GND, C

BU+

-C

BV+

-C

, C

BW+

-C

Applied between U

· V

· W

· U

· V

· Br-GND

Applied between F

· F

-GND

Sink current of F

· F

Applied between CL-GND

Sink current of CL

Sink current of CU · CV · CW

, V

Supply voltage

Symbol

Item

Ratings

Unit

CONTROL PART

Condition

0.5 ~ 7

CIN

Input signal voltage

Fault output supply voltage

Fault output current

Current-limit warning (CL) output voltage

CL output current

Analogue current signal output current

0.5 ~ 7.5

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

PS11017

FLAT-BASE TYPE

INSULATED TYPE

May 2001

LABEL

1.75

2.4

2.9

4.5

0.031

C/W

Junction to case Thermal
Resistance

Condition

Symbol

Item

Ratings

Unit

(Note 2)

(Fig. 3)

60 Hz sinusoidal AC applied between all terminals and
the base plate for 1 minute.

Mounting screw: M4.0

stg

iso

Junction temperature

Storage temperature

Module case operating temperature

Isolation voltage

Mounting torque

20 ~ +125

40 ~ +125

20 ~ +100

2500

0.98 ~ 1.47

Vrms

N·m

TOTAL SYSTEM

Note 2) The item defines the maximum junction temperature for the power elements (IGBT/Diode) of the ASIPM to ensure safe operation. How-

ever, these power elements can endure instantaneous junction temperature as high as 150

C instantaneously . To make use of this ad-

ditional temperature allowance, a detailed study of the exact application conditions is required and, accordingly, necessary information
is requested to be provided before use.

Condition

Symbol

Item

Ratings

Inverter IGBT (1/6)

Inverter FWDi (1/6)

Brake IGBT

Brake FWDi

Case to fin, thermal grease applied

Rth(j-c)

Rth(c-f)

Min.

THERMAL RESISTANCE

Typ.

Max.

Unit

(Fig. 3)

CASE TEMPERATURE MEASUREMENT POINT (3mm from the base surface)

Contact Thermal Resistance

Circuit current

Input on threshold voltage

Input off threshold voltage

Input pull-up resister

Min.

FBr

ton

tc(on)

toff

tc(off)

trr

Collector-emitter saturation voltage

FWDi forward voltage

CE(sat)

Ratings

= V

= 15V, Input = ON, Tj = 25

C, Ic = 50A

Condition

Symbol

Item

Typ.

Max.

Unit

· No destruction
· F

output by protection operation

ELECTRICAL CHARACTERISTICS

(Tj = 25

C, V

= 15V, V

= 15V unless otherwise noted)

Tj = 25

C, Ic = 50A, Input = OFF

th(on)

th(off)

· No destruction
· No protecting operation
· No F

output

CE(sat)Br

Brake IGBT
Collector-emitter saturation voltage

Brake diode forward voltage

= 15V, Input = ON, Tj = 25

C, Ic = 15A

Tj = 25

C, I

= 15A, Input = OFF

Switching times

1/2 Bridge inductive, Input = ON

= 300V, Ic = 50A, Tj = 125

= 15V, V

= 15V

Note : ton, toff include delay time of the internal control

circuit

FWD reverse recovery time

Short circuit endurance

(Output, Arm, and Load,

Short Circuit Modes)

400V, Input = ON (one-shot)

Tj = 125

C start

13.5V

= V

16.5V

400V, Tj

125

Ic < I

(CL) operation level, Input = ON,

13.5V

= V

16.5V

Switching SOA

= 15V, V

CIN

= 5V

0.8

2.5

Integrated between input terminal-V

0.40

1.5

1.4

3.0

150

0.8

0.15

0.6

2.9
2.9

3.5

1.0

2.4

150

2.0

4.0

2.9

2.0

1.3

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

PS11017

FLAT-BASE TYPE

INSULATED TYPE

May 2001

10.0

16.50

18.00

11.55

d(read)

CL(H)

CL(L)

OTr

DHr

DBr

FO(H)

FO(L)

0.77

ELECTRICAL CHARACTERISTICS

(Tj = 25

C, V

= 15V, V

= 15V unless otherwise noted)

3.37

Idle

Active

Trip level

Reset level

Trip level

Reset level

Trip level

Reset level

Trip level

Reset level

Filter time

Idle
Active

Ic = 0A

Ic = I

(200%)

Ic = I

(200%)

int

C+

(200%)

C+

(200%)

= 20 ~ +100

125

= 15V

= 20

C ~ 100

(Fig. 4)

100

C, Tj

125

= 15V, T

= 20

C ~ +100

(Note 3)

PWM input frequency

Condition

Symbol

Ratings

PWM

Min.

Typ.

Max.

Unit

= 15V, T

= 20

C ~ 100

Ic > I

(200%), V

= 15V

(Fig. 4)

-V

(200%)|

After input signal trigger point

(Fig. 8)

Fault output current

Open collector output

= 15V, T

= 20

C ~ 100

(Note 4)

Tj = 25

(Fig. 7) (Note 5)

Analogue signal over all linear variation

Item

dead

Allowable input on-pulse width
Allowable input signal dead time for
blocking arm shoot-through

Relates to corresponding input (Except break part)

Analogue signal linearity with output current

Offset change area vs temperature

Analogue signal output voltage limit

Analogue signal data hold accuracy

Analogue signal reading time

Correspond to max. 500

s data hold period

only, Ic = I

(200%)

(Fig. 5)

CL warning operation level

Short circuit over current trip level

2.5

1.87

4.0

48.2

79.2

100

11.05

Open collector output

--
--

2.27

1.17

1.1

60.0

102

110

11.0

12.00

12.50

19.20

500

100

2.57

1.47

3.67

0.7

72.0

120

12.0

12.5

12.75

13.25

20.15

18.65

kHz

V
V

17.50

Relates to corresponding inputs,
(Except brake part), T

= 20

C ~ +100

Input inter-lock sensing

2.97

Signal output current of
CL operation

Over temperature
protection

Supply circuit under &
over voltage protection

11.5

10.5

= 15V

(Note 3) : (a) Allowable minimum input on-pulse width : This item applies to P-side circuit only.

(b) Allowable maximum input on-pulse width : This item applies to both P-side and N-side circuits excluding the brake circuit.

(Note4) : CL output : The "current limit warning (CL) operation circuit outputs warning signal whenever the arm current exceeds this limit. The

circuit is reset automatically by the next input signal and thus, it operates on a pulse-by-pulse scheme.

(Note5) : The short circuit protection works instantaneously when a high short circuit current flows through an internal IGBT rising up momen-

tarily. The protection function is, thus meant primarily to protect the ASIPM against short circuit distraction. Therefore, this function is
not recommended to be used for any system load current regulation or any over load control as this might, cause a failure due to
excessive temperature rise. Instead, the analogue current output feature or the over load warning feature (CL) should be appropri-
ately used for such current regulation or over load control operation. In other words, the PWM signals to the ASIPM should be shut
down, in principle, and not to be restarted before the junction temperature would recover to normal, as soon as a fault is feed back
from its F

pin of the ASIPM indicating a short circuit situation.

Supply voltage ripple

Input on voltage

Input off voltage

PWM Input frequency

Arm shoot-through blocking time

Supply voltage

CIN(on)

CIN(off)

PWM

dead

RECOMMENDED CONDITIONS

400 (max.)

Applied across P-N terminals

Condition

Symbol

Item

Ratings

Unit

, V

Control Supply voltage

Applied between V

-GND, C

BU+

-C

, C

BV+

-C

BW+

-C

Using application circuit

1.5

1 (max.)

0 ~ 0.3

4.8 ~ 5.0

2 ~ 15

2.5 (min.)

kHz

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

PS11017

FLAT-BASE TYPE

INSULATED TYPE

May 2001

delay time

Short circuit sensing signal V

Error output F

Gate signal Vo of each phase
upper arm(ASIPM internal)

Input signal V

CIN

of each phase

upper arm

Input signal V

CIN(p)

of each phase upper arm

Input signal V

CIN(n)

of each phase lower arm

Gate signal V

o(p)

of each phase upper arm

(ASIPM internal)

Gate signal V

o(n)

of each phase upper arm

(ASIPM internal)

Error output F

200

Analogue output signal

data hold range

400

300

100

300

400

+(200%)

(200%)

(V)

min

max

Real load current peak value.(%)(I

=15V

100°C

(Fig. 4)

Fig. 4 OUTPUT CURRENT ANALOGUE SIG-

NALING LINEARITY

Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING

"DATA HOLD" DEFINITION

Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART

Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta-

neously in "LOW" level.

By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and "F

" signal is outputted. After an "input

interlock" operation the circuit is latched. The "F

" is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input,

whichever comes in later.

Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION

Note : Short circuit protection operation. The protection operates with "F

" flag and reset on a pulse-by-pulse scheme. The protection by

gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the "Brake").

(505

500

(505

s)-V

Note ; Ringing happens around the point where the signal output
voltage changes state from "analogue" to "data hold" due
to test circuit arrangement and instrumentational trouble.
Therefore, the rate of change is measured at a 5

s delayed point.

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