RM5231A/5261A
64-Bit MIPS RISC Microprocessor with 32/64-Bit System Bus
PMC- 2010740 (R1)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
Copyright PMC-Sierra, Inc. 2000
FEATURES
Dual-Issue 64-bit Superscalar
architecture
High-performance 64-bit integer unit
High-throughput fully pipelined 64-
bit floating point unit (IEEE754)
High performance SysAD interface
32-bit or 64-bit multiplexed system
address/data bus for optimum
price/performance
Available with 32-bit or 64-bit
external bus interface
Supports fractional clock ratios
IEEE 1149.1 JTAG boundary scan
Integrated primary caches
32KB instruction - 2-way set
associative
32KB data - 2-way set associative
Virtually indexed, physically tagged
Write-back and write-through on
per-page basis
Pipeline restart on first double word
for data cache misses
64-bit MIPS instruction set architecture
Floating point multiply-add
instruction increases performance in
signal processing and graphics
applications
Conditional moves to reduce branch
frequency
Index address modes (register +
register)
Integrated memory management
Fully associative joint TLB (shared
by I and D transistors)
48 dual entries map 96 pages
Variable page size (4KB to 16MB)
Embedded application enhancements
Specialized DSP integer Multiply-
Accumulate instructions
(MAD/MADU) and 3 operand
Multiply instruction (MUL)
Instruction and Data cache locking
by set
Optional dedicated exception vector
for interrupts
BLOCK DIAGRAM
64-bit Integer unit
Dual-Issue
Superscalar
64-bit FP Unit
Double / Single
IEEE 754
Integer Multiplier / Accum.
D-Cache 32KB, 2-
way, lockable
I-Cache 32KB,
2-way, lockable
System Control
PC Unit
MMU 96 Pages,
(4KB 16 MB)
Bus Interface Unit
Instr. Dispatch
SysA / D Bus
32-bit (5231A)
64-bit (5261A)
NMI, INT5 INT0
Int Ctlr
Device
CPU
Frequency
(MHz)
I/D
Cache
External
Cache
Support
External Bus
Width
External Bus
Frequency
(MHz)
VccInt
(V)
VccIO
(V)
Package
RM5231A
250, 300, 350
32K/32K
No
32-bit
100
1.65/1.8
2.5/3.3
128 QFP
RM5261A
250, 300, 350
32K/32K
No
64-bit
125
1.65/1.8
2.5/3.3
208 QFP
Head Office:
PMC-Sierra, Inc.
8555 Baxter Place
Burnaby, B.C. V5A 4V7
Canada
Tel: 604.415.6000
Fax: 604.415.6200
64-Bit MIPS RISC Microprocessor with 32/64-Bit System Bus
To order documentation,
send email to:
document@pmc-sierra.com
or contact the head office,
Attn: Document Coordinator
PMC- 2010740 (R1)
Copyright PMC-Sierra, Inc. 2001. All
rights reserved. RM5231A/and RM 5261A
are trademarks of PMC-Sierra Inc.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RM5231A/5261A
All product documentation is available
on our web site at:
http://www.pmc-sierra.com
For corporate information,
send email to:
info@pmc-sierra.com
DEVELOPMENT TOOLS
Operating Systems:
Linux by MontaVista and Red Hat
VxWorks by Wind River Systems
Nucleus by Accelerated Technology
Neutrino by QNX Software Systems
Compiler Suites
Algorithmics
Green Hills Software
Red Hat
Evaluation Boards and Companion
Chips
Algorithmics:
P-6032 (RM5231A): 32-bit,
33MHz PCI
P-4052 (RM5231A): 32-bit,
33MHz PCI
Galileo Technology
EV-64120A: (RM5261A): 32/64-
bit, 33/66MHz PCI
EV-64115 (RM5231A): 32-bit,
33/66MHz PCI
V3 Semiconductor
V320USC (RM5231A): 32-bit,
50MHz PC
V340HPC (RM5261A): 64-bit,
66MHz PCI
Logic Analyzers and Emulation
HP
Tektronix
Corelis
Crescent Heart Software
Marvell/Galileo
PCI Bus
SDRAM
Devices
GT-64120
64/32/16/8-bit
64/32-bit
SCSI
Network
PCI to
PCI
Bridge
Other
Data
64/32-bit
Address &
Control
SysAD 64/32-bit
L3 Cache
(Optional)
RM52XX
64/32-bit
64/32-bit
TYPICAL APPLICATION
PDF 
ZIP