Document Outline

• Product Overview
• 1 System Applications
  • 1.1 QRT System Overview
  • 1.2 622 Mbps Switch Configuration
  • 1.3 32 x 32 Switch Application (5 Gbps)
  • 1.4 64 x 64 Switch Application (10 Gbps)
  • 1.5 5 Gbps to 20 Gbps Application Example - Seamless Growth
  • 1.6 5 Gbps to 160 Gbps Application Example � LAN-to-WAN
• 2 Theory of Operations
  • 2.1 Overview
  • 2.2 Interface Descriptions
    • 2.2.1 Switch Fabric Interface
    • 2.2.2 Phase Aligners
    • 2.2.3 UTOPIA Interface
    • 2.2.4 Cell Buffer SDRAM Interface
    • 2.2.5 Channel RAM (CH_RAM) Interface
    • 2.2.6 Address Lookup RAM (AL_RAM) Interface
    • 2.2.7 AB_RAM Interface
    • 2.2.8 Host Processor Interface
    • 2.2.9 SE_SOC Encodings
    • 2.2.10 BP_ACK Encodings
    • 2.2.11 Relation Between External CELL_START and Local CELL_START
  • 2.3 Cell Flow Overview
  • 2.4 UTOPIA Operation
    • 2.4.1 General
    • 2.4.2 UTOPIA Interface
      • 2.4.2.1 UTOPIA Level 2 Polling
        • 2.4.2.1.1 Standard Single Cell Available Polling
        • 2.4.2.1.2 Multiplexed Status Polling (MSP) Using Four Cell Available Signals
        • 2.4.2.1.3 Direct Status Indication Using Four Cell Available Signals
      • 2.4.2.2 Priority Encoding and TDM Table
        • 2.4.2.2.1 Basic 2 Level Priority Algorithm
        • 2.4.2.2.2 TDM and the Basic 2 Level Priority Algorithm
      • 2.4.2.3 Independently Configurable Interfaces
      • 2.4.2.4 Output Channel Number Insertion
  • 2.5 Receiver Operation
    • 2.5.1 Receive Channel Lookup
    • 2.5.2 Receive VC (Channel) Queuing
    • 2.5.3 Receive Channel Ring
    • 2.5.4 Receive Congestion Management
    • 2.5.5 Receive Queue Service Algorithm
    • 2.5.6 Receive Sequencing Algorithm
  • 2.6 Transmitter Operation
    • 2.6.1 Transmit Queuing
    • 2.6.2 Transmit Congestion Management
    • 2.6.3 Transmit Queue Service Algorithm
    • 2.6.4 Transmit Resequencing Algorithm
    • 2.6.5 Transmit Recovery Algorithm
    • 2.6.6 Transmit Multicast Cell Background Process
    • 2.6.7 Transmit Multicast Congestion Management
  • 2.7 System Diagram of Internal QRT Blocks and External RAM
• 3 Fault Tolerance
  • 3.1 The Data Path
    • 3.1.1 UTOPIA Interface
    • 3.1.2 Switch Fabric Interface
  • 3.2 Fault Detection and Isolation
    • 3.2.1 Memory Parity Checking
    • 3.2.2 UTOPIA Interface Fault Detection and Recovery Mechanisms
      • 3.2.2.1 Header Error Check (HEC)
      • 3.2.2.2 Start Of Cell (SOC) Recovery
      • 3.2.2.3 Transmit Watchdog
      • 3.2.2.4 Transmit Parity
      • 3.2.2.5 ATM Clock Failure Detection
      • 3.2.2.6 Receive Cell Available Signal Stuck at 1
      • 3.2.2.7 Highest Bandwidth Device Support in UTOPIA Level 2 Mode
    • 3.2.3 Switch Fabric Fault Detection and Recovery Mechanisms
      • 3.2.3.1 SOC Coding
      • 3.2.3.2 SOC Inversions
      • 3.2.3.3 Redundant Cell Present Coding
      • 3.2.3.4 Idle Cell Pattern Checking
      • 3.2.3.5 Dropping Cells with Bad Header Parity
      • 3.2.3.6 Forced Bad Parity
      • 3.2.3.7 Marked Cell Counting
      • 3.2.3.8 Remote Data Path Failure Indication
      • 3.2.3.9 Unacknowledged Cell Detection
      • 3.2.3.10 Switch Fabric Loopback
      • 3.2.3.11 Fabric Clock Failure Detection
      • 3.2.3.12 Liveness of Backpressure Signal
      • 3.2.3.13 BP_ACK_IN Pattern Checking
      • 3.2.3.14 BP_ACK Inversion Checking
      • 3.2.3.15 BP_ACK Remote Failure Detection
      • 3.2.3.16 Detection Hysteresis
    • 3.2.4 Tables of Switch Fabric Interface Failure Behaviors
      • 3.2.4.1 IRT-to-Switch Fabric Interface
      • 3.2.4.2 QSE Interface, Receive Data Direction
      • 3.2.4.3 QSE Interface, Transmit Data Direction
      • 3.2.4.4 Switch Fabric-to-ORT Interface
      • 3.2.4.5 Types of Failures and Their Manifestations
• 4 Pin Descriptions
  • 4.1 Package Diagram
  • 4.2 Signal Locations
  • 4.3 Signal Descriptions (372 Signal Pins)
    • 4.3.1 Processor Interface Signals
    • 4.3.2 Statistics Interface Signal
    • 4.3.3 Switch Element Interface Signals
    • 4.3.4 CH_RAM Interface Signals
    • 4.3.5 AL_RAM Interface Signals
    • 4.3.6 ABR_RAM Interface Signals
    • 4.3.7 Receive Cell Buffer DRAMs
    • 4.3.8 Transmit Cell Buffer DRAMs
    • 4.3.9 UTOPIA ATM Layer Interface Signals
      • 4.3.9.1 Transmit UTOPIA ATM Layer Interface Signals
      • 4.3.9.2 Receive UTOPIA ATM Layer Interface Signals
    • 4.3.10 Boundary Scan Signals
    • 4.3.11 Miscellaneous Signals
• 5 Physical Characteristics
• 6 Timing Diagrams
  • 6.1 UTOPIA Timing
  • 6.2 DRAM External Memory Timing
  • 6.3 SRAM Timings
  • 6.4 QRT-QSE Interface Timing
    • 6.4.1 Switch Fabric Cell Formats
  • 6.5 Processor Interface Timing
  • 6.6 Miscellaneous Timing
• 7 Microprocessor Ports
  • 7.1 Microprocessor Ports Summary
  • 7.2 Microprocessor Ports Bit Definitions
    • 7.2.1 REVISION
    • 7.2.2 RESET
    • 7.2.3 TEST_CONFIG
    • 7.2.4 SRAM_CONFIG
    • 7.2.5 SWITCH_CONFIG
    • 7.2.6 RAM BIST RESULT
    • 7.2.7 MARKED_CELLS_COUNT
    • 7.2.8 CONDITION_PRES_BITS
    • 7.2.9 CONDITION_LATCH_BITS
    • 7.2.10 INTR_MASK
    • 7.2.11 UTOPIA_CONFIG
    • 7.2.12 UT_PRIORITY
    • 7.2.13 UT_ENABLE
    • 7.2.14 TX_UT_STAT
    • 7.2.15 TX_UT_WD_ALIVE
    • 7.2.16 RX_CELL_START_ALIGN (Internal Structure)
    • 7.2.17 RX_QUEUE_ENGINE_TEST
    • 7.2.18 TX_QUEUE_ENGINE_TEST
    • 7. 2. 19. QUEUE ENGINE CONDITION_PRES_BITS
    • 7. 2. 20. QUEUE_ENGINE_CONDITION_LATCH_BITS
    • 7. 2. 21. QUEUE_ENGINE_INT_MASK
    • 7.2.22 RX_DIR_CONFIG
    • 7.2.23 RX_DIR_STATE (Internal Structure)
    • 7.2.24 TX_DIR_CONFIG
    • 7.2.25 TX_DIR_STATE (Internal Structure)
    • 7.2.26 RX_SENT_CELLS
    • 7.2.27 RX_DROPPED_CELLS
    • 7.2.28 TX_SENT_CELLS
    • 7.2.29 TX_DROPPED_CELLS
    • 7. 2. 30. RX_LOWER16_SCG_CONFIG
    • 7. 2. 31. RX_LOWER16_SCG_STATE (Internal State)
    • 7. 2. 32. RX_LOWER32_SCG_CONFIG
    • 7. 2. 33. RX_LOWER32_SCG_STATE (Internal State)
    • 7. 2. 34. RX_LOWER48_SCG_CONFIG
    • 7. 2. 35. RX_LOWER48_SCG_STATE (Internal State)
    • 7. 2. 36. TX_LOWER4_SCG_CONFIG
    • 7. 2. 37. TX_LOWER4_SCG_STATE (Internal State)
    • 7. 2. 38. TX_LOWER8_SCG_CONFIG
    • 7. 2. 39. TX_LOWER8_SCG_STATE (Internal State)
    • 7. 2. 40. TX_LOWER12_SCG_CONFIG
    • 7. 2. 41. TX_LOWER12_SCG_STATE (Internal State)
• 8 Internal RAM Memory Map
  • 8.1 Internal RAM Summary
  • 8.2 Transmit Service Class RAM (TSC_RAM) Summary
    • 8.2.1 Transmit Service Class Queue (TX SCQ) Control Block
      • 8.2.1.1 TX_SCQ_CONFIG
      • 8.2.1.2 TX_SCQ_STATE (Internal Structure)
      • 8.2.1.3 TX_SCQ_HEAD/TX_SCQ_OUT_FIFO_HEAD (Internal Structure)
      • 8.2.1.4 TX_SCQ_TAIL/TX_SCQ_OUT_FIFO_TAIL (Internal Structure)
  • 8.3 Receive Service Class RAM (RSC_RAM) Summary
    • 8.3.1 Receive Service Class (RX SC) Control Block
      • 8.3.1.1 RX_SC_CONFIG
      • 8.3.1.2 RX_SC_STATE (Internal Structure)
      • 8.3.1.3 RX_SC_CUR_CHAN (Internal Structure)
      • 8.3.1.4 RX_SC_PREV_CHAN (Internal Structure)
      • 8.3.1.5 RX_SC_CH_COUNT (Internal Structure)
  • 8.4 Virtual Output Control RAM (VO_RAM) Summary
    • 8.4.1 Transmit VO Control Block
      • 8.4.1.1 TX_VO_CONFIG
      • 8.4.1.2 TX_VO_STATE (Internal Structure)
      • 8.4.1.3 TX_VO_CELLS_PRES (Internal Structure)
      • 8.4.1.4 TX_VO_SERVICE_STATE_0 (Internal Structure)
      • 8.4.1.5 TX_VO_SERVICE_STATE_1 (Internal Structure)
    • 8.4.2 Transmit SC Control Block
      • 8.4.2.1 TX_SC_CONFIG
      • 8.4.2.2 TX_SC_STATE (Internal Structure)
    • 8.4.3 Transmit Multicast SC Control Block Summary
      • 8.4.3.1 TX_SC_MC_IN_FIFO_HEAD (Internal Structure)
      • 8.4.3.2 TX_SC_MC_IN_FIFO_TAIL (Internal Structure)
      • 8.4.3.3 TX_SC_MC_BOTTLE (Internal Structure)
      • 8.4.3.4 TX_SC_MC_NEXT_HEADER_PTR (Internal Structure)
  • 8.5 Receive Switch Fabric Control RAM (RSF_CONTROL) Summary
    • 8.5.1 RX_RSF_CONFIG (Internal Structure)
    • 8.5.2 RX_RSF_TAG (Internal Structure)
    • 8.5.3 RX_RSF_NEW_VPI_VCI (Internal Structure)
    • 8.5.4 RX_RSF_SN_CHAN (Internal Structure)
    • 8.5.5 RX_RSF_ER_CELL_PTR (Internal Structure)
  • 8.6 Transmit Switch Fabric Control RAM (TSF_CONTROL_RAM) Summary
    • 8.6.1 TX_TSF_SN_CHAN (Internal Structure)
  • 8.7 Test Access to the Receive UTOPIA RAM (RU_RAM)
  • 8.8 Test Access to the Transmit UTOPIA RAM (TU_RAM)
  • 8.9 Test Access to Receive Switch Element RAM (RS_RAM)
  • 8.10 Test Access to Transmit Swith Element RAM (TS_RAM)
• 9 External RAM Memory Map
  • 9.1 External RAM Summary
  • 9.2 Address Lookup RAM (AL_RAM)
    • 9.2.1 VI_VPI_TABLE
    • 9.2.2 VCI_TABLE
    • 9.2.3 Multicast Cell Instance Control Block (Internal Structure)
      • 9.2.3.1 MC_HEADER_PTR (Internal Structure)
      • 9.2.3.2 MC_CELL_PTR (Internal Structure)
    • 9.2.4 RX_NEXT_CELL (Internal Structure)
    • 9.2.5 Transmit Cell Buffer Control Block (Internal Structure)
    • 9.2.6 Service Order Control Block (Internal Structure)
      • 9.2.6.1 TX_SERVICE_TABLE
      • 9.2.6.2 RX_SERVICE_TABLE
  • 9.3 Channel RAM (CH_RAM)
    • 9.3.1 Channel Control Block
      • 9.3.1.1 RX_CH_CONFIG
      • 9.3.1.2 RX_CH_TAG
      • 9.3.1.3 RX_CH_NEW_VPI_VCI
      • 9.3.1.4 RX_CH_STATE (Internal Structure)
      • 9.3.1.5 RX_CH_NEXT_CH/RX_CH_SEQ_PTR1 (Internal Structure)
      • 9.3.1.6 RX_CH_SEQ_ST (Internal Structure)
      • 9.3.1.7 TX_CH_CONFIG
      • 9.3.1.8 TX_NEW_VPI_RESEQ_PTR
      • 9.3.1.9 TX_CH_STATE (Internal Structure)
      • 9.3.1.10 TX_CH_RESEQ_ST
      • 9.3.1.11 TX_CH_CELLS_SENT
      • 9.3.1.12 TX_CH_CELLS_DRPD
    • 9.3.2 Multicast Control Block
      • 9.3.2.1 MC_LIST
      • 9.3.2.2 MC_NEW_VPI_VCI
  • 9.4 ABR_RAM
    • 9.4.1 Receive Channel Queue Block
      • 9.4.1.1 RX_CH_HEAD (Internal Structure)
      • 9.4.1.2 RX_CH_TAIL (Internal Structure)
    • 9.4.2 Receive Channel Statistics Block
      • 9.4.2.1 RX_CH_SENT (Internal Structure)
      • 9.4.2.2 RX_CH_DROPPED (Internal Structure)
  • 9.5 SDRAM/SGRAM Interface Description
    • 9.5.1 RX_DRAM_REGISTER
    • 9.5.2 TX_DRAM_REGISTER
    • 9.5.3 Receive Cell Buffer SDRAM/SGRAM Summary (Internal Structure)
    • 9.5.4 Transmit Cell Buffer SDRAM/SGRAM Summary (Internal Structure)
• 10 JTAG
• 11 Application Notes
  • 11.1 Connecting QRTs to QSEs Using Gigabit Ethernet Transceivers
  • 11.2 Connecting to Standard Serializer/Deserializer Chipsets
  • 11.3 Connecting the QRT to the S/UNI-ATLAS PM7324
  • 11.4 Relationships Among Various Clock Domains
    • 11.4.1 Relationship Among the SYSCLK, SE_CLK, and the Switch Speed-Up Factor
    • 11.4.2 The Phase Aligner SE_CLK Frequency Constraint
    • 11.4.3 The SYSCLK DRAM Refresh Constraint
    • 11.4.4 Relationship Between ATM_CLK and SYSCLK
    • 11.4.5 Relationship Between the PCLK and the SYSCLK
• Appendix A Nomenclature
  • A.1 Definitions
  • A.2 Signal Name Prefixes
  • A.3 Numbers
  • A.4 Glossary of Abbreviations
• Appendix B References
• Appendix C RAM SELECTION