RELEASED
PM73122 AAL1GATOR-32
DATASHEET
PMC-1981419
ISSUE 7
32 LINK CES/DBCES AAL1 SAR PROCESSOR
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
PM73122
AAL1GATOR-32
ATM ADAPTATION LAYER 1
SEGMENTATION AND REASSEMBLY
PROCESSOR-32
DATASHEET
PROPRIETARY AND CONFIDENTIAL
RELEASED
ISSUE 7: JUNE 2001
RELEASED
PM73122 AAL1GATOR-32
DATASHEET
PMC-1981419
ISSUE 7
32 LINK CES/DBCES AAL1 SAR PROCESSOR
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
i
REVISION HISTORY
Issue
No.
Issue Date
Details of Change
1
Dec 1998
Document created.
2
Sept 1999
Significant design details added.
3
Nov 1999
Further design details and pinout added.
4
Jan 2000
Updated to reflect functional details based on latest design. Clarified and added further
descriptive text. Finalized pinout.
5
May 2000
Added description of the floating CAS nibble capability. (SHIFT_CAS). Added more functional
detail.
RELEASED
PM73122 AAL1GATOR-32
DATASHEET
PMC-1981419
ISSUE 7
32 LINK CES/DBCES AAL1 SAR PROCESSOR
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
ii
Issue
No.
Issue Date
Details of Change
6
May 2001
Added section: Changes from Rev B to Rev C.
Added "BUSMASTER" bit in SBI_BUS_CFG_REG, along with description.
Clarified NODROP_IN_START and DROPPED_CELL counter functionality is that
NODROP_IN_START has no effect for ROBUST SN Processing and UDF-HS mode.
In LIN_STR_MODE added cross reference to HS Operations section for Dual DS3 mode.
Corrected "Out of Band Signaling Idle Detection" section with respect to RX and TX CAS.
Fixed Robust SN processing Figure.
Added note in SN PROCESSING register to clarify that only ROBUST_SN_EN or DISABLE_SN
can be set, not both.
Only SBI mapping ram has 2 pages not SBI control RAM.
Sometimes An_SW_RESET needs to be used with high speed queue. Updated Operations
section and An_SW_RESET description.
Added times when OFFSET needs to be set to FRAMES_PER_CELL in OFFSET bit description.
Clarified MVIP-90 configuration in the Operations section
Changed DC_INT from link to tributary.
Flipped HIZDATA and HIZIO.
In DC Characteristics, made operating current for I/O typical, added .5 ns margin to C1FP hold
and SBI Tz. Also applied C1FP timing to C1FP_ADD also.
Default value corrected for MIN_DEPTH for DS3 Register.
Clarified and/or corrected "INSBI/EXSBI Programming Steps" section, "SBI Operation" section,
tributary mapping sequences in "Programming Sequence for SBI" section and lack of depth check
support in SBI Synchronous Mode.
Added statements describing that UDF_HS Loopback Mode requires that the High Speed Queue
be reset, that SPE Activation Must Occur After Tributaries are Enabled, that SPE Activation must
occur after tributaries are enabled.
Updated applications section with new PMC devices: PM8316 TEMUX-84, PM7341 S/UNI-IMA-
84.
RELEASED
PM73122 AAL1GATOR-32
DATASHEET
PMC-1981419
ISSUE 7
32 LINK CES/DBCES AAL1 SAR PROCESSOR
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
iii
Issue
No.
Issue Date
Details of Change
7
June 2001
Changed DC_INT_EN to SYNC_INT_EN in operations section.
In DC Characteristics, corrected IDDOP(2.7) for HS mode.
In Operations section, clarified function of SBI Parity Error Detection and recommended setting
the BUSMASTER bit in the PHY SBI device.
Added note at beginning of AC Characteristics recommending that transition times on clock inputs
is less than 15 ns.
Corrected Ram Interface Timing
In Memory Mapped Register Section added CSD_BYTES_LEFT register definition in
T_QUEUE_TABLE. Added hidden bits in QUE_CREDITS word and added
R_DBCES_BM_IN_NEXT to R_TOT_LEFT memory register and changed
R_DBCES_BM_IN_NEXT bit to R_DBCES_BM_INACT in R_STATE_0 memory register.
Clarified C1FP signal definition in SBI Signal Definition section.
Changed "Out of Band" idle detection mode to "Processor Controlled" idle detection mode in Idle
Detection section of Functional Description.
Updated PCR section in Functional Description
Added SRTS patent legal note to footer of last page
Corrected T1/E1 Link Rate Table (reversed polarity of C1FP)
Corrected cross reference in ADD QUEUE FIFO section
Removed equations from partial cell PCR section and replaced with summary table.
Added reference by RL_CLK that clock can not be gapped and must have jitter less than .3 UI if
using SRTS.
Added minor clarifications, including: R_LINE_STATE location not used in UDF-HS mode,
explanation of PCR for UDF-ML, removed references to E3 over SBI, added recommendation to
tie unused TL_CLK pins high in UDF-HS modes, renamed RPHY_ADD_RSX pin to
RPHY_ADD[4]/RSX to match Tx side, removed `sampled on rising edge' from ADETECT pin
description, added that PAGE bit is a don't care when accessing SBI Control RAM's, clarified max
RSTB timing and max 400 SYSCLK rd/wr timing, clarified T1/E1 granularity in SBI mode(at
DA1SP level), E1_w_T1_sig mode not supported over SBI, clarified that SN state machines
freeze during underruns.
RELEASED
PM73122 AAL1GATOR-32
DATASHEET
PMC-1981419
ISSUE 7
32 LINK CES/DBCES AAL1 SAR PROCESSOR
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
iv
CONTENTS
1
CHANGES FROM REV. A TO REV. B ..................................................... 1
2
CHANGES FROM REV B TO REV C ...................................................... 2
3
FEATURES .............................................................................................. 3
4
APPLICATIONS ....................................................................................... 9
5
REFERENCES....................................................................................... 10
6
APPLICATION EXAMPLES ....................................................................11
6.1
ATM MULTI-SERVICE SWITCH ..................................................11
6.2
PASSIVE OPTICAL NETWORK (PON) SYSTEM....................... 12
6.3
DIGITAL ACCESS CROSS-CONNECT SYSTEM (DACS) WITH AN
ATM INTERFACE........................................................................ 13
7
BLOCK DIAGRAM ................................................................................. 14
8
DESCRIPTION ...................................................................................... 15
9
PIN DIAGRAM ....................................................................................... 16
10
PIN DESCRIPTION................................................................................ 17
10.1 UTOPIA INTERFACE SIGNALS (52) .......................................... 17
10.2 MICROPROCESSOR INTERFACE SIGNALS (43)..................... 26
10.3 RAM 1 INTERFACE SIGNALS(41) ............................................. 28
10.4 LINE INTERFACE SIGNALS(DIRECT LOW SPEED)(132) ........ 31
10.5 LINE INTERFACE SIGNALS(H-MVIP)(37) ................................. 36
10.6 SBI INTERFACE SIGNALS (ONLY USED IN SBI MODE)(64).... 38
10.7 LINE INTERFACE SIGNALS(HIGH SPEED)(10)........................ 45
10.8 RAM 2 INTERFACE SIGNALS (ONLY USED IN H-MVIP, HS, AND
SBI MODES)(41)......................................................................... 46
PDF 
ZIP