Document Outline

TITLE PAGE
REVISION HISTORY
CONTENTS
LIST OF REGISTERS
LIST OF FIGURES
LIST OF TABLES
FEATURES
APPLICATIONS
REFERENCES
DEFINITIONS
APPLICATION EXAMPLES
BLOCK DIAGRAM
DESCRIPTION
PIN DIAGRAM
PIN DESCRIPTION
- Line Side Interface Signals
- Section and Line Status Docs Signals
- ATM (Utopia) & Packet Over Sonet (POS-PHY) System Interface
- Microprocessor Interface Signals
- JTAG Test Access Port (TAP) Signals
- Analog Signals
- Power and Ground
FUNCTIONAL DESCRIPTION
- Receive Line Interface (CRSI)
  - Clock Recovery
  - Serial to Parallel Converter
- Receive Section Overhead Processor (RSOP)
  - Framer
  - Descramble
  - Data Link Extract
  - Error Monitor
  - Loss of Signal
  - Loss of Frame
- Receive Line Overhead Processor (RLOP)
  - Line RDI Detect
  - Lline AIS Detect
  - Data Link Extract Block
  - Error Monitor Block
- The Receive Aps, Synchronization, Extractor and Bit Error Monitor (RASE)
  - Automatic Protection Switch Control
  - Bit Error Rate Monitor
  - Synchronization Status Extraction
- Receive Path Overhead Processor (RPOP)
  - Pointer Interpreter
  - SPE Timing
  - Error Monitor
- Receive ATM Cell Processor (RXCP)
  - Cell Delineation
  - Descrambler
  - Cell Filter and HCS Verification
  - Performance Monitor
- Receive POS Frame Processor (RXFP)
  - Overhead Removal
  - Descrambler
  - POS Frame Delineation
  - Byte Destuffing
  - FCS Check
  - Performance Monitor
  - Receive FIFO
- Transmit Line Interface (CSPI)
  - Clock Synthesis
  - Parallel to Serial Converter
- Transmit Section Overhead Processor (TSOP)
  - Line AIS Insert
  - Data Link Insert
  - BIP-8 Insert
  - Framing and Identity Insert
  - Scrambler
- Transmit Line Overhead Processor (TLOP)
  - APS Insert
  - Data Link Insert
  - Line BIP Calculater
  - Line RDI Insert
  - Line Febe Insert
- Transmit Path Overhead Processor (TPOP)
  - Pointer Generator
  - BIP-8 Calculate
  - FEBE Calculate
- Transmit ATM Cell Processor (TXCP)
  - Idle/Unassigned Cell Generator
  - Scrambler
  - HCS Generator
- Transmit POS Frame Processor (TXFP)
  - Transmit FIFO
  - POS Frame Generator
  - FCS Generator
  - Byte Stuffing
  - Data Scrambling
  - Sonet/SDH Framer
- SONET/SDH Section and Path Trace Buffers (SSTB & SPTB)
  - Receive Trace Buffer (RTB)
    - Trace Message Receiver
    - Overhead Byte Receiver
  - Transmit Trace Buffer (TTB)
- ATM Utopia and Packet Over SONET/SDH POS-PHY System Interfaces
  - Receive ATM Interface
  - Receive POS Interface
    - Premature RPA Assertion
  - Transmit ATM Interface
  - Transmit POS Interface
- WAN Synchronization Controller (WANS)
  - Phase Comparison
  - Phase Reacquisition Control
  - Phase Averager
- JTAG Test Access Port
- Microprocessor Interface
NORMAL MODE REGISTER DESCRIPTION
TEST FEATURES DESCRIPTION
- Master Test Register
- Test Mode 0 Details
- JTAG Test Port
  - Boundary Scan Cells
OPERATION
- SONET/SDH Frame Mappings and Overhead Byte Usage
  - ATM Mapping
  - Packet Over SONET/SDH Mapping
  - Transport and Path Overhead Bytes
- ATM Cell Data Structure
- Packet Over SONET/SDH Data Structure
- Bit Error Rate Monitor
- Clocking Options
- Loopback Operation
- JTAG Support
  - TAP Controller
    - States
    - Instructions
- Board Design Reccomendations
- Analog Power Supply Filtering
- Power Supplies Sequencing
- Interfacing to ECL or PECL Devices
- Clock Recovery Loop Filter
- Setting the S/UNI-TETRA in ATM Mode
- Setting the S/UNI-TETRA in POS Mode
- Setting the S/UNI-TETRA for SONET or SDH Applications
- Using the S/UNI-TETRA with a 5 Volt ODL
FUNCTIONAL TIMING
- ATM Utopia Level 2 System Interface
- Packet Over SONET/SDH (POS) System Interface
- Section and Line Data Communications Channels
ABSOLUTE MAXIMUM RATINGS
D.C. CHARACTERISTICS
MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS
A.C. TIMING CHARACTERISTICS
- System Reset Timing
- Reference Timing
- ATM System Interface Timing
- POS System Interface Timing
- Line and Section DCC Timing
- Transmit and Receive Frame Pulses
- Transmit Line Timing in Single Ended TXD/TXC Mode
- JTAG Test Port Timing
ORDERING AND THERMAL INFORMATION
MECHANICAL INFORMATION

S/UNI-TETRA

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

DATASHEET

PMC-1971240

ISSUE 7

SATURN USER NETWORK INTERFACE (155-TETRA)

PMC-Sierra, Inc.

105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

Issue
No.

Issue Date

Details of Change

December,
1999

General update including:

Page 17 Signal Detect connection information

Page 18 Power info when using 155.52 transmit clocks

Page 24,32 Clarification on use of TENB and RENB

Page 37 PHY_OEN operation when the TETRA is

shared with other PHY devices on the same bus

Page 38 Device initialization information

Page 40 220nf X7R 10% ceramatic capacitor used to

meet jitter transfer specifications

Page 42 Pull-up resistor on QAVD signals needed to

avoid latchup during power-up

Page 60, 214, 234 Maximum packet length should be

set no greater than 0xFFFE

Page 66 Packets are not aborted in overrun conditions

Page 72 RPA assertion information

Page 86 Revision ID bits incremented

Page 105 LANB_WAN bit added to select between jitter

transfer and non jitter transfer mode of operations

Page 152 Path far end receiver failure alarm persistence

bit info updated

Page 161 Info on setting Path Signal Label for POS

mode

Page 176 FIFO reset should be performed after FIFO

overrrun

Page 210 Register bit added to select between abort

sequence or flag insertion under a drop path AIS condition

Page 216 Maximum Receive Packet Available High

Water Mark is 0xF0

S/UNI-TETRA

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

DATASHEET

PMC-1971240

ISSUE 7

SATURN USER NETWORK INTERFACE (155-TETRA)

PMC-Sierra, Inc.

105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

Issue
No.

Issue Date

Details of Change

December
1999

Page 229 Info on setting Transmit Initiation Levels

Page 232 Setting of Transmit Packet Available High

Water Mark to avoid FIFO overrruns

Page 250 S1 debouncing information

Page 268 Updated boundary scan info

Page 296 Analog Power Supply Filtering info

Page 298 Updated Power Supply Sequencing info

Page 303 Setting the TETRA for SDH or SONET mode

Page 308 Updated POS Receive Synchronous FIFO

Timing Diagram

Page 313 Updated DC characteristic

Page 336 Updated air flow info

S/UNI-TETRA

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

DATASHEET

PMC-1971240

ISSUE 7

SATURN USER NETWORK INTERFACE (155-TETRA)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE

CONTENTS

FEATURES .............................................................................................................. 1

1.1

GENERAL.................................................................................................... 1

1.2

THE SONET RECEIVER............................................................................... 2

1.3

THE RECEIVE ATM PROCESSOR................................................................ 3

1.4

THE RECEIVE POS PROCESSOR ............................................................... 3

1.5

THE SONET TRANSMITTER ........................................................................ 4

1.6

THE TRANSMIT ATM PROCESSOR.............................................................. 4

1.7

THE TRANSMIT POS PROCESSOR............................................................. 5

APPLICATIONS ........................................................................................................ 6

REFERENCES ......................................................................................................... 7

DEFINITIONS........................................................................................................... 9

APPLICATION EXAMPLES ..................................................................................... 12

BLOCK DIAGRAM .................................................................................................. 16

DESCRIPTION ....................................................................................................... 18

PIN DIAGRAM........................................................................................................ 21

PIN DESCRIPTION................................................................................................. 23

9.1

LINE SIDE INTERFACE SIGNALS............................................................... 23

9.2

SECTION AND LINE STATUS DCC SIGNALS .............................................. 27

9.3

ATM (UTOPIA) AND PACKET OVER SONET (POS-PHY) SYSTEM
INTERFACE ............................................................................................... 29

9.4

MICROPROCESSOR INTERFACE SIGNALS .............................................. 51

9.5

JTAG TEST ACCESS PORT (TAP) SIGNALS ............................................... 52

9.6

ANALOG SIGNALS..................................................................................... 53

9.7

POWER AND GROUND.............................................................................. 54

FUNCTIONAL DESCRIPTION................................................................................. 61

10.1

RECEIVE LINE INTERFACE (CRSI) ............................................................ 61

10.1.1

CLOCK RECOVERY................................................................. 61

10.1.2

SERIAL TO PARALLEL CONVERTER....................................... 62

10.2

RECEIVE SECTION OVERHEAD PROCESSOR (RSOP)............................. 62

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: PM5351-BI