PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PM4314
QDSX
QUAD T1/E1 LINE INTERFACE DEVICE
DATA SHEET
ISSUE 5: JUNE 1998
PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PUBLIC REVISION HISTORY
Issue
No.
Issue
Date
Details of Change
5
June,
1998
Data Sheet Reformatted -- No Change in Technical Content
Generated R5 data sheet from PMC-950739, R4
4
January,
1997
Eng Doc Issue R3 released
3
March,
1996
Public release of document: removal of confidential notices
2
January,
1996
Upgrade to Eng Doc Issue P2
1
August,
1995
Creation of Document
PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
i
CONTENTS
1
FEATURES ............................................................................................... 1
2
APPLICATIONS ........................................................................................ 5
3
REFERENCES ......................................................................................... 6
4
APPLICATION EXAMPLES ...................................................................... 8
5
BLOCK DIAGRAM.................................................................................. 13
6
DESCRIPTION ....................................................................................... 15
7
PIN DIAGRAM ........................................................................................ 18
8
PIN DESCRIPTION ................................................................................ 19
9
FUNCTIONAL DESCRIPTION ............................................................... 32
9.1
ANALOG PULSE SLICER (RSLC) .............................................. 32
9.2
CLOCK AND DATA RECOVERY (CDRC) .................................... 35
9.3
LINE CODE VIOLATION PERFORMANCE MONITOR
(LCV_PMON)............................................................................... 39
9.4
INBAND LOOPBACK CODE DETECTOR (IBCD) ....................... 40
9.5
PSEUDO-RANDOM BIT SEQUENCE MONITOR (PRSM).......... 40
9.6
TIMING OPTIONS (TOPS) .......................................................... 42
9.7
PSEUDO-RANDOM BIT SEQUENCE GENERATOR (PRSG)..... 42
9.8
INBAND LOOPBACK CODE GENERATOR (XIBC)..................... 43
9.9
B8ZS/HDB3/AMI LINE ENCODER (LCODE) .............................. 43
9.10
DIGITAL JITTER ATTENUATOR (DJAT)....................................... 43
9.11
ANALOG PULSE GENERATOR (XPLS)...................................... 49
PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
ii
9.12
IEEE P1149.1 JTAG TEST ACCESS PORT................................ 52
9.13
MICROPROCESSOR INTERFACE ............................................. 52
9.14
REGISTER MEMORY MAP ......................................................... 53
10
NORMAL MODE REGISTER DESCRIPTION........................................ 56
11
TEST FEATURES DESCRIPTION ....................................................... 113
11.1
TEST MODE 0 DETAILS ........................................................... 114
11.2
JTAG TEST PORT...................................................................... 116
12
OPERATIONS....................................................................................... 119
12.1
PROGRAMMING THE XPLS WAVEFORM TEMPLATE ............ 122
12.2
USING THE DIGITAL JITTER ATTENUATOR............................ 127
12.3
USING XPLS WITHOUT DJAT .................................................. 128
12.3.1 FIFO NOT IN TX PATH, XSEL[1] = 0 ............................... 129
12.3.2 FIFO NOT IN TX PATH, XSEL[1] = 1, XSEL[0] = 0.......... 129
12.3.3 FIFO IS IN TX PATH, XSEL[1] = 1, XSEL[0] = 0. ............ 129
12.3.4 FIFO NOT IN TX PATH, XSEL[1] = 1, XSEL[0] = 1.......... 129
12.3.5 FIFO IS IN TX PATH, XSEL[1] = 1, XSEL[0] = 1.............. 130
12.4
JTAG SUPPORT ........................................................................ 130
13
FUNCTIONAL TIMING ......................................................................... 141
13.1
LINE CODE VIOLATION INSERTION ....................................... 141
14
ABSOLUTE MAXIMUM RATINGS........................................................ 144
15
CAPACITANCE ..................................................................................... 145
16
D.C. CHARACTERISTICS .................................................................... 146
17
MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS ...... 149
PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
iii
18
A.C. TIMING CHARACTERISTICS ....................................................... 153
19
ORDERING AND THERMAL INFORMATION ...................................... 163
20
MECHANICAL INFORMATION............................................................. 164
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