Document Outline

• Contents
• Figures
• Tables
• Registers
• Timing Diagrams
• Preface
• Feature Summary
• 1 Introduction
  • 1.1 Company and ProductBackground
    • 1.1.1 PCI9030 SMARTarget I/O Accelerator
    • 1.1.2 SMARTarget Technology
    • 1.1.3 PCI9030 Applications
      • 1.1.3.1 High-Performance PCITargetInterface
      • 1.1.3.2 High-Performance CompactPCI Adapter Card
      • 1.1.3.3 PMC Adapter Cards
    • 1.1.4 PCI9030 SMARTarget Features
      • 1.1.4.1 Performance Features
      • 1.1.4.2 Flexibility Features
      • 1.1.4.3 Additional Features
    • 1.1.5 PLX Chip Compatibility
      • 1.1.5.1 Pin Compatibility
      • 1.1.5.2 Register Compatibility
    • 1.1.6 PCI9030 Comparison with Other PLX Chips
• 2 PCI and Local Bus
  • 2.1 PCI Bus
    • 2.1.1 PCI Bus Interface and Bus Cycles
      • 2.1.1.1 PCI Target Command Codes
      • 2.1.1.2 Wait States�PCI Bus
      • 2.1.1.3 PCI Bus Little Endian Mode
      • 2.1.1.4 PCI Prefetchable MemoryMapping
      • 2.1.1.5 PCI Target Accesses to an 8or16Bit Local Bus Device
  • 2.2 Local Bus
    • 2.2.1 Introduction
      • 2.2.1.1 Transactions
      • 2.2.1.2 Basic Bus States
    • 2.2.2 Local Bus Signals Used in TimingDiagrams
    • 2.2.3 Local Bus Signals
      • 2.2.3.1 Clock
      • 2.2.3.2 Address/Data
        • 2.2.3.2.1 Multiplexed Mode (MODE=1)
          • 2.2.3.2.1.1 LA[27:2]
          • 2.2.3.2.1.2 LAD[31:0]
        • 2.2.3.2.2 Non-Multiplexed Mode (MODE=0)
          • 2.2.3.2.2.1 LA[27:2]
          • 2.2.3.2.2.2 LD[31:0]
      • 2.2.3.3 Control/Status
        • 2.2.3.3.1 ADS#, ALE
        • 2.2.3.3.2 LBE[3:0]#
        • 2.2.3.3.3 LLOCKo#
        • 2.2.3.3.4 LW/R#
        • 2.2.3.3.5 RD#
        • 2.2.3.3.6 READY#
        • 2.2.3.3.7 WAITo#
        • 2.2.3.3.8 WR#
      • 2.2.3.4 Local Bus Arbitration
        • 2.2.3.4.1 LGNT
        • 2.2.3.4.2 LREQ
        • 2.2.3.4.3 Arbitration Timing Diagram
    • 2.2.4 Local Bus Interface andBusCycles
      • 2.2.4.1 Bus Cycles
      • 2.2.4.2 Wait State Control
        • 2.2.4.2.1 Internal Wait State Generator
        • 2.2.4.2.2 Ready Signaling
      • 2.2.4.3 Burst Mode and Continuous BurstMode (Bterm �Burst Terminate� Mode)
        • 2.2.4.3.1 Burst and Bterm Modes
        • 2.2.4.3.2 Burst-4 Mode
        • 2.2.4.3.3 Continuous Burst Mode (Bterm �Burst Terminate� Mode)
        • 2.2.4.3.4 Partial Lword Accesses
      • 2.2.4.4 Recovery States
      • 2.2.4.5 Local Bus Read Accesses
      • 2.2.4.6 Local Bus Write Accesses
    • 2.2.5 Local Bus Big/Little Endian Mode
      • 2.2.5.1 32-Bit Local Bus� BigEndianMode
      • 2.2.5.2 16-Bit Local Bus� BigEndianMode
      • 2.2.5.3 8-Bit Local Bus� BigEndianMode
• 3 Serial EEPROM Reset and Initialization
  • 3.1 Initialization
  • 3.2 Reset
    • 3.2.1 PCI Bus RST# Input
    • 3.2.2 Software Reset
    • 3.2.3 Local Bus Output LRESETo#
  • 3.3 Serial EEPROM
    • 3.3.1 Serial EEPROM Load Sequence
      • 3.3.1.1 Serial EEPROM Load
      • 3.3.1.2 Recommended Serial EEPROMs
  • 3.4 Internal Register Access
    • 3.4.1 PCI Configuration Registers
    • 3.4.2 PCI Bus Access to InternalRegisters
  • 3.5 New Capabilities FunctionSupport
  • 3.6 Serial EEPROM and Configuration Initialization Timing Diagrams
• 4 PCI Target (Direct Slave) Operation
  • 4.1 Overview
  • 4.2 Direct Data Transfer Mode
    • 4.2.1 PCI Target Operation (PCI Masterto-Local Bus Access)
      • 4.2.1.1 PCI Target Lock
      • 4.2.1.2 PCI r2.2 Features Enable
        • 4.2.1.2.1 PCI Target Delayed Read Mode
        • 4.2.1.2.2 215 PCI Clock Timeout
        • 4.2.1.2.3 PCI r2.2 16- and 8-Clock Rule
      • 4.2.1.3 Local Bus Prefetch
      • 4.2.1.4 PCI Target Read Ahead Mode
      • 4.2.1.5 PCI Target Delayed Write Mode
      • 4.2.1.6 PCI Target Local Bus READY#Timeout Mode
      • 4.2.1.7 PCI Target Transfer
      • 4.2.1.8 PCI Target PCI-to-Local AddressMapping
        • 4.2.1.8.1 PCI Target Local Bus Initialization
        • 4.2.1.8.2 PCI Target Initialization
        • 4.2.1.8.3 PCI Target Example
        • 4.2.1.8.4 PCI Target Byte Enables (Multiplexed Mode)
        • 4.2.1.8.5 PCI Target Byte Enables (NonMultiplexed Mode)
  • 4.3 Response to FIFO Full or Empty
  • 4.4 PCI Target (Direct Slave) Operation Timing Diagrams
    • 4.4.1 Serial EEPROM and Configuration Initialization Timing Diagrams
    • 4.4.2 Multiplexed and Non-Multiplexed Modes Timing Diagrams
      • 4.4.2.1 Multiplexed Mode Only Timing Diagrams
      • 4.4.2.2 Non-Multiplexed Mode Only Timing Diagrams
• 5 Local Chip Selects
  • 5.1 Overview
  • 5.2 Chip Select Base AddressRegisters
  • 5.3 Procedure for Using ChipSelect Base AddressRegisters
    • 5.3.1 Chip Select Base Address Register Programming Example
  • 5.4 Chip Select Timing Diagrams
• 6 Interrupts and General Purpose I/O
  • 6.1 Overview
  • 6.2 Interrupts
    • 6.2.1 PCI Interrupts (INTA#)
    • 6.2.2 Local Interrupt Input (LINTi[2:1])
    • 6.2.3 Local Power Management Interrupt (LPMINT#)
    • 6.2.4 Local Power Management Enumerator Set
    • 6.2.5 All Modes PCI SERR# (PCI NMI)
  • 6.3 General Purpose I/O
  • 6.4 Interrupts and General Purpose I/O Timing Diagrams
• 7 PCI Power Management
  • 7.1 Overview
  • 7.2 PCI Power Management Functional Description
    • 7.2.1 Power Management Data_Select,Data_Scale, andPower Data Utilization
    • 7.2.2 Reading Hidden Data Example
  • 7.3 System Changes Power Mode Example
  • 7.4 Wake-Up Request Example
• 8 CompactPCI Hot Swap
  • 8.1 Overview
  • 8.2 Controlling Connection Processes
    • 8.2.1 Connection Control
      • 8.2.1.1 Board Slot Control
      • 8.2.1.2 Board Healthy
      • 8.2.1.3 Platform Reset
    • 8.2.2 Software Connection Control
      • 8.2.2.1 Ejector Switch and Blue LED
      • 8.2.2.2 ENUM#
      • 8.2.2.3 Hot Swap Control/Status Register (HS_CSR)
      • 8.2.2.4 Hot Swap Capabilities Register
• 9 PCI Vital Product Data (VPD)
  • 9.1 Overview
  • 9.2 VPD Capabilities Register
  • 9.3 VPD Serial EEPROM Partitioning
  • 9.4 Sequential Read Only
  • 9.5 Random Access ReadandWrite
• 10 Registers
  • 10.1 New Register Definitions Summary (AsComparedtothePCI9050andPCI 9052)
  • 10.2 Register Address Mapping
  • 10.3 PCI Configuration Registers
  • 10.4 Local Configuration Registers
  • 10.5 Chip Select Registers
  • 10.6 Control Registers
• 11 Pin Description
  • 11.1 Pin Summary
  • 11.2 Pull-Up and Pull-Down Resistor Recommendations
    • 11.2.1 Input Pins (Pin Type I)
    • 11.2.2 Output Pins (Pin Type O)
      • 11.2.2.1 Three-State Output Pins
      • 11.2.2.2 Totem-Pole Output Pins
      • 11.2.2.3 Open-Drain Output Pins
    • 11.2.3 I/O Pins (Pin Type I/O)
  • 11.3 Pinout Common to All Bus Modes
  • 11.4 Multiplexed Local Bus Mode Pinout
  • 11.5 Non-Multiplexed Local Bus Mode Pinout
  • 11.6 Debug Interface
    • 11.6.1 IEEE 1149.1 Test Access Port (JTAG Debug Port)
    • 11.6.2 JTAG Instructions
    • 11.6.3 JTAG Boundary Scan
• 12 Electrical Specifications
  • 12.1 General Electrical Specifications
  • 12.2 Local Inputs
  • 12.3 Local Outputs
• 13 Physical Specifications
  • 13.1 176-Pin PQFP
  • 13.2 180-Pin �BGA
• A General Information
• Index
  • A
  • B
  • C
  • D
  • E
  • F
  • G
  • H
  • I
  • J
  • L
  • M
  • N
  • O
  • P
  • R
  • S
  • T
  • U
  • V
  • W
  • Z