Document Outline
- DESCRIPTION
- PIN
- FEATURES
- APPLICATION
- ORDERING INFORMATION
- FUNCTIONAL DIAGRAM
- TYPICAL APPLICATIONS
- ABSOLUTE MAXIMUM RATINGS
- DC ELECTRICAL CHARACTERISTICS
- TYPICAL DC PERFORMANCE CHARACTERISTICS
- TYPICAL AC PERFORMANCE CHARACTERISTICS
- PACKING
Philips
Semiconductors
LF398
Sample-and-hold amplifier
Product data
Replaces LF198/LF298/LF398 of 1994 Aug 31
IC11
2001 Aug 03
INTEGRATED CIRCUITS
Philips Semiconductors
Product data
LF398
Sample-and-hold amplifier
2
2001 Aug 03
853-0135 26832
DESCRIPTION
The LF398 is a monolithic sample-and-hold circuit which utilizes
high-voltage ion-implant JFET technology to obtain ultra-high DC
accuracy with fast acquisition of signal and low droop rate.
Operating as a unity gain follower, DC gain accuracy is 0.002%
typical and acquisition time is as low as 6
s to 0.01%. A bipolar
input stage is used to achieve low offset voltage and wide
bandwidth. Input offset adjust is accomplished with a single pin and
does not degrade input offset drift. The wide bandwidth allows the
LF398 to be included inside the feedback loop of 1 MHz op amps
without having stability problems. Input impedance of 10
10
allows
high source impedances to be used without degrading accuracy.
P-channel junction FETs are combined with bipolar devices in the
output amplifier to give droop rates as low as 5 mV/min with a 1
F
hold capacitor. The JFETs have much lower noise than MOS
devices used in previous designs and do not exhibit high
temperature instabilities. The overall design guarantees no
feedthrough from input to output in the hold mode even for input
signals equal to the supply voltages.
Logic inputs are fully differential with low input current, allowing
direct connection to TTL, PMOS, and CMOS; differential threshold is
1.4 V. The LF398 will operate from
5 V to
18 V supplies. It is
available in 8-pin plastic DIP and 14-pin plastic SO packages.
FEATURES
Operates from
5 V to
18 V supplies
Less than 10
s acquisition time
TTL, PMOS, CMOS compatible logic input
0.5 mV typical hold step at C
H
= 0.01
F
Low input offset
0.002% gain accuracy
Low output noise in hold mode
Input characteristics do not change during hold mode
High supply rejection ratio in sample or hold
Wide bandwidth
PIN CONFIGURATIONS
N Package
D Package
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
14
13
12
11
10
9
V+
OFFSET VOLTAGE
INPUT
V
NC
V+
OUTPUT
LOGIC
INPUT
V
LOGIC REF
NC
NC
NC
NC
NC
LOGIC
LOGIC REFERENCE
OUTPUT
VOS Adj
Ch
Ch
SL00083
Figure 1. Pin Configurations
APPLICATION
The LF398 is ideally suited for a wide variety of sample-and-hold
applications, including data acquisition, analog-to-digital
conversion, synchronous demodulation, and automatic test setup.
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
DWG #
14-Pin Plastic Small Outline (SO) Package
0 to +70
C
LF398D
SOT108-1
8-Pin Plastic Dual In-Line Package (DIP)
0 to +70
C
LF398N
SOT97-1
Philips Semiconductors
Product data
LF398
Sample-and-hold amplifier
2001 Aug 03
3
FUNCTIONAL DIAGRAM
SL00084
OFFSET
INPUT
LOGIC
LOGIC
REFERENCE
HOLD
CAPACITOR
OUTPUT
3
8
7
6
5
+
30 k
300
Figure 2. Functional Diagram
TYPICAL APPLICATIONS
OUTPUT
INPUT
LOGIC
ANALOG INPUT
SAMPLE 5 V
HOLD 0 V
S/H
3
8
7
6
5
4
1
V+
V
Ch
SL00085
Figure 3. Typical Applications
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
V
S
Supply voltage
18
V
Maximum power dissipation
T
amb
= 25
C (still-air)
3
N package
1160
mW
D package
1040
mW
T
amb
Operating ambient temperature range
0 to +70
C
T
stg
Storage temperature range
-65 to +150
C
V
IN
Input voltage
Equal to supply voltage
Logic-to-logic reference differential voltage
2
+7, -30
V
Output short-circuit duration
Indefinite
Hold capacitor short-circuit duration
10
sec
T
SOLD
Lead soldering temperature (10 sec max)
230
C
NOTES:
1. The maximum junction temperature of the LF398 is 150
C.
When operating at elevated ambient temperature, the packages must be
derated based on the thermal resistance specified.
2. Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins must always be at least 2V
below the positive supply and 3 V above the negative supply.
3. Derate above 25
C, at the following rates:
N package at 9.3 mW/
C
D package at 8.3 mW/
C
Philips Semiconductors
Product data
LF398
Sample-and-hold amplifier
2001 Aug 03
4
DC ELECTRICAL CHARACTERISTICS
Unless otherwise specified, the following conditions apply: unit is in "sample" mode; V
S
=
15 V; T
j
= 25
C; 11.5 V3 V
IN
+11.5 V;
C
H
= 0.01
F; and R
L
= 10 k
. Logic reference voltage = 0 V and logic voltage = 2.5 V.
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ
Max
UNIT
V
OS
Input offset voltage
4
T
j
= 25
C
2
7
mV
V
OS
In ut offset voltage
Full temperature range
10
mV
I
BIAS
Input bias current
4
T
j
= 25
C
10
50
nA
I
BIAS
In ut bias current
Full temperature range
100
nA
Input impedance
T
j
= 25
C
10
10
Gain error
T
j
= 25
C, R
L
=10 k
0.004
0.01
%
Gain error
Full temperature range
0.02
%
Feedthrough attenuation ratio at 1 kHz
T
j
= 25
C,
C
h
= 0.01
F
80
90
dB
Output impedance
T
j
= 25
C,
"HOLD" mode
0.5
4
Out ut im edance
Full temperature range
6
"HOLD" step
2
T
j
= 25
C, C
h
= 0.01
F, V
OUT
= 0 V
1.0
2.5
mV
I
CC
Supply current
4
T
j
25
C
4.5
6.5
mA
Logic and logic reference input current
T
j
= 25
C
2
10
A
Leakage current into hold capacitor
4
T
j
= 25
C, "HOLD" mode
30
200
pA
t
AC
Acquisition time to 0 1%
V
OUT
= 10 V, C
h
= 1000 pF
4
s
t
AC
Acquisition time to 0.1%
C
h
= 0.01
F
20
s
Hold capacitor charging current
V
IN
V
OUT
= 2 V
5
mA
Supply voltage rejection ratio
V
OUT
= 0 V
80
110
dB
Differential logic threshold
T
j
= 25
C
0.8
1.4
2.4
V
NOTES:
1. Unless otherwise specified, the following conditions apply. Unit is in "sample" mode, V
S
=
15 V, T
j
= 25
C, 11.5 V
V
IN
+11.5 V,
C
h
= 0.01
F, and R
L
= 10 k
. Logic reference voltage = 0 V and logic voltage = 2.5 V.
2. Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an
additional 0.5 mV step with a 5 V logic swing and a 0.01
F hold capacitor. Magnitude of the hold step is inversely proportional to hold
capacitor value.
3. Leakage current is measured at a junction temperature of 25
C. The effects of junction temperature rise due to power dissipation or
elevated ambient can be calculated by doubling the 25
C value for each 11
C increase in chip temperature. Leakage is guaranteed over
full input signal range.
4. The parameters are guaranteed over a supply voltage of
5 to
18 V.
Philips Semiconductors
Product data
LF398
Sample-and-hold amplifier
2001 Aug 03
5
TYPICAL DC PERFORMANCE CHARACTERISTICS
JUNCTION TEMPERATURE (
C)
HOLD STEP
(mV)
Input Bias Current
Output Short Circuit Current
Gain Error
Hold Step
Leakage Current Into
Hold Capacitor
Hold Step Input Voltage
CURRENT
(mA)
100
10
1
0.1
0.01
25
20
15
10
5
0
5
10
15
50
25
0
25
50
75
100
125 150
JUNCTION TEMPERATURE (
C)
100 pF
1000 pF
0.01
F
0.1
F
1
F
HOLD CAPACITOR
V+ = V = 15 V
Tj = 25
C
CURRENT
(nA)
CURRENT
(mA)
100
10
1
10
1
10
2
50
25
0
25
50
75
100
125 150
50
25
0
25
50
75
100
125 150
JUNCTION TEMPERATURE (
C)
VS =
15 V
VOUT = 0 V
HOLD MODE
20
18
16
14
12
10
8
6
4
2
0
SOURCING
SINKING
NORMALIZED HOLD STEP
AMPLITUDE
INPUT VOL
T
AGE
--
OUTPUT
VOL
T
AGE (mV)
1
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1
15
10
5
0
5
10
15
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
15
10
5
0
5
10
15
Tj = 25
C
Tj = 55
C
Tj = 100
C
Tj = 25
C
RL = 10 k
SAMPLE MODE
SL00086
Figure 4. Typical DC Performance Characteristics
TYPICAL AC PERFORMANCE CHARACTERISTICS
V+ = V = 15 V
VOUT
1 mV
NEGATIVE
INPUT
STEP
VIN = 10 V
POSITIVE
INPUT
STEP
Acquisition Time
Aperture Time
Capacitor Hysteresis
TIME ( s)
1
10
100
1000
1%
0.1%
0.01%
VIN = 0 V to
10 V
Tj = 25
C
HOLD CAPACITOR (
F)
0.001
0.01
0.1
250
225
200
175
150
125
100
75
50
25
0
TIME (ns)
50
25
0
25
50
75
100
125 150
JUNCTION TEMPERATURE (
C)
100
10
1
0.1
100
10
1
0.1
SAMPLE TIME (ms)
SL00087
POLYPROPYLENE
AND POLYSTYRENE
HYSTERESIS
MYLAR
HYSTERESIS
MYLAR
TIME
CONSTANT
POLYPROPYLENE
AND POLYSTYRENE
TIME CONSTANT
Figure 5. Typical AC Performance Characteristics
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