2003 Apr 10
2
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
CONTENTS
1
FEATURES
1.1
General
1.2
Control
1.3
IEC 60958 input
1.4
IEC 60958 output
1.5
Digital I/O interface
1.6
ADC digital sound processing
1.7
DAC digital sound processing
2
GENERAL DESCRIPTION
3
ORDERING INFORMATION
4
QUICK REFERENCE DATA
5
BLOCK DIAGRAM
6
PINNING
7
FUNCTIONAL DESCRIPTION
7.1
IC control
7.2
Microcontroller interface
7.3
Clock systems
7.4
IEC 60958 decoder
7.5
IEC 60958 encoder
7.6
Analog input
7.7
Analog output
7.8
Digital audio input and output
7.9
Power-on reset
8
APPLICATION MODES
8.1
Static mode pin assignment
8.2
Static mode basic applications
8.3
Microcontroller mode pin assignment
8.4
Microcontroller mode applications
9
SPDIF SIGNAL FORMAT
9.1
SPDIF channel encoding
9.2
SPDIF hierarchical layers
9.3
Timing characteristics
10
L3-BUS DESCRIPTION
10.1
Device addressing
10.2
Register addressing
10.3
Data write mode
10.4
Data read mode
11
I
2
C-BUS DESCRIPTION
11.1
Characteristics
11.2
Bit transfer
11.3
Byte transfer
11.4
Data transfer
11.5
Register address
11.6
Device address
11.7
Start and stop conditions
11.8
Acknowledgment
11.9
Write cycle
11.10
Read cycle
12
REGISTER MAPPING
12.1
Address mapping
12.2
Read/write registers mapping
12.3
Read registers mapping
13
LIMITING VALUES
14
THERMAL CHARACTERISTICS
15
CHARACTERISTICS
16
TIMING CHARACTERISTICS
17
PACKAGE OUTLINE
18
SOLDERING
18.1
Introduction to soldering surface mount
packages
18.2
Reflow soldering
18.3
Wave soldering
18.4
Manual soldering
18.5
Suitability of surface mount IC packages for
wave and reflow soldering methods
19
DATA SHEET STATUS
20
DEFINITIONS
21
DISCLAIMERS
22
PURCHASE OF PHILIPS I
2
C COMPONENTS
2003 Apr 10
3
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
1
FEATURES
1.1
General
2.7 to 3.6 V power supply
Integrated digital interpolator filter and Digital-to-Analog
Converter (DAC)
24-bit data path in interpolator
No analog post filtering required for DAC
Integrated Analog-to-Digital Converter (ADC),
Programmable Gain Amplifier (PGA) and digital
decimator filter
24-bit data path in decimator
Master or slave mode for digital audio data I/O interface
I
2
S-bus, MSB-justified, LSB-justified 16, 18, 20,
and 24 bits formats supported on digital I/O interface.
1.2
Control
Controlled by means of static pins or microcontroller
(L3-bus or I
2
C-bus) interface.
1.3
IEC 60958 input
On-chip amplifier for converting IEC 60958 input to
CMOS levels
Supports level I, II and III timing
Selectable IEC 60958 input channel, one of four
Supports input frequencies from 28 to 96 kHz
Lock indication signal available on pin LOCK
40 status bits can be read for left and right channel via
L3-bus or I
2
C-bus
Channel status bits available via L3-bus or I
2
C-bus: lock,
pre-emphasis, audio sample frequency, two channel
Pulse Code Modulation (PCM) indication and clock
accuracy
Pre-emphasis information of incoming IEC 60958
bitstream available in register
Detection of digital data preamble, such as AC3,
available on pin in microcontroller mode.
1.4
IEC 60958 output
CMOS output level converted to IEC 60958 output
signal
Full-swing digital signal, with level II timing using crystal
oscillator clock
32, 44.1 and 48 kHz output frequencies supported in
static mode
32, 44.1 and 48 kHz output frequencies (including
double and half of these frequencies) supported in
microcontroller mode
Via microcontroller, 40 status bits can be set for left and
right channel.
1.5
Digital I/O interface
Supports sampling frequencies from 16 to 100 kHz
Supported static mode:
I
2
S-bus format
LSB-justified 16 and 24 bits format
MSB-justified format.
Supported microcontroller mode:
I
2
S-bus format
LSB-justified 16, 18, 20 or 24 bits format
MSB-justified format.
BCK and WS signals can be slave or master, depending
on application mode.
1.6
ADC digital sound processing
Supports sampling frequencies from 16 to 100 kHz
Analog front-end includes a 0 to +24 dB PGA in steps of
3 dB, selectable via microcontroller interface
Digital independent left and right volume control of
+24 to
-
63.5 dB in steps of 0.5 dB via microcontroller
interface
Bitstream ADC operating at 64f
s
Comb filter decreases sample rate from 64f
s
to 8f
s
Decimator filter (8f
s
to f
s
) made of a cascade of three
FIR half-band filters.
1.7
DAC digital sound processing
Digital de-emphasis for 32, 44.1, 48 and 96 kHz audio
sampling frequencies
Automatic de-emphasis when using IEC 60958 to DAC
Soft mute made of a cosine roll-off circuit selectable via
pin MUTE or L3-bus interface
2003 Apr 10
4
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
Programmable digital silence detector
Interpolating filter (f
s
to 64f
s
or f
s
to 128f
s
) comprising a
recursive and a FIR filter in cascade
Selectable fifth-order noise shaper operating at 64f
s
or
third-order noise shaper operating at 128f
s
(specially for
low sampling frequencies, e.g. 16 kHz) generating
bitstream for DAC
Filter Stream DAC (FSDAC)
In microcontroller mode:
Left and right volume control (for balance control)
0 to
-
78 dB and
-
Left and right bass boost and treble control
Optional resonant bass boost control
Mixing possibility of two data streams.
2
GENERAL DESCRIPTION
The UDA1355H is a single-chip IEC 60958 decoder and
encoder with integrated stereo digital-to-analog converters
and analog-to-digital converters employing bitstream
conversion techniques.
The UDA1355H has a selectable one-of-four SPDIF input
(accepting level I, II and III timing) and one SPDIF output
which can generate level II output signals with CMOS
levels. In microcontroller mode the UDA1355H offers a
large variety of possibilities for defining signal flows
through the IC, offering a flexible analog, digital and SPDIF
converter chip with possibilities for off-chip sound
processing via the digital input and output interface.
A lock indicator is available on pin LOCK when the
IEC 60958 decoder and the clock regeneration
mechanism is in lock. By default the DAC output and the
digital data interface output are muted when the decoder
is not in lock.
The UDA1355H contains two clock systems which can run
at independent frequencies, allowing to lock-on to an
incoming SPDIF or digital audio signal, and in the mean
time generating a stable signal by means of the crystal
oscillator for driving, for example, the ADC or SPDIF
output signal.
Using the crystal oscillator (which requires a 12.288 MHz
crystal) and the on-chip low jitter PLL, all standard audio
sampling frequencies (f
s
= 32, 44.1 and 48 kHz including
half and double these frequencies) can be generated.
3
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
UDA1355H
QFP44
plastic quad flat package; 44 leads (lead length 1.3 mm); body
10
10
1.75 mm
SOT307-2
2003 Apr 10
5
Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
4
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
DDA1
DAC supply voltage
2.7
3.0
3.6
V
V
DDA2
ADC supply voltage
2.7
3.0
3.6
V
V
DDX
crystal oscillator and PLL
supply voltage
2.7
3.0
3.6
V
V
DDI
digital core supply voltage
2.7
3.0
3.6
V
V
DDE
digital pad supply voltage
2.7
3.0
3.6
V
I
DDA1
DAC supply current
f
s
= 48 kHz; power-on
-
4.7
-
mA
f
s
= 96 kHz; power-on
-
4.7
-
mA
f
s
= 48 kHz; power-down
-
1.7
-
A
f
s
= 96 kHz; power-down
-
1.7
-
A
I
DDA2
ADC supply current
f
s
= 48 kHz; power-on
-
10.2
-
mA
f
s
= 96 kHz; power-on
-
10.4
-
mA
f
s
= 48 kHz; power-down
-
0.2
-
A
f
s
= 96 kHz; power-down
-
0.2
-
A
I
DDX
crystal oscillator and PLL
supply current
f
s
= 48 kHz; power-on
-
0.9
-
mA
f
s
= 96 kHz; power-on
-
1.2
-
mA
I
DDI
digital core supply current
f
s
= 48 kHz; all on
-
18.2
-
mA
f
s
= 96 kHz; all on
-
34.7
-
mA
I
DDE
digital pad supply current
f
s
= 48 kHz; all on
-
0.5
-
mA
f
s
= 96 kHz; all on
-
0.7
-
mA
T
amb
ambient temperature
-
40
-
+85
C
Digital-to-analog converter; f
i
= 1 kHz; V
DDA1
= 3.0 V
V
o(rms)
output voltage (RMS
value)
-
900
-
mV
V
o
output voltage unbalance
-
0.1
-
dB
(THD+N)/S
total harmonic
distortion-plus-noise to
signal ratio
IEC 60958 input; f
s
= 48 kHz
at 0 dB
-
-
88
-
dB
at
-
20 dB
-
-
75
-
dB
at
-
60 dB; A-weighted
-
-
37
-
dB
IEC 60958 input; f
s
= 96 kHz
at 0 dB
-
-
83
-
dB
at
-
60 dB; A-weighted
-
-
37
-
dB
S/N
signal-to-noise ratio
IEC 60958 input; code = 0;
A-weighted
f
s
= 48 kHz
-
98
-
dB
f
s
= 96 kHz
-
96
-
dB
cs
channel separation
-
100
-
dB
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