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Электронный компонент: UCB1510DB

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UCB1510
AC97 digital modem codec
Rev. 01 -- 4 February 2000
Preliminary specification
c
c
1.
Description
The UCB1510 is a single chip, integrated mixed signal telecom codec that can
directly be connected to a DAA and supports high speed modem protocols. The
general purpose I/O pins provide programmable inputs and/or outputs to the system.
The UCB1510 has a serial AClink interface intended to communicate to the system
controller. Both the codec input data and codec output data and the control register
data are multiplexed on this interface.
2.
Features
s
Sigma delta telecom codec with programmable sample rate, including digitally
controlled input voltage level, mute, loop back and clip detection functions. The
telecom codec can be directly connected to a Data Access Arrangement (DAA)
and includes a built in sidetone suppression circuit
s
AClink (rev 2.1) interface with secondary codec support
s
3.3 V supply voltage and built in power saving modes make the UCB1510 optimal
for portable and battery powered applications
s
5 V tolerant interface for motherboard/PC add on
s
Maximum operating current 25 mA
s
8 general purpose IO pins for line interface control
s
Interrupt detection driven wake up sequence for ring detect
s
Low cost 12.288 MHz crystal
3.
Applications
s
Standalone modems
s
Integrated modems
s
Audio/Modem Riser (AMR) Cards
s
Mobile Daughter Cards (MDC)
Philips Semiconductors
UCB1510
AC97 digital modem codec
Preliminary specification
Rev. 01 -- 4 February 2000
2 of 32
9397 750 06856
Philips Electronics N.V. 2000. All rights reserved.
4.
Ordering information
5.
Block diagram
Table 1:
Ordering information
Type number
Package
Name
Description
Version
UCB1510DB
SSOP28
plastic shrink small outline package, 28 leads, body width 5.3mm
SOT341-1
Fig 1.
Block diagram
ADC
DAC
down
sample
filter
up
sample
filter
GPIO
data /
control
registers
Voltage
reference
Serial bus
interface
Clock buffers &
sample rate
dividers
TINP
TINN
TOUTP
TOUTN
IO[7:0]
SDOUT
SDIN
SYNC
RESET
BIT_CLK
XTAL_IN/A1
VREFBYP
Line1 PCM flow
XTAL_OUT
PON
A0
Philips Semiconductors
UCB1510
AC97 digital modem codec
Preliminary specification
Rev. 01 -- 4 February 2000
3 of 32
9397 750 06856
Philips Electronics N.V. 2000. All rights reserved.
6.
Pinning information
6.1 Pinning
6.2 Pin description
Fig 2.
Pin configuration
UCB1510
VSSA
TINN
TINP
VREFBYP
TOUTN
TOUTP
VDDA
VSSD
IO7
IO6
IO5
IO4
IO0
IO1
IO2
IO3
RESET
A0
VDDD
PON
SYNC
SDOUT
VSSD
SDIN
BIT_CLK
VDDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
26
25
24
23
22
21
20
19
18
17
16
XTAL_OUT
XTAL_IN/A1
28
27
Table 2:
Pin description
Symbol
Pin
Reset
state
[1]
Type
[2]
Description
V
DDD
1
-
S
digital supply
IO0
2
input
I/O
C
general purpose I/O pins
IO1
3
input
I/O
C
general purpose I/O pins
IO2
4
input
I/O
C
general purpose I/O pins
IO3
5
input
I/O
C
general purpose I/O pins
RESET
6
-
I
C
asynchronous reset input
A0
7
-
I
C
address select (for secondary codec) -
inverted polarity
PON
8
-
I
C
asynchronous cold reset
SYNC
9
-
I/O
C
AClink synchronization input
SDOUT
10
-
I
C
AClink data input
V
SSD
11
-
S
digital ground
SDIN
12
0
[4]
O
C
AClink data output
BIT_CLK
13
-
[3]
I/O
C
AClink serial interface clock
V
DDD
14
-
S
digital supply
IO4
15
input
I/O
C
general purpose I/O pins
Philips Semiconductors
UCB1510
AC97 digital modem codec
Preliminary specification
Rev. 01 -- 4 February 2000
4 of 32
9397 750 06856
Philips Electronics N.V. 2000. All rights reserved.
[1]
After cold or warm reset, the AClink interface is active with MLNK bit reset.
[2]
I/O
C
= CMOS bidirectional; I
D
= digital input; S = supply; O
A
= analog output; I
C
= CMOS input;
I
A
= analog input; I/O
A
= analog bidirectional; O
C
= CMOS output.
[3]
BIT_CLK is an input for AClink secondary codec, an output for primary codec. When BIT_CLK is an
output, the XTAL oscillator is active.
[4]
SDIN is driving a 0 until a valid SYNC framing signal is received after cold reset.
IO5
16
input
I/O
C
general purpose I/O pins
IO6
17
input
I/O
C
general purpose I/O pins
IO7
18
input
I/O
C
general purpose I/O pins
V
SSD
19
-
S
digital ground
V
DDA
20
-
S
analog supply
TOUTP
21
hi Z
O
A
positive telecom codec output
TOUTN
22
hi Z
O
A
negative telecom codec output
VREFBYP
23
hi Z
I/O
A
external reference voltage bypass
TINP
24
-
I
A
positive telecom codec input
TINN
25
-
I
A
negative telecom codec input
V
SSA
26
-
S
analog ground
XTAL_IN/A1
27
-
[3]
I
A
/I
C
Xtal oscillator/master clock input or inverted
secondary address
XTAL_OUT
28
-
[3]
O
A
Xtal oscillator output
Table 2:
Pin description
...continued
Symbol
Pin
Reset
state
[1]
Type
[2]
Description
Philips Semiconductors
UCB1510
AC97 digital modem codec
Preliminary specification
Rev. 01 -- 4 February 2000
5 of 32
9397 750 06856
Philips Electronics N.V. 2000. All rights reserved.
7.
Functional description
The functional description of the devices id described in
Section 8
through
Section 15
.
8.
Telecom codec
The telecom codec contains an input channel, built up from a 64 times oversampling
sigma delta analog to digital converter (ADC) with digital decimation filters,
programmable gain and attenuation and built-in sidetone suppression circuit.
The output path consists of a digital up sample filter, a 64 time oversampling 4 bit
digital to analog converter (DAC) circuit with integrated filter followed by a differential
output driver, capable of directly driving a 600
isolation transformer. The output
path includes a mute function. The telecom codec also incorporates loop back
modes, in which codec output path and the input path are connected in series. The
loop back tap and entry points are identified as circled letters in
Figure 3
, loop back
modes are described in the AClink register definition.
The telecom sample rate (f
st
) is derived from the AC master clock and is
programmable using the sample rate registers. Not all AC97 specified sample rates
are supported, refer to
Table 3 "Sampling frequencies"
for details.
PCM data is transferred in the slot 5 of the AClink.
Fig 3.
Telecom codec block diagram
TINP
TOUTP
TOUTN
sidetone_enable
ADC
DIGITAL
DECIMATION
FILTER
14
14
DAC Mute
DAC
DIGITAL
NOISE
SHAPER
TINN
SIDETONE
SUPPRESSION
CIRCUIT
ADC[3:2]
E
C
J
H
G
B
D