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Электронный компонент: TZA3017HW

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DATA SHEET
Product specification
Supersedes data of 2002 Jan 16
2003 May 14
INTEGRATED CIRCUITS
TZA3017HW
30 Mbits/s up to 3.2 Gbits/s
A-rate
TM
fibre optic transmitter
2003 May 14
2
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate
TM
fibre optic transmitter
TZA3017HW
FEATURES
Single 3.3 V power supply
I
2
C-bus and pin programmable fibre optic transmitter.
Synthesizer features
Supports SDH/SONET bit rates at 155.52, 622.08,
2488.32 and 2666.06 Mbits/s (STM16/OC48
+
FEC)
Supports Gigabit Ethernet at 1250 and 3125 Mbits/s
Supports Fibre Channel at 1062.5 and 2125 Mbits/s
Loss Of Lock (LOL) indicator
ITU-T compliant jitter generation.
Multiplexer features
16:1, 10:1, 8:1 or 4:1 multiplexing ratio
Rail-to-rail parallel inputs compliant with LVPECL, CML
and LVDS
4-stage FIFO for wide tolerance to clock skew
Supports co-directional and contra-directional clocking
Programmable parity checking
CML data and clock outputs, and loop mode inputs
LVPECL outputs on parallel interface
Line loop back input
Diagnostic loop back output.
Additional features with the I
2
C-bus
A-rate
TM(1)
supports any bit rate from 30 Mbits/s to
3.2 Gbits/s with one reference frequency
Programmable frequency resolution of 10 Hz
Adjustable swings of data and clock outputs
CML outputs on parallel interface
Programmable polarity of all RF I/Os
Exchangeable pin designations of RF clock with data for
all I/Os for optimum connectivity
Reversible pin designations of parallel data bus bits for
optimum connectivity
Four reference frequency ranges.
APPLICATIONS
Any optical transmission system with bit rates between
30 Mbits/s and 3.2 Gbits/s
Physical interface IC in transmit channels
Transponder applications
Dense Wavelength Division Multiplexing (DWDM)
systems.
GENERAL DESCRIPTION
The TZA3017HW is a fully integrated optical network
transmitter, containing a clock synthesizer and a
multiplexer with multiplexing ratios of 16:1, 10:1, 8:1
or 4:1.
The A-rate feature allows the IC to operate at any bit rate
between 30 Mbits/s and 3.2 Gbits/s using a single
reference frequency. The transmitter supports loop modes
with serial clock and data inputs and outputs. All clock
signals are generated using a fractional N synthesizer with
10 Hz resolution giving a true, continuous rate operation.
For full configuration flexibility, the transmitter is
programmable either by pin or via the I
2
C-bus.
(1) Koninklijke Philips Electronics N.V.
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
TZA3017HW
HTQFP100
plastic, heatsink thin quad flat package; 100 leads;
body 14
14
1.0 mm
SOT638
-
1
2003
May
14
3
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-r
ate
TM
fibre optic tr
ansmitter
TZA3017HW
2003
May
14
3
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-r
ate
TM
fibre optic tr
ansmitter
TZA3017HW
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BLOCK DIA
GRAM
handbook, full pagewidth
MGW559
PARITY
PARITYQ
PAREVEN
PARERR
PARERRQ
FIFORESET
OVERFLOW
16
55
56
74
73
44
38
81
45
46
82
78
79
37
3, 5, 7, 9, 11, 14, 16,
18, 20, 22, 27, 29, 31,
94, 96, 98
4, 6, 8, 10, 12, 15, 17,
19, 21, 23, 28, 30, 32,
95, 97, 99
CLOCK
SYNTHESIZER
0
/ 90
PHASE SHIFT
I
2
C-BUS
INTERRUPT
CONTROLLER
POWER-ON
RESET
PARITY
CHECKER
AND
BUS SWAP
MUX
4 : 1
8 : 1
10 : 1
16 : 1
4 deep
FIFO
W
R
D00 to D15
34
71
40
39
35
16
D00Q to D15Q
PICLKQ
PICLK
POCLKQ
CLKDIR
PRSCLO
CREF
CREFQ
LOL
PRSCLOQ
SCL(DR2)
ENLOUTQ
ENLINQ
SDA(DR1)
CS(DR0)
UI
16
16
16
16
2
2
COUT
POCLK
2
18
7
2
2
CINQ
DINQ
CIN
DIN
MUXR0
MUXR1
DOUT
INT
2
84
67
66
60
59
89
88
92
91
52
57
47
43
MD0
62
MD1
63
VCCD VCCA
75
VCCO
69
VDD
51
VEE
2, 13, 24,
26, 50,
70, 76
42
1, 25, 33, 36, 41, 49,
58, 61, 64, 65, 68, 77,
80, 83, 87, 90, 93, 100
48
53
54
72
85
86
D
C
D
C
2
2
2
CLOOP
DLOOP
COUTQ
DOUTQ
CLOOPQ
DLOOPQ
TZA3017HW
Fig.1 Simplified block diagram.
2003 May 14
4
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate
TM
fibre optic transmitter
TZA3017HW
PINNING
SYMBOL
PIN
DESCRIPTION
V
EE
die pad common ground plane
V
CCD
1
supply voltage (digital part)
V
EE
2
ground
D12Q
3
parallel data input 12 inverted
D12
4
parallel data input 12
D11Q
5
parallel data input 11 inverted
D11
6
parallel data input 11
D10Q
7
parallel data input 10 inverted
D10
8
parallel data input 10
D09Q
9
parallel data input 09 inverted
D09
10
parallel data input 09
D08Q
11
parallel data input 08 inverted
D08
12
parallel data input 08
V
EE
13
ground
D07Q
14
parallel data input 07 inverted
D07
15
parallel data input 07
D06Q
16
parallel data input 06 inverted
D06
17
parallel data input 06
D05Q
18
parallel data input 05 inverted
D05
19
parallel data input 05
D04Q
20
parallel data input 04 inverted
D04
21
parallel data input 04
D03Q
22
parallel data input 03 inverted
D03
23
parallel data input 03
V
EE
24
ground
V
CCD
25
supply voltage (digital part)
V
EE
26
ground
D02Q
27
parallel data input 02 inverted
D02
28
parallel data input 02
D01Q
29
parallel data input 01 inverted
D01
30
parallel data input 01
D00Q
31
parallel data input 00 inverted
D00
32
parallel data input 00
V
CCD
33
supply voltage (digital part)
PICLKQ
34
parallel clock input inverted
PICLK
35
parallel clock input
V
CCD
36
supply voltage (digital part)
PARITYQ
37
parity input inverted
PARITY
38
parity input
POCLKQ
39
parallel clock output inverted
POCLK
40
parallel clock output
V
CCD
41
supply voltage (digital part)
CREFQ
42
reference clock input inverted
CREF
43
reference clock input
PAREVEN
44
parity select (odd or even)
MUXR1
45
multiplexing ratio select 1
MUXR0
46
multiplexing ratio select 0
PRSCLOQ
47
prescaler output signal inverted
PRSCLO
48
prescaler output signal
V
CCD
49
supply voltage (digital part)
V
EE
50
ground
V
DD
51
supply voltage (digital part)
SCL(DR2)
52
I
2
C-bus serial clock (data rate
select 2)
SDA(DR1)
53
I
2
C-bus serial data (data rate
select 1)
CS(DR0)
54
chip select (data rate select 0)
OVERFLOW
55
FIFO overflow alarm output
FIFORESET
56
FIFO reset input
LOL
57
loss of lock output
V
CCD
58
supply voltage (digital part)
COUTQ
59
serial clock output inverted
COUT
60
serial clock output
V
CCD
61
supply voltage (digital part)
MD0
62
parallel data input termination
mode select 0
MD1
63
parallel data input termination
mode select 1
V
CCD
64
supply voltage (digital part)
V
CCD
65
supply voltage (digital part)
DOUTQ
66
serial data output inverted
DOUT
67
serial data output
V
CCD
68
supply voltage (digital part)
V
CCO
69
supply voltage (clock
generator)
V
EE
70
ground
CLKDIR
71
selection between co- and
contra-directional clocking
UI
72
user interface select
PARERRQ
73
parity error output inverted
PARERR
74
parity error output
V
CCA
75
supply voltage (analog part)
SYMBOL
PIN
DESCRIPTION
2003 May 14
5
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate
TM
fibre optic transmitter
TZA3017HW
V
EE
76
ground
V
CCD
77
supply voltage (digital part)
DINQ
78
loop mode data input inverted
DIN
79
loop mode data input
V
CCD
80
supply voltage (digital part)
CINQ
81
loop mode clock input inverted
CIN
82
loop mode clock input
V
CCD
83
supply voltage (digital part)
INT
84
interrupt output
ENLOUTQ
85
diagnostic loop back enable
input (active LOW)
ENLINQ
86
line loop back enable input
(active LOW)
V
CCD
87
supply voltage (digital part)
DLOOPQ
88
loop mode data output inverted
DLOOP
89
loop mode data output
V
CCD
90
supply voltage (digital part)
SYMBOL
PIN
DESCRIPTION
CLOOPQ
91
loop mode clock output
inverted
CLOOP
92
loop mode clock output
V
CCD
93
supply voltage (digital part)
D15Q
94
parallel data input 15 inverted
D15
95
parallel data input 15
D14Q
96
parallel data input 14 inverted
D14
97
parallel data input 14
D13Q
98
parallel data input 13 inverted
D13
99
parallel data input 13
V
CCD
100
supply voltage (digital part)
SYMBOL
PIN
DESCRIPTION