September 1989

Philips Semiconductors

Preliminary specification

TV and VTR stereo/dual sound processor with
integrated filters and I

C-bus control

TDA8417

GENERAL DESCRIPTION

The TDA8417 is a processor of stereo/dual language
signals (B/G-standard) for stereo sound television
receivers and VTRs, using the switched-capacitor
technique. The AF signals at the TDA8417 inputs must be
"(L

R)/2" or "language A" on one channel and "R" or

"language B" on the second channel (where L = left and
R = right). The carrier frequency of the second channel is
also modulated by an identification signal (stereo or dual
sound). The device is controlled by a microcomputer via
the two-line, bidirectional I

C-bus.

Features

Use of the switched-capacitor technique for signal
processing

Small amount of peripheral components

Integrated anti-aliasing filters

Low distortion AF signal handling

Integrated de-emphasis with a time constant of 50

Two general purpose output ports

Full ESD protection

QUICK REFERENCE DATA

PACKAGE OUTLINE

20-lead DIL; plastic (SOT146); SOT146-1; 1996 November 18

PARAMETER

CONDITION

SYMBOL

MIN.

TYP.

MAX.

UNIT

Supply voltage (pin 15)

Supply current (pin 15)

AF output signal (RMS value)

(pins 11 to 14)

Weighted signal-to-noise

ratio of the AF output
signals (CCIR 468/3)

W)/W

Crosstalk attenuation

stereo mode at

f = 1 kHz

dual sound mode at

f = 40 Hz to 12.5 kHz

Pilot signal input sensitivity

2.5

Total harmonic distortion

THD

0.1

September 1989

Philips Semiconductors

Preliminary specification

TV and VTR stereo/dual sound processor
with integrated filters and I

C-bus control

TDA8417

PINNING

FUNCTIONAL DESCRIPTION

Anti-aliasing filters

Frequency band limitation is performed by a second order Sallen and Key low-pass filter inserted in the AF signal path
and the identification circuit. This limitation is necessary because of the time-discrete signal processing needed to meet
the Nyquist criterium.

Identification

To enable the identification of the transmitted AF signal (mono, stereo or dual sound), the carrier frequency of the second
channel (E2) is also modulated by an identification signal. The identification signal is a 54.6875 kHz pilot carrier signal
which is 50% amplitude modulated by either a 117.4 Hz signal for stereo transmission or by a 274.1 Hz signal for dual
sound transmission.

The identification section of the circuit consists of a 54 kHz high-pass filter followed by a gain controlled amplifier with an
AM demodulator. The total gain of the high-pass filter and the amplifier is approximately 56 dB. The demodulated
identification signal is filtered by the identification band-pass filters, (117.4 Hz for stereo transmission, 274.1 Hz for dual
sound transmission). The output from either filter is converted to a DC signal by a peak detector and the necessary
hysteresis is performed by a Schmitt-trigger. The resultant DC output signals indicate the status of the transmitter (mono,
stereo or dual sound).

Control port C1

SDA, serial data line (I

C-bus)

SCL, serial clock line (I

C-bus)

Oscillator input (or quartz)

Digital ground (0 V)

Not connected, but reserved

Sound channel input AF2 (E2)

Sound channel input AF1 (E1)

External AF input (E4)

Not connected, but reserved

Output A4 AF 2 output

Output A3 AF 2 output

Output A2 AF 1 output

Output A1 AF 1 output

Supply voltage V

Analogue ground (0 V)

Ripple rejection improvement

Mute input

Control port C2

Not connected, but reserved

September 1989

Philips Semiconductors

Preliminary specification

TV and VTR stereo/dual sound processor
with integrated filters and I

C-bus control

TDA8417

De-matrix and de-emphasis

Depending on the results of the identification circuit (mono, stereo or dual sound) the AF signals at the inputs E1 and E2
are converted to the signals at E1* and E2* as listed in Table 1.

Table 1

Transmitter status

(1)

Note

1. L = left channel signal;

R = right channel signal;
A = first sound channel signal;
B = second sound channel signal

This section of the circuit also performs the de-emphasis (50

s time constant) with a high degree of accuracy.

AF switch

The AF switch is used to switch to either the internal sound sources (E1* or E1* and E2*) or, to the external sound source
(E3 and E4) and is controlled via the I

C-bus.

Source selector

The source selector is used to connect the outputs from the AF switch to the outputs A1 to A4 as illustrated by Table 5.
The selector is controlled via the I

C-bus.

Muting

In this mode the AF outputs A1 to A4 are muted, and the identification circuit is deactivated (mono). The muting is active
after power-on reset or as a result of user control (via the mute input and bit CR3 of the control byte of the mute and port
control register; see Table 4).

Sound mute

If the switch register is set to (00) hex, (sound mute) only the AF outputs are muted, the identification circuit is still active
and can be read (status register) via the I

C-bus.

TRANSMITTER STATUS

E1*

E2*

mono

0.7(L

2(L

stereo

0.7(L

dual sound

0.7A

September 1989

Philips Semiconductors

Preliminary specification

TV and VTR stereo/dual sound processor
with integrated filters and I

C-bus control

TDA8417

Power-on reset

The following actions are carried out by the internal power-on reset when it is active:

The AF outputs are muted

The identification circuit is deactivated (mono)

The control ports (C1 and C2) are set LOW

The I

C-bus transceiver is initialized

When the power-on reset becomes passive the following occurs:

The AF outputs are kept in the mute state until the contents of the switch register are changed from (00) hex via the
I

C-bus

The identification circuit is activated

The control ports are LOW until the mute and control port register is changed (CR bits 10, 11, 20 and 21)

The I

C-bus transceiver is activated

September 1989

Philips Semiconductors

Preliminary specification

TV and VTR stereo/dual sound processor
with integrated filters and I

C-bus control

TDA8417

Control ports

The general purpose control ports C1 and C2 can be set to LOW, HIGH or high impedance via the I

C-bus.

C-bus receiver and data handling

Bus specification

The TDA8417 is controlled, via the bidirectional 2-line I

C-bus, by a microcomputer. The two lines are a serial data line

(SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer
may be initiated only when the bus is not busy.

When the bus is free both lines are HIGH. The data on the SDA line must be stable during the HIGH period of the clock.
The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. The set up and
hold times are specified in the CHARACTERISTICS.

A HIGH-to-LOW transition of the SDA line while SCL is HIGH is defined as the start condition (S).
A LOW-to-HIGH transition of the SDA line while SCL is HIGH is defined as the stop condition (P). The bus receiver will
be reset on the reception of a start condition. The bus is considered to be busy after the start condition. The bus is
considered to be free again after a stop condition.

The I

C-BUS PROTOCOL OF THE TDA8417

The TDA8417 is controlled by a microcomputer and can be written to or read from via the I

C-bus.

The first byte is the address and determines whether the TDA8417 is to be read from (status register) or written to (switch
register or mute and port control register).

Fig.4 Address byte.

Where:

S = start bit

A = acknowledge bit

Read from (TDA8417 is a slave transmitter)

Write to (TDA8417 is a slave receiver)

September 1989

Philips Semiconductors

Preliminary specification

TV and VTR stereo/dual sound processor
with integrated filters and I

C-bus control

TDA8417

Reading the TDA8417

Reading the TDA8417 means reading the status register and the data stream will have the format as illustrated in
Fig.5 below.

The second byte, the contents of the status register, is defined by Table 2.

Table 2

Status register

Where:

The truth table for the ST and DS bits is provided by Table 3.

Table 3

Truth table for ST and DS bits

PONRES

power on reset

1 =

power on reset active after switching on or power breakdown

0 =

after reading the status register

stereo transmission

dual sound transmission

DEFINITION

mono transmission

dual sound transmission

stereo transmission

Fig.5 Read format.

Where:

S = start bit

A = acknowledge bit

P = stop bit

September 1989

Philips Semiconductors

Preliminary specification

TV and VTR stereo/dual sound processor
with integrated filters and I

C-bus control

TDA8417

Writing to the TDA8417

Writing to the TDA8417 means, writing to either the switch register or the mute and port control register. Which one is to
be addressed is defined by the subaddress (the second byte) as illustrated by Fig.6 below. The third byte contains the
information to be stored in the specified register.

Table 4 defines the contents of the mute and port control register.

Table 4

Mute and port control register

(1)

Note

1. X = don't care

D4
CR3

D3
CR21

D2
CR20

D1
CR11

D0
CR10

DEFINITION

control port C1 = LOW

control port C1 = HIGH

control port C1 = high impedance

control port C2 = LOW

control port C2 = HIGH

control port C2 = high impedance

mute is active when pin 18 is LOW (default)

mute is active when pin 18 is HIGH

Fig.6 Write format.

Where:

S = start bit

A = acknowledge bit

P = stop bit

September 1989

Philips Semiconductors

Preliminary specification

TV and VTR stereo/dual sound processor
with integrated filters and I

C-bus control

TDA8417

Table 5 defines the contents of the switch register.

Table 5

Switch register

Where:

SWITCH
REGISTER

INPUT

OUTPUT

(HEX)

sound mute

no signal

(00)

mono

(10)

stereo

(2A)

sound A

DS A

(10)

sound B

DS A

(1F)

dual sound

DS A

(1C)

DS A

(13)

dual sound

DS A

(12)

mix

DS A

(18)

DS A

(1A)

DS A

(1B)

DS A

(1E)

external

(7F)

mono

stereo

DS =

dual sound

right

left

R)/2

sound A

sound B

September 1989

Philips Semiconductors

Preliminary specification

TV and VTR stereo/dual sound processor
with integrated filters and I

C-bus control

TDA8417

RATINGS

Limiting values in accordance with Absolute Maximum System (IEC 134)

Note

1. Supply voltage may be applied only when both pins 5 and 15 are connected to ground.

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

Supply voltage

(1)

= V

15-16

13.2

Output current

pins 11, 12, 13, 14

pins 1 and 19 (sink)

(source)

Input voltage (not pin 18)

Input voltage pin 18

= V

18-16

Output voltage

Total power dissipation

tot

ESD protection (each pin) (0

/200 pF)

500

Operating ambient temperature range

amb

Storage temperature range

stg

150

September 1989

Philips Semiconductors

Preliminary specification

TV and VTR stereo/dual sound processor
with integrated filters and I

C-bus control

TDA8417

CHARACTERISTICS

= 12 V; T

amb

= 25

C. Measurement conditions (see Fig.7): reference level is 1 V (RMS); test

frequency = 3.183 kHz; noise measurement in accordance with DIN 45405, CCIR 468-3; oscillator
frequency = 10 MHz; pre-emphasis time constant = 50

PARAMETER

CONDITIONS

SYMBOL

MIN.

TYP.

MAX.

UNIT

Supplies

Supply voltage

= V

15-16

10.8

13.2

Supply current

= I

DC levels

pins 7 - 14 and 17

n-16

3.25

pin 4

4-5

Bus transceiver

Clock frequency

C-bus)

note 1

CLK

0.7

100

kHz

Clock SCL (pin 3)

Input voltage LOW

0.3

1.5

Input voltage HIGH

Timing LOW period

LOW

4.7

Timing HIGH period

HIGH

Rise time

Fall time

0.3

Input current LOW

Input current HIGH

Data SDA (pin 2)

Input voltage LOW

0.3

1.5

Input voltage HIGH

Rise time

Fall time

0.3

Data set-up time

SU; DAT

0.25

Input current LOW

Input current HIGH

Output current LOW

Mute port (pin 18)

Input voltage LOW

note 2

0.3

1.5

Input voltage HIGH

note 2

September 1989

Philips Semiconductors

Preliminary specification

TV and VTR stereo/dual sound processor
with integrated filters and I

C-bus control

TDA8417

Control ports

(pins 1 and 19)

Output voltage LOW

note 3

0.5

Output voltage HIGH

note 3

4.5

Output impedance

3-state

Output current LOW

Output current HIGH

AF stages and identification
(pins 7 to 14)

Input impedance

(pins 7 to 9)

150

200

Input voltage E1

0.7

Input voltage E2

Input voltage E2 for

identification
active (RMS value)

note 4

2.5

Voltage gain 7-15/output

note 5

5.9

6.1

Voltage gain 8-15/output

note 5

8.9

9.1

Voltage gain

9-15/output

0.1

Crosstalk attenuation

notes 6 to 8

dual mode

stereo mode

Output impedance

(pins 11 to 14)

400

500

600

De-emphasis time

constant

note 9

49.5

50.5

Frequency response

note 6

Total harmonic

distortion

note 10

THD

0.2

Capacitive load

(pins 11 to 14)

1.5

Output signal

(RMS value)
(pins 11 to 14)

THD

0.2%

Ripple rejection

note 11

Noise from I

C-bus

Signal-to-noise ratio

W)/W

dBV
CCIR

PARAMETER

CONDITIONS

SYMBOL

MIN.

TYP.

MAX.

UNIT

September 1989

Philips Semiconductors

Preliminary specification

TV and VTR stereo/dual sound processor
with integrated filters and I

C-bus control

TDA8417

Notes to the characteristics

1. Full specification of I

C-bus will be supplied on request.

2. Programmable mute state. If the CR3 bit of the mute and port control register is LOW, the mute is active LOW; if it

is HIGH, the mute input is active HIGH.

3. Output current I

1 mA.

4. Unmodulated.

5. f = 400 Hz; R

= 1 M

6. 40 Hz

15 kHz.

7. In dual mode: A(B)-signal into B(A)-channel.

In stereo mode: R-signal into left, L-signal = 0, reference is 1 V RMS.

8. Source impedance

1 k

9. Equivalent to an output level of

3 dB at f = 3.183 kHz.

10. V

= 1 V RMS; f =1 kHz.

11. Test circuit see Fig.7.

Signal suppression

during mute

note 6

Change of output

DC voltage level
between any two
modes

Oscillator

Oscillator frequency

OSC

MHz

External oscillator

signal (RMS value)

4-5

1.7

Quartz series resistor

100

Impedance

1.2

j9.3

Capacitance

OSC

1.7

PARAMETER

CONDITIONS

SYMBOL

MIN.

TYP.

MAX.

UNIT

September 1989

Philips Semiconductors

Preliminary specification

TV and VTR stereo/dual sound processor
with integrated filters and I

C-bus control

TDA8417

PACKAGE OUTLINE

UNIT

max.

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

EIAJ

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT146-1

92-11-17
95-05-24

min.

max.

1.73
1.30

0.53
0.38

0.36
0.23

26.92
26.54

6.40
6.22

3.60
3.05

0.254

2.54

7.62

8.25
7.80

10.0

8.3

2.0

4.2

0.51

3.2

0.068
0.051

0.021
0.015

0.014
0.009

1.060
1.045

0.25
0.24

0.14
0.12

0.01

0.10

0.30

0.32
0.31

0.39
0.33

0.078

0.17

0.020

0.13

SC603

(e )

seating plane

pin 1 index

10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

(1)

DIP20: plastic dual in-line package; 20 leads (300 mil)

SOT146-1

September 1989

Philips Semiconductors

Preliminary specification

TV and VTR stereo/dual sound processor
with integrated filters and I

C-bus control

TDA8417

SOLDERING

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

Soldering by dipping or by wave

The maximum permissible temperature of the solder is
260

C; solder at this temperature must not be in contact

with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg max

). If the

printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

Repairing soldered joints

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300

C it may remain in

contact for up to 10 seconds. If the bit temperature is
between 300 and 400

C, contact may be up to 5 seconds.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PURCHASE OF PHILIPS I

C COMPONENTS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

C components conveys a license under the Philips' I

C patent to use the

components in the I

C system provided the system conforms to the I

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

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