2002 Jan 21

Philips Semiconductors

Product specification

Full bridge vertical deflection output circuit
in LVDMOS

TDA8359J

FEATURES

Few external components required

High efficiency fully DC-coupled vertical bridge output
circuit

Vertical flyback switch with short rise and fall times

Built-in guard circuit

Thermal protection circuit

Improved EMC performance due to differential inputs.

GENERAL DESCRIPTION

The TDA8359J is a power circuit for use in 90

and 110

colour deflection systems for 25 to 200 Hz field
frequencies, and for 4 : 3 and 16 : 9 picture tubes. The IC
contains a vertical deflection output circuit, operating as a
high efficiency class G system. The full bridge output
circuit allows DC coupling of the deflection coil in
combination with single positive supply voltages.

The IC is constructed in a Low Voltage DMOS (LVDMOS)
process that combines bipolar, CMOS and DMOS
devices. DMOS transistors are used in the output stage
because of absence of second breakdown.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

supply voltage

7.5

flyback supply voltage

q(P)(av)

average quiescent supply current

during scan

q(FB)(av)

average quiescent flyback supply current

during scan

tot

total power dissipation

Inputs and outputs

i(p-p)

input voltage (peak-to-peak value)

1000

1500

o(p-p)

output current (peak-to-peak value)

3.2

Flyback switch

o(peak)

maximum (peak) output current

1.5 ms

1.8

Thermal data; in accordance with IEC 60747-1

stg

storage temperature

150

amb

ambient temperature

junction temperature

150

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA8359J

DBS9P

plastic DIL-bent-SIL power package; 9 leads (lead length
12/11 mm); exposed die pad

SOT523-1

2002 Jan 21

Philips Semiconductors

Product specification

Full bridge vertical deflection output circuit
in LVDMOS

TDA8359J

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MGL862

INPUT

AND

FEEDBACK

CIRCUIT

GUARD

CIRCUIT

TDA8359J

INA

INB

GND

GUARD

VFB

VI(bias)

OUTB

OUTA

FEEDB

Vi(p-p)

PINNING

SYMBOL

PIN

DESCRIPTION

INA

input A

INB

input B

supply voltage

OUTB

output B

GND

ground

flyback supply voltage

OUTA

output A

GUARD

guard output

FEEDB

feedback input

handbook, halfpage

INA

INB

OUTB

GND

VFB

OUTA

GUARD

FEEDB

TDA8359J

MGL863

Fig.2 Pin configuration.

The exposed die pad is connected to pin GND.

2002 Jan 21

Philips Semiconductors

Product specification

Full bridge vertical deflection output circuit
in LVDMOS

TDA8359J

FUNCTIONAL DESCRIPTION

Vertical output stage

The vertical driver circuit has a bridge configuration. The
deflection coil is connected between the complimentary
driven output amplifiers. The differential input circuit is
voltage driven. The input circuit is specially designed for
direct connection to driver circuits delivering a differential
signal but it is also suitable for single-ended applications.
For processors with output currents, the currents are
converted to voltages by the conversion resistors
R

CV1

and R

CV2

(see Fig.5) connected to pins INA

and INB. The differential input voltage is compared with
the voltage across the measuring resistor R

, providing

feedback information. The voltage across R

proportional with the output current. The relationship
between the differential input voltage and the output
current is defined by:

i(dif)(p-p)

= I

o(p-p)

i(dif)(p-p)

= V

INA

INB

The output current should not exceed 3.2 A (p-p) and is
determined by the value of R

and R

. The allowable

input voltage range is 100 mV to 1.6 V for each input. The
formula given does not include internal bondwire
resistances. Depending on the values of R

and the

internal bondwire resistance (typical value of 50 m

) the

actual value of the current in the deflection coil will be
approximately 5% lower than calculated.

Flyback supply

The flyback voltage is determined by the flyback supply
voltage V

. The principle of two supply voltages (class G)

allows to use an optimum supply voltage V

for scan and

an optimum flyback supply voltage V

for flyback, thus

very high efficiency is achieved. The available flyback
output voltage across the coil is almost equal to V

, due

to the absence of a coupling capacitor which is not
required in a bridge configuration. The very short rise and
fall times of the flyback switch are determined mainly by
the slew rate value of more than 300 V/

Protection

The output circuit contains protection circuits for:

Too high die temperature

Overvoltage of output A.

Guard circuit

A guard circuit with output pin GUARD is provided.

The guard circuit generates a HIGH-level during the
flyback period. The guard circuit is also activated for one
of the following conditions:

During thermal protection (T

170

During an open-loop condition.

The guard signal can be used for blanking the picture tube
and signalling fault conditions. The vertical
synchronization pulses of the guard signal can be used by
an On Screen Display (OSD) microcontroller.

Damping resistor compensation

HF loop stability is achieved by connecting a damping
resistor R

across the deflection coil. The current values

in R

during scan and flyback are significantly different.

Both the resistor current and the deflection coil current flow
into measuring resistor R

, resulting in a too low deflection

coil current at the start of the scan.

The difference in the damping resistor current values
during scan and flyback have to be externally
compensated in order to achieve a short settling time. For
that purpose a compensation resistor R

CMP

in series with

a zener diode is connected between pins OUTA and INA
(see Fig.4). The zener diode voltage value should be
equal to V

. The value of R

CMP

is calculated by:

where:

loss(FB)

is the voltage loss between pins V

and OUTA

at flyback

coil

is the deflection coil resistance

is the voltage of zener diode D4.

CMP

loss FB

(

)

(

)

CV1

loss FB

(

)

coil peak

(

)

coil

(

)

------------------------------------------------------------------------------------------------------------

2002 Jan 21

Philips Semiconductors

Product specification

Full bridge vertical deflection output circuit
in LVDMOS

TDA8359J

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).

Notes

1. When the voltage at pin OUTA supersedes 70 V the circuit will limit the voltage.

2. At T

j(max)

3. Equivalent to 200 pF capacitance discharge through a 0

resistor.

4. Equivalent to 100 pF capacitance discharge through a 1.5 k

resistor.

5. Internally limited by thermal protection at T

170

THERMAL CHARACTERISTICS
In accordance with IEC 60747-1.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

supply voltage

flyback supply voltage

DC voltage

pin OUTA

note 1

pin OUTB

pins INA, INB, GUARD and FEEDB

0.5

DC current

pins OUTA and OUTB

during scan (p-p)

3.2

pins OUTA and OUTB

at flyback (peak); t

1.5 ms

1.8

pins INA, INB, GUARD and FEEDB

latch-up current

current into any pin; pin voltage is
1.5

; note 2

200

current out of any pin; pin voltage is

1.5

; note 2

200

electrostatic handling voltage

machine model; note 3

500

human body model; note 4

5000

tot

total power dissipation

stg

storage temperature

150

amb

ambient temperature

junction temperature

note 5

150

SYMBOL

PARAMETER

CONDITIONS

MAX.

UNIT

th(j-c)

thermal resistance from junction to case

K/W

th(j-a)

thermal resistance from junction to ambient

in free air

K/W

2002 Jan 21

Philips Semiconductors

Product specification

Full bridge vertical deflection output circuit
in LVDMOS

TDA8359J

CHARACTERISTICS
V

= 12 V; V

= 45 V; f

vert

= 50 Hz; V

I(bias)

= 880 mV; T

amb

= 25

C; measured in test circuit of Fig.3; unless otherwise

specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

operating supply voltage

7.5

flyback supply voltage

note 1

q(P)(av)

average quiescent supply current

during scan

q(P)

quiescent supply current

no signal; no load

q(FB)(av)

average quiescent flyback supply
current

during scan

Inputs A and B

i(p-p)

input voltage (peak-to-peak value)

note 2

1000

1500

I(bias)

input bias voltage

note 2

100

880

1600

I(bias)

input bias current

source

Outputs A and B

loss(1)

voltage loss first scan part

note 3

= 1.1 A

4.5

= 1.6 A

6.6

loss(2)

voltage loss second scan part

note 4

1.1 A

3.3

1.6 A

4.8

o(p-p)

output current
(peak-to-peak value)

3.2

linearity error

o(p-p)

= 3.2 A; notes 5 and 6

adjacent blocks

non adjacent blocks

offset

offset voltage

across R

; V

i(dif)

= 0 V

I(bias)

= 200 mV

I(bias)

= 1 V

offset(T)

offset voltage variation with
temperature

across R

; V

i(dif)

= 0 V

V/K

DC output voltage

i(dif)

= 0 V

0.5

v(ol)

open-loop voltage gain

notes 7 and 8

3dB(h)

high

3 dB cut-off frequency

open-loop

kHz

voltage gain

note 9

v(T)

voltage gain variation with the
temperature

PSRR

power supply rejection ratio

note 10

2002 Jan 21

Philips Semiconductors

Product specification

Full bridge vertical deflection output circuit
in LVDMOS

TDA8359J

Notes

1. To limit V

OUTA

to 68 V, V

must be 66 V due to the voltage drop of the internal flyback diode between pins OUTA

and V

at the first part of the flyback.

2. Allowable input range for both inputs: V

I(bias)

+ V

< 1600 mV and V

I(bias)

> 100 mV.

3. This value specifies the sum of the voltage losses of the internal current paths between pins V

and OUTA, and

between pins OUTB and GND. Specified for T

= 125

C. The temperature coefficient for V

loss(1)

is a positive value.

4. This value specifies the sum of the voltage losses of the internal current paths between pins V

and OUTB, and

between pins OUTA and GND. Specified for T

= 125

C. The temperature coefficient for V

loss(2)

is a positive value.

5. The linearity error is measured for a linear input signal without S-correction and is based on the `on screen'

measurement principle. This method is defined as follows. The output signal is divided in 22 successive equal time
parts. The 1st and 22nd parts are ignored, and the remaining 20 parts form 10 successive blocks k. A block consists
of two successive parts. The voltage amplitudes are measured across R

, starting at k = 1 and ending at k = 10,

where V

and V

k+1

are the measured voltages of two successive blocks. V

min

, V

max

and V

avg

are the minimum,

maximum and average voltages respectively. The linearity errors are defined as:

% (adjacent blocks)

% (non adjacent blocks)

6. The linearity errors are specified for a minimum input voltage of 300 mV (p-p). Lower input voltages lead to voltage

dependent S-distortion in the input stage.

8. Pin FEEDB not connected.

10. V

P(ripple)

= 500 mV (RMS value); 50 Hz < f

P(ripple)

< 1 kHz; measured across R

11. This value specifies the internal voltage loss of the current path between pins V

and OUTA.

Flyback switch

o(peak)

maximum (peak) output current

1.5 ms

1.8

loss(FB)

voltage loss at flyback

note 11

= 1.1 A

7.5

8.5

= 1.6 A

Guard circuit

O(grd)

guard output voltage

O(grd)

= 100

O(grd)(max)

allowable guard voltage

maximum leakage current
I

L(max)

= 10

O(grd)

output current

O(grd)

= 0 V; not active

O(grd)

= 4.5 V; active

2.5

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

avg

--------------------------

100

max

min

avg

-------------------------------

100

v ol

( )

OUTA

OUTB

FEEDB

OUTB

--------------------------------------------

FEEDB

OUTB

INA

INB

--------------------------------------------

2002

Jan

Philips Semiconductors

Product specification

Full br

idge v

r
tical deflection output circuit

in L

VDMOS

TD
A8359J

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ok, full pagewidth

VP = 14 V

VFB = 30 V

deflection
coil
5 mH
6

(W66ESF)

0.5

RD1
270

RCMP
680 k

TV SIGNAL

PROCESSOR

2.2 nF

CD
47 nF

100 nF

(14 V)

C1
47

(100 V)

100 nF

C2
220

(25 V)

RD2
1.5

INA

INB

FEEDB

GUARD

RGRD

12 k

RCV1

2.2 k

(1%)

RCV2

2.2 k

(1%)

2.7 k

MBL364

INPUT

AND

FEEDBACK

CIRCUIT

GUARD

CIRCUIT

TDA8359J

GND

VFB

OUTB

OUTA

VI(bias)

Vi(p-p)

Fig.4 Application diagram.

vert

= 50 Hz; t

= 640

s; I

I(bias)

= 400

A; I

i(p-p)

= 290

A; I

o(p-p)

= 2.4 A.

2002 Jan 21

Philips Semiconductors

Product specification

Full bridge vertical deflection output circuit
in LVDMOS

TDA8359J

calculation

Most Philips brand TV signal processors have outputs in
the form of current. This current has to be converted to a
voltage by using resistors at the input of the TDA8359J
(R

CV1

and R

CV2

). The differential voltage across these

resistors can be calculated by:

For calculating the measuring resistor R

, use the

differential input voltage (V

i(dif)(p-p)

). This voltage can also

be measured between pins INA and INB (see Fig.5). The
calculation for R

is:

XAMPLE

Measured or given values: I

I(bias)

= 400

A; I

i1(p-p)

= I

i2(p-p)

290

The differential input voltage will be:

Supply voltage calculation

For calculating the minimum required supply voltage,
several specific application parameter values have to be
known. These parameters are the required maximum
(peak) deflection coil current I

coil(peak)

, the coil impedance

coil

and L

coil

, and the measuring resistance of R

. The

required maximum (peak) deflection coil current should
also include overscan.

The deflection coil resistance has to be multiplied by 1.2 in
order to take account of hot conditions.

Chapter "Characteristics" supplies values for voltage
losses of the vertical output stage. For the first part of the
scan, the voltage loss is given by V

loss(1)

. For the second

part of the scan, the voltage loss is given by V

loss(2)

The voltage drop across the deflection coil during scan is
determined by the coil impedance. For the first part of the
scan the inductive contribution and the ohmic contribution
to the total coil voltage drop are of opposite sign, while for
the second part of the scan the inductive part and the
ohmic part have the same sign.

For the vertical frequency the maximum frequency
occurring must be applied to the calculations.

The required power supply voltage V

for the first part of

the scan is given by:

The required power supply voltage V

for the second part

of the scan is given by:

The minimum required supply voltage V

shall be the

highest of the two values V

P(1)

and V

P(2)

. Spread in supply

voltage and component values also has to be taken into
account.

i dif

(

)

(

)

i1 p

(

)

CV1

i2 p

(

)

(

)

CV2

i dif

(

)

(

)

o p

(

)

----------------------------

handbook, halfpage

TV SIGNAL

PROCESSOR

2.2 nF

INA

INB

RCV1

2.2 k

RCV2

2.2 k

II(bias)

Ii1(p-p)

Ii2(p-p)

MBL366

Fig.5 Input Circuit

i dif

(

)

(

)

290

2.2k

290

2.2k

(

)

1.27V

P 1

( )

coil peak

(

)

coil

(

)

coil

coil peak

(

)

vert max

(

)

loss 1

( )

P 2

( )

coil peak

(

)

coil

(

)

coil

coil peak

(

)

vert max

(

)

loss 2

( )

2002 Jan 21

Philips Semiconductors

Product specification

Full bridge vertical deflection output circuit
in LVDMOS

TDA8359J

Flyback supply voltage calculation

If the flyback time is known, the required flyback supply
voltage can be calculated by the simplified formula:

where:

The flyback supply voltage calculated this way is
approximately 5% to 10% higher than required.

Calculation of the power dissipation of the vertical
output stage

The IC total power dissipation is given by the formula:

tot

= P

sup

The power to be supplied is given by the formula:

In this formula 0.3 [W] represents the average value of the
losses in the flyback supply.

The average external load power dissipation in the
deflection coil and the measuring resistor is given by the
formula:

Example

Table 1

Application values

Table 2

Calculated values

Heatsink calculation

The value of the heatsink can be calculated in a standard
way with a method based on average temperatures. The
required thermal resistance of the heatsink is determined
by the maximum die temperature of 150

C. In general we

recommend to design for an average die temperature
not exceeding 130

XAMPLE

Measured or given values: P

tot

= 6 W; T

amb(max)

= 40

= 120

C; R

th(j-c)

= 4 K/W; R

th(c-h)

= 2 K/W.

The required heatsink thermal resistance is given by:

When we use the values given we find:

The heatsink temperature will be:

= T

amb

+ (R

th(h-a)

tot

) = 40 + (7

6) = 82

SYMBOL

VALUE

UNIT

coil(peak)

1.2

coil(p-p)

2.4

coil

0.6

vert

640

coil p p

(

)

coil

---------------------------

coil

---------------------------

sup

coil peak

(

)

------------------------

0.015 [A]

0.3 [W]

coil peak

(

)

(

)

--------------------------------

coil

(

)

SYMBOL

VALUE

UNIT

+ R

coil

(hot)

7.8

vert

0.02

0.000641

sup

8.91

3.74

tot

5.17

th h

(

)

amb

tot

------------------------

th j

(

)

th c

(

)

(

)

th h

(

)

120

----------------------

(

)

7 K/W

2002 Jan 21

Philips Semiconductors

Product specification

Full bridge vertical deflection output circuit
in LVDMOS

TDA8359J

PACKAGE OUTLINE

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

EIAJ

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

2. Plastic surface within circle area D1 may protrude 0.04 mm maximum.

SOT523-1

10 mm

scale

non-concave

98-11-12
00-07-03

DBS9P: plastic DIL-bent-SIL power package; 9 leads (lead length 12/11 mm); exposed die pad

SOT523-1

view B: mounting base side

UNIT

(1)

2.7
2.3

(2)

0.80
0.65

0.58
0.48

13.2
12.8

(2)

6.2
5.8

3.5

2.54

1.27

5.08

4.85

(1)

14.7
14.3

(1)

1.65
1.10

11.4
10.0

6.7
5.5

4.5
3.7

3.4
3.1

1.15
0.85

17.5
16.3

2.8

0.8

3.8
3.6

3.0
2.0

12.4
11.0

0.02

0.3

2002 Jan 21

Philips Semiconductors

Product specification

Full bridge vertical deflection output circuit
in LVDMOS

TDA8359J

SOLDERING

Introduction to soldering through-hole mount
packages

This text gives a brief insight to wave, dip and manual
soldering. A more in-depth account of soldering ICs can be
found in our

"Data Handbook IC26; Integrated Circuit

Packages" (document order number 9398 652 90011).

Wave soldering is the preferred method for mounting of
through-hole mount IC packages on a printed-circuit
board.

Soldering by dipping or by solder wave

The maximum permissible temperature of the solder is
260

C; solder at this temperature must not be in contact

with the joints for more than 5 seconds.

The total contact time of successive solder waves must not
exceed 5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg(max)

). If the

printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300

C it may remain in contact for up to

10 seconds. If the bit temperature is between
300 and 400

C, contact may be up to 5 seconds.

Suitability of through-hole mount IC packages for dipping and wave soldering methods

Note

1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

PACKAGE

SOLDERING METHOD

DIPPING

WAVE

DBS, DIP, HDIP, SDIP, SIL

suitable

(1)

2002 Jan 21

Philips Semiconductors

Product specification

Full bridge vertical deflection output circuit
in LVDMOS

TDA8359J

DATA SHEET STATUS

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

DATA SHEET STATUS

(1)

PRODUCT

STATUS

(2)

DEFINITIONS

Objective data

Development

This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.

Preliminary data

Qualification

This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.

Product data

Production

This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.

DEFINITIONS

Short-form specification

The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition

Limiting values given are in

accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information

Applications that are

described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.

DISCLAIMERS

Life support applications

These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes

Philips Semiconductors

reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

SCA74

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Philips Semiconductors a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

Printed in The Netherlands

753504/25/02/pp

Date of release:

2002 Jan 21

Document order number:

9397 750 08868

Document Outline

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Document Outline

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