Document Outline
- FEATURES
- GENERAL DESCRIPTION
- QUICK REFERENCE DATA
- ORDERING INFORMATION
- BLOCK DIAGRAM
- PINNING
- FUNCTIONAL DESCRIPTION
- LIMITING VALUES
- THERMAL CHARACTERISTICS
- CHARACTERISTICS
- APPLICATION INFORMATION
- INTERNAL PIN CONFIGURATION
- PACKAGE OUTLINE
- SOLDERING
- DATA SHEET STATUS
- DEFINITIONS
- DISCLAIMERS
DATA SHEET
Product specification
Supersedes data of 1999 Dec 22
2002 Sep 25
INTEGRATED CIRCUITS
TDA8358J
Full bridge vertical deflection output
circuit in LVDMOS with east-west
amplifier
2002 Sep 25
2
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
TDA8358J
FEATURES
Few external components required
High efficiency fully DC-coupled vertical bridge output
circuit
Vertical flyback switch with short rise and fall times
Built-in guard circuit
Thermal protection circuit
Improved EMC performance due to differential inputs
East-west output stage.
GENERAL DESCRIPTION
The TDA8358J is a power circuit for use in 90
and 110
colour deflection systems for 25 to 200 Hz field
frequencies, and for 4 : 3 and 16 : 9 picture tubes. The IC
contains a vertical deflection output circuit, operating as a
high efficiency class G system. The full bridge output
circuit allows DC coupling of the deflection coil in
combination with single positive supply voltages.
The east-west output stage is able to supply the sink
current for a diode modulator circuit.
The IC is constructed in a Low Voltage DMOS (LVDMOS)
process that combines bipolar, CMOS and DMOS
devices. DMOS transistors are used in the output stage
because of absence of second breakdown.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
P
supply voltage
7.5
12
18
V
V
FB
flyback supply voltage
2
V
P
45
66
V
I
q(P)(av)
average quiescent supply current
during scan
-
10
15
mA
I
q(FB)(av)
average quiescent flyback supply current
during scan
-
-
10
mA
P
tot
total power dissipation
-
-
15
W
Inputs and outputs
V
i(p-p)
input voltage (peak-to-peak value)
-
1000
1500
mV
I
o(p-p)
output current (peak-to-peak value)
-
-
3.2
A
Flyback switch
I
o(peak)
maximum (peak) output current
t
1.5 ms
-
-
1.8
A
East-west amplifier
V
o
output voltage
-
-
68
V
V
I(bias)
input bias voltage
2
-
3.2
V
I
o
output current
-
-
750
mA
Thermal data; in accordance with IEC 747-1
T
stg
storage temperature
-
55
-
+150
C
T
amb
ambient temperature
-
25
-
+85
C
T
j
junction temperature
-
-
+150
C
2002 Sep 25
3
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
TDA8358J
ORDERING INFORMATION
BLOCK DIAGRAM
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
TDA8358J
DBS13P
plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm)
SOT141-6
handbook, full pagewidth
MGL866
INPUT
AND
FEEDBACK
CIRCUIT
GUARD
CIRCUIT
TDA8358J
12
10
4
6
7
2
8
5
1
11
9
3
INA
INB
INEW
VGND
EWGND
GUARD
VP
VFB
VI(bias)
Vi(p-p)
VI(bias)
0
Vi(p-p)
0
OUTB
OUTEW
OUTA
FEEDB
COMP.
CIRCUIT
13
COMP
II(av)
Ii(p-p)
0
M5
M2
M4
M1
M3
M6
D2
D3
D1
Fig.1 Block diagram.
2002 Sep 25
4
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
TDA8358J
PINNING
FUNCTIONAL DESCRIPTION
Vertical output stage
The vertical driver circuit has a bridge configuration. The
deflection coil is connected between the complimentary
driven output amplifiers. The differential input circuit is
voltage driven. The input circuit is specially designed for
direct connection to driver circuits delivering a differential
signal but it is also suitable for single-ended applications.
For processors with output currents, the currents are
converted to voltages by the conversion resistors
R
CV1
and R
CV2
(see Fig.3) connected to pins INA
and INB. The differential input voltage is compared with
the voltage across the measuring resistor R
M
, thus
providing feedback information. The voltage across R
M
is
proportional with the output current. The relationship
between the differential input voltage and the output
current is defined by:
V
i(dif)(p-p)
=
I
o(p-p)
R
M
; V
i(dif)(p-p)
=
V
INA
-
V
INB
The output current should not exceed 3.2 A (p-p) and is
determined by the value of R
M
and R
CV
. The allowable
input voltage range is 100 mV to 1.6 V for each input. The
formula given does not include internal bondwire
resistances. Depending on the value of R
M
and the internal
bondwire resistance (typical value 50 m
) the actual value
of the current in the deflection coil will be about 5% lower
than calculated.
Flyback supply
The flyback voltage is determined by the flyback supply
voltage V
FB
. The principle of two supply voltages (class G)
allows to use an optimum supply voltage V
P
for scan and
an optimum flyback supply voltage V
FB
for flyback, thus
very high efficiency is achieved. The available flyback
output voltage across the coil is almost equal to V
FB
, due
to the absence of a coupling capacitor which is not
required in a bridge configuration. The very short rise and
fall times of the flyback switch are determined mainly by
the slew rate value of more than 300 V/
s.
Protection
The output circuit contains protection circuits for:
Too high die temperature
Overvoltage of output A.
SYMBOL
PIN
DESCRIPTION
INA
1
positive vertical input
INB
2
negative vertical input
V
P
3
supply voltage
OUTB
4
vertical output voltage B
INEW
5
east-west input voltage
VGND
6
vertical ground
EWGND
7
east-west ground
OUTEW
8
east-west output voltage
V
FB
9
flyback supply voltage
OUTA
10
vertical output voltage A
GUARD
11
guard output voltage
FEEDB
12
input measuring resistor
COMP
13
input compensation current
handbook, halfpage
TDA8358J
MGL867
1
2
3
4
5
6
7
8
9
10
11
12
13
INA
INB
VP
OUTB
INEW
VGND
EWGND
OUTEW
VFB
OUTA
GUARD
FEEDB
COMP
Fig.2 Pin configuration.
The die has been glued to the metal block of the package. If the metal
block is not insulated from the heatsink, the heatsink shall only be
connected directly to pin VGND.
2002 Sep 25
5
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
TDA8358J
Guard circuit
A guard circuit with output pin GUARD is provided.
The guard circuit generates a HIGH-level during the
flyback period. The guard circuit is also activated for one
of the following conditions:
During thermal protection (T
j
170
C)
During an open-loop condition.
The guard signal can be used for blanking the picture tube
and signalling fault conditions. The vertical
synchronization pulses of the guard signal can be used by
an On Screen Display (OSD) microcontroller.
Damping resistor compensation
HF loop stability is achieved by connecting a damping
resistor R
D1
(see Fig.4) across the deflection coil. The
current values in R
D1
during scan and flyback are
significantly different. Both the resistor current and the
deflection coil current flow into measuring resistor R
M
,
resulting in a too low deflection coil current at the start of
the scan.
The difference in the damping resistor current values
during scan and flyback have to be externally
compensated in order to achieve a short settling time.
For that purpose a compensation resistor R
CMP
is
connected between pins OUTA and COMP. The value of
R
CMP
is calculated by:
where:
R
coil
is the coil resistance
V
loss(FB)
is the voltage loss between pins V
FB
and OUTA
at flyback.
East-west amplifier
The east-west amplifier is current driven. The output can
only sink currents of the diode modulator circuit.
A feedback resistor (see Fig.4) has to be connected
between the input and output of the inverting east-west
amplifier in order to convert the east-west correction input
current into an output voltage. The output voltage of the
east-west circuit at pin OUTEW is given by:
V
OUTEW
I
INEW
R
EWF
+ V
INEW
The maximum output voltage is V
o(max)
= 68 V, while the
maximum output current of the circuit is I
o(max)
= 750 mA.
R
CMP
V
FB
V
loss FB
(
)
V
P
(
)
R
D1
R
S
300
+
(
)
V
FB
V
loss FB
(
)
I
coil peak
(
)
R
coil
(
)
R
M
-------------------------------------------------------------------------------------------------------------
=
2002 Sep 25
6
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
TDA8358J
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
Notes
1. When the voltage at pin OUTA supersedes 70 V the circuit will limit the voltage.
2. Equivalent to 200 pF capacitance discharge through a 0
resistor.
3. Equivalent to 100 pF capacitance discharge through a 1.5 k
resistor.
4. For repetitive time durations of t < 0.1 ms or a non-repetitive time duration of t < 5 ms the maximum (peak) east-west
power dissipation P
EW(peak)
= 15 W.
5. Internally limited by thermal protection at T
j
170
C.
THERMAL CHARACTERISTICS
In accordance with IEC 747-1.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
P
supply voltage
-
18
V
V
FB
flyback supply voltage
-
68
V
V
VGND-EWGND
voltage difference between
pins VGND and EWGND
-
0.3
V
V
n
DC voltage
pins OUTA and OUTEW
note 1
-
68
V
pin OUTB
-
V
P
V
pins INA, INB, INEW, GUARD,
FEEDB, and COMP
-
0.5
V
P
V
I
n
DC current
pins OUTA and OUTB
during scan (p-p)
-
3.2
A
pins OUTA and OUTB
at flyback (peak); t
1.5 ms
-
1.8
A
pins INA, INB, INEW, GUARD,
FEEDB, and COMP
-
20
+20
mA
pin OUTEW
-
750
mA
I
lu
latch-up current
input current into any pin;
pin voltage is 1.5
V
P
; T
j
= 150
C
-
+200
mA
input current out of any pin;
pin voltage is
-
1.5
V
P
; T
j
= 150
C
-
200
-
mA
V
es
electrostatic handling voltage
machine model; note 2
-
350
+350
V
human body model; note 3
-
4000
+4000 V
P
EW
east-west power dissipation
note 4
-
4
W
P
tot
total power dissipation
-
15
W
T
stg
storage temperature
-
55
+150
C
T
amb
ambient temperature
-
25
+85
C
T
j
junction temperature
note 5
-
+150
C
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
R
th(j-c)
thermal resistance from junction to case
4
K/W
R
th(j-a)
thermal resistance from junction to ambient
in free air
40
K/W
2002 Sep 25
7
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
TDA8358J
CHARACTERISTICS
V
P
= 12 V; V
FB
= 45 V; f
vert
= 50 Hz; V
I(bias)
= 880 mV; T
amb
= 25
C; measured in test circuit of Fig.3; unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
P
operating supply voltage
7.5
12
18
V
V
FB
flyback supply voltage
note 1
2
V
P
45
66
V
I
q(P)(av)
average quiescent supply current
during scan
-
10
15
mA
I
q(P)
quiescent supply current
no signal; no load
-
45
75
mA
I
q(FB)(av)
average quiescent flyback supply
current
during scan
-
-
10
mA
Inputs A and B
V
i(p-p)
input voltage (peak-to-peak value)
note 2
-
1000
1500
mV
V
I(bias)
input bias voltage
note 2
100
880
1600
mV
I
I(bias)
input bias current
-
25
35
A
Outputs A and B
V
loss(1)
voltage loss first scan part
note 3
I
o
= 1.1 A
-
-
4.5
V
I
o
= 1.6 A
-
-
6.6
V
V
loss(2)
voltage loss second scan part
note 4
I
o
=
-
1.1 A
-
-
3.3
V
I
o
=
-
1.6 A
-
-
4.8
V
I
o(p-p)
output current
(peak-to-peak value)
-
-
3.2
A
LE
linearity error
I
o(p-p)
= 3.2 A; notes 5 and 6
adjacent blocks
-
1
2
%
non-adjacent blocks
-
1
3
%
V
offset
offset voltage
across R
M
; V
i(dif)
= 0 V
V
I(bias)
= 200 mV
-
-
15
mV
V
I(bias)
= 1 V
-
-
20
mV
V
offset(T)
offset voltage variation with
temperature
across R
M
; V
i(dif)
= 0 V
-
-
40
V/K
V
O
DC output voltage
V
i(dif)
= 0 V
-
0.5
V
P
-
V
G
v(ol)
open-loop voltage gain
notes 7 and 8
-
60
-
dB
f
-
3dB(h)
high
-
3 dB cut-off frequency
open-loop
-
1
-
kHz
G
v
voltage gain
note 9
-
1
-
G
v(T)
voltage gain variation with
temperature
-
-
10
-
4
K
-
1
PSRR
power supply rejection ratio
note 10
80
90
-
dB
2002 Sep 25
8
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
TDA8358J
Flyback switch
I
o(peak)
maximum (peak) output current
t
1.5 ms
-
-
1.8
A
V
loss(FB)
voltage loss at flyback
note 11
I
o
= 1.1 A
-
7.5
8.5
V
I
o
= 1.6 A
-
8
9
V
Guard circuit
V
O(grd)
guard output voltage
I
O(grd)
= 100
A
5
6
7
V
V
O(grd)(max)
allowable guard voltage
maximum leakage current
I
L(max)
= 10
A
-
-
18
V
I
O(grd)
output current
V
O(grd)
= 0 V; not active
-
-
10
A
V
O(grd)
= 4.5 V; active
1
-
2.5
mA
East-west amplifier
V
o
output voltage
at pin OUTEW
-
-
68
V
V
loss
voltage loss
I
o
= 750 mA; note 12
-
-
5
V
V
I(bias)
input bias voltage
2
2.5
3.2
V
I
I(bias)
input bias current
into pin INEW; note 13
I
o
= 100 mA
-
2.5
-
A
I
o
= 500 mA
-
11.5
-
A
G
v(ol)
open-loop voltage gain
-
30
-
dB
THD
harmonic distortion
-
0.5
1
%
f
-
3dB(h)
high
-
3 dB cut-off frequency
-
-
1
MHz
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
2002 Sep 25
9
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
TDA8358J
Notes
1. To limit V
OUTA
to 68 V, V
FB
must be 66 V due to the voltage drop of the internal flyback diode between pins OUTA
and V
FB
at the first part of the flyback.
2. Allowable input range for both inputs: V
I(bias)
+ V
i
< 1600 mV and V
I(bias)
-
V
i
> 100 mV.
3. This value specifies the sum of the voltage losses of the internal current paths between pins V
P
and OUTA, and
between pins OUTB and GND. Specified for T
j
= 125
C. The temperature coefficient for V
loss(1)
is a positive value.
4. This value specifies the sum of the voltage losses of the internal current paths between pins V
P
and OUTB, and
between pins OUTA and GND. Specified for T
j
= 125
C. The temperature coefficient for V
loss(2)
is a positive value.
5. The linearity error is measured for a linear input signal without S-correction and is based on the `on screen'
measurement principle. This method is defined as follows. The output signal is divided in 22 successive equal time
parts. The 1st and 22nd parts are ignored, and the remaining 20 parts form 10 successive blocks k. A block consists
of two successive parts. The voltage amplitudes are measured across R
M
, starting at k = 1 and ending at k = 10,
where V
k
and V
k+1
are the measured voltages of two successive blocks. V
min
, V
max
and V
avg
are the minimum,
maximum and average voltages respectively. The linearity errors are defined as:
a)
(adjacent blocks)
b)
(non adjacent blocks)
6. The linearity errors are specified for a minimum input voltage at pin 1 or pin 2 of 300 mV. Lower input voltages lead
to voltage dependent S-distortion in the input stage.
7.
8. Pin FEEDB not connected.
9.
10. V
P(ripple)
= 500 mV (RMS value); 50 Hz < f
P(ripple)
< 1 kHz; measured across R
M
.
11. This value specifies the internal voltage loss of the current path between pins V
FB
and OUTA.
12. This value specifies the internal voltage loss of the current path between pins OUTEW and EWGND.
13. Measured for R
EWF
= 10 k
; R
EWL
= 30
; V
o
= 6 V.
a) For I
o
= 100 mA and a voltage of 9 V at R
EWL
connected to the line output transformer, the east-west amplifier
input current (see Fig.4) is I
i
= 300
A.
b) For I
o
= 500 mA and a voltage of 21 V at R
EWL
connected to the line output transformer, the east-west amplifier
input current (see Fig.4) is I
i
= 350
A.
LE
V
k
V
k
1
+
V
avg
--------------------------
100%
=
LE
V
max
V
min
V
avg
-------------------------------
100%
=
G
v ol
( )
V
OUTA
V
OUTB
V
FEEDB
V
OUTB
--------------------------------------------
=
G
V
V
FEEDB
V
OUTB
V
INA
V
INB
--------------------------------------------
=
2002 Sep 25
10
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
TDA8358J
APPLICATION INFORMATION
handbook, full pagewidth
2
1
INA
INB
VP
VFB
FEEDB
C1
100 nF
C2
100 nF
CM
10 nF
GUARD
RGRD
4.7 k
RCV1
2.2 k
(1%)
RCV2
2.2 k
(1%)
REWL
30
REWF
10 k
RM
0.5
RL
3.2
RS
2.7 k
II(bias)
II(bias)
Ii(dif)
MGL873
INPUT
AND
FEEDBACK
CIRCUIT
GUARD
CIRCUIT
TDA8358J
4
6
Ii
Ii
11
9
3
VGND
EWGND
VP
VFB
OUTB
OUTA
VI(bias)
0
VI(bias)
0
12
10
7
8
5
INEW
OUTEW
COMP.
CIRCUIT
13
COMP
II(av)
Ii(p-p)
0
Vi(p-p)
Vi(p-p)
M5
M2
M4
M1
M3
M6
D2
D3
D1
Fig.3 Test diagram.
2002
Sep
25
11
Philips Semiconductors
Product specification
Full br
idge v
e
r
tical deflection output circuit
in L
VDMOS with east-w
est amplifier
TD
A8358J
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d
book, full pagewidth
VP = 14 V
VFB = 30 V
deflection
coil
5 mH
6
W66ESF
RM
0.87
RD1
270
RCMP
500 k
CD
47 nF
C3
100
nF
C1
47
F
(100 V)
C4
100 nF
C2
220
F
RD2
1.5
FEEDB
GUARD
RGRD
12 k
RS
2.7 k
INPUT
AND
FEEDBACK
CIRCUIT
GUARD
CIRCUIT
TDA8358J
4
11
3
VP
VFB
OUTB
OUTA
TV SIGNAL
PROCESSOR
C5
2.2 nF
C6
2.2 nF
2
1
INA
INB
RCV1
2.2 k
RCV2
2.2 k
VI(bias)
0
VI(bias)
0
REWL
12
REWF
82 k
MGL874
6
Ii
9
VGND
EWGND
12
10
7
8
5
INEW
OUTEW
to line output
transformer
COMP.
CIRCUIT
13
COMP
II(av)
Ii(p-p)
0
Vi(p-p)
Vi(p-p)
M5
M2
M4
M1
M3
M6
D2
D3
D1
Fig.4 Application diagram.
f
vert
= 50 Hz; t
FB
= 640
s; I
I(bias)
= 400
A; I
i(p-p)
= 475
A; I
o(p-p)
= 2.4 A.
2002 Sep 25
12
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
TDA8358J
R
M
calculation
Before calculating the measuring resistor (R
M
), the
differential input voltage [V
i(dif)
] has to be known. This
voltage can be measured between pins INA and INB. The
calculation is as follows:
Most of the TV signal processors from Philips have a
current output. This current has to be converted by
resistors at the input of the TDA8358J (R
CV1
and R
CV2
).
The voltage across these resistors can be calculated. The
differential input voltage is given in the following equation
(see also Fig 5):
V
i(dif)(p-p)
= I
i1(p-p)
R
CV1
-
[
-
I
i2(p-p)
]
R
CV2
Values for these currents are, for instance:
I
i(bias)
= 400
A; I
i1(p-p)
= I
i2(p-p)
= 475
A.
Therefore the differential input voltage be as follows:
V
i(dif)(p-p)
= 475
A
2.2 k
-
(
-
475
A
2.2 k
)
= 2.09 V
Supply voltage calculation
For calculating the minimum required supply voltage,
several specific application parameter values have to be
known. These parameters are the required maximum
(peak) deflection coil current I
coil(peak)
, the coil impedance
R
coil
and L
coil
and the measuring resistance of R
M
. The
required maximum (peak) deflection coil current should
also include the overscan.
The deflection coil resistance has to be multiplied by 1.2 in
order to take account of hot conditions.
Chapter "Characteristics" supplies values for the voltage
losses of the vertical output stage. For the first part of the
scan the voltage loss is given by V
loss(1)
. For the second
part of the scan the voltage loss is given by V
loss(2)
.
The voltage drop across the deflection coil during scan is
determined by the coil impedance. For the first part of the
scan the inductive contribution and the ohmic contribution
to the total coil voltage drop are of opposite sign, while for
the second part of the scan the inductive part and the
ohmic part have the same sign.
For the vertical frequency the maximum frequency
occurring must be applied to the calculations.
The required power supply voltage V
P
for the first part of
the scan is given by:
The required power supply voltage V
P
for the second part
of the scan is given by:
The minimum required supply voltage V
P
shall be the
highest of the two values V
P(1)
and V
P(2)
. Spread in supply
voltage and component values also has to be taken into
account.
Flyback supply voltage calculation
If the flyback time is known, the required flyback supply
voltage can be calculated by the simplified formula:
where:
R
M
V
i(dif)(p-p)
I
o(p-p)
----------------------
=
TV SIGNAL
PROCESSOR
C5
2.2 nF
C6
2.2 nF
RCV1
2.2 k
RCV2
2.2 k
II(bias)
0
1
2
II(bias)
0
Ii1(p-p)
Ii2(p-p)
MBL520
Fig.5 Differential input voltage.
V
P 1
( )
I
coil peak
(
)
R
coil
R
M
+
(
)
L
coil
2I
coil peak
(
)
f
vert max
(
)
V
loss 1
( )
+
=
V
P 2
( )
I
coil peak
(
)
R
coil
R
M
+
(
)
=
L
coil
2I
coil peak
(
)
f
vert max
(
)
V
loss 2
( )
+
+
V
FB
I
coil p p
(
)
R
coil
R
M
+
1
e
t
FB
x
/
---------------------------
=
x
L
coil
R
coil
R
M
+
---------------------------
=
2002 Sep 25
13
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
TDA8358J
The flyback supply voltage calculated this way is
approximately 5% to 10% higher than required.
Calculation of the power dissipation of the vertical
output stage
The power dissipation of the vertical output stage is given
by the formula:
P
V
= P
sup
-
P
L
The power to be supplied is given by the formula:
In this formula 0.3 [W] represents the average value of the
losses in the flyback supply.
The average external load power dissipation in the
deflection coil and the measuring resistor is given by the
formula:
Example
Table 1
Application values
Table 2
Calculated values
Power dissipation calculation for the east-west stage
In general the shape of the east-west output wave form is
a parabola. The output voltage will be higher at the
beginning and end of the vertical scan compared to the
voltage at the scan middle, while the output current will be
higher at the scan middle. This results in an almost uniform
power dissipation distribution during scan. Therefore the
power dissipation can be calculated by multiplying the
average values of the output voltage and the output
current of pin OUTEW.
When verifying the dissipation the switch-on and switch-off
dissipation should also be taken into account. Power
dissipation during start-up can be 3 to 5 times higher than
during normal operation.
Heatsink calculation
The value of the heatsink can be calculated in a standard
way with a method based on average temperatures. The
required thermal resistance of the heatsink is determined
by the maximum die temperature of 150
C. In general we
recommend a design for an average die temperature
not exceeding 130
C. It should be noted that the
heatsink thermal resistance R
th(h-a)
found by performing a
standard calculation will be lower then normally found for
a vertical deflection stand alone device, due to the
contribution of the EW power dissipation to this value.
E
XAMPLE
Measured or known values:
P
EW
= 3 W; P
V
= 6 W; T
amb
= 40
C; T
j
= 130
C;
R
th(j-c)
= 4 K/W; R
th(c-h)
= 1 K/W.
The required heatsink thermal resistance is given by:
When we use the values known we find:
The heatsink temperature will be:
T
h
= T
amb
+ R
th(h-a)
P
tot
= 40 + 5
9 = 85
C
SYMBOL
VALUE
UNIT
I
coil(peak)
1.2
A
I
coil(p-p)
2.4
A
L
coil
5
mH
R
coil
6
R
M
0.6
f
vert
50
Hz
t
FB
640
s
SYMBOL
VALUE
UNIT
V
P
14
V
R
M
+ R
coil
(hot)
7.8
t
vert
0.02
s
x
0.000641
V
FB
30
V
P
sup
8.91
W
P
L
3.74
W
P
V
5.17
W
P
sup
V
P
I
coil peak
(
)
2
------------------------
V
P
0.015 [A]
0.3 [W]
+
+
=
P
L
I
coil peak
(
)
(
)
2
3
--------------------------------
R
coil
R
M
+
(
)
=
R
th h
a
(
)
T
j
T
amb
P
EW
P
V
+
-------------------------
R
(
th j
c
(
)
R
th c
h
(
)
)
+
=
R
th h
a
(
)
130
40
3
6
+
----------------------
4
(
1
)
+
5 K/W
=
=
2002 Sep 25
14
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
TDA8358J
Equivalent thermal resistance network
The TDA8358J has two independent power dissipating
systems, the vertical output circuit and the east-west
circuit.
It is recommended to verify the individual maximum (peak)
junction temperatures of both circuits. Therefore the
maximum (peak) power dissipations of the circuits and
also the heatsink temperature should be measured. The
maximum (peak) junction temperatures can be calculated
by using an equivalent thermal network (see Fig.6).
The network only includes the contribution of the
maximum (peak) power dissipation P
TRv(peak)
, being the
dissipation of the most critical transistor internally
connected to pins OUTA and VGND. The model assumes
equivalent maximum (peak) power dissipations during the
different vertical scan stages for all the functionally paired
transistors. The calculated maximum (peak) junction
temperatures should not exceed T
j
= 150
C.
E
XAMPLE
Measured or known values:
The east-west power dissipation: P
EW
= 3 W
The vertical power dissipation: P
V
= 6 W
The maximum (peak) power dissipation of the most
critical transistor: P
TRv(peak)
= 5 W
The case temperature: T
c
= 85
C.
The IC total power dissipation is:
P
tot
= P
EW
+ P
V
= 6 + 3 = 9 W
It should be noted that the allowed IC total power
dissipation is P
tot
= 15 W (maximum value).
The maximum (peak) temperature T
P1(peak)
is given by:
T
P1(peak)
= T
c
+ (P
EW
+ P
TRv(peak)
)
R
th(P1-c)
= 85 + (3 + 5)
2.2 = 102.6
C
The maximum (peak) junction temperatures for the output
circuits are given by:
T
j(EW)(peak)
= T
P1(peak)
+ R
th(EW-P1)
P
EW
= 102.6 + 10.5
3 = 134.1
C
T
j(TRv)(peak)
= T
P1(peak)
+ R
th(TRv-P1)
P
TRv(peak)
= 102.6 + 5.2
5 = 128.6
C
handbook, halfpage
MGL872
TEW(M)
PEW
TTRv(M)
Tc
TP1(M)
PTRv(M)
Ptot
Rth(TRv-P1)
5.2 K/W
Rth(P1-c)
2.2 K/W
Rth(EW-P1)
10.5 K/W
Fig.6 Equivalent thermal resistance network.
2002 Sep 25
15
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
TDA8358J
INTERNAL PIN CONFIGURATION
PIN
SYMBOL
EQUIVALENT CIRCUIT
1
INA
2
INB
3
V
P
4
OUTB
6
VGND
9
V
FB
10
OUTA
5
INEW
7
EWGND
8
OUTEW
1
300
MBL100
2
300
MBL102
MGL869
9
3
10
4
6
MGL868
5
7
8
300
2002 Sep 25
16
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
TDA8358J
11
GUARD
12
FEEDB
13
COMP
PIN
SYMBOL
EQUIVALENT CIRCUIT
MGL870
11
300
MGL871
12
300
MGL875
13
300
2002 Sep 25
17
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
TDA8358J
PACKAGE OUTLINE
UNIT
A
e
1
A
2
b
p
c
D
(1)
E
(1)
Z
(1)
d
e
D
h
L
L
3
m
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
17.0
15.5
4.6
4.4
0.75
0.60
0.48
0.38
24.0
23.6
20.0
19.6
10
3.4
v
0.8
12.2
11.8
1.7
e
2
5.08
2.4
1.6
E
h
6
2.00
1.45
2.1
1.8
3.4
3.1
4.3
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
12.4
11.0
SOT141-6
0
5
10 mm
scale
Q
j
0.25
w
0.03
x
D
L
E
A
c
A
2
m
L
3
Q
w
M
b
p
1
d
D
Z
e
2
e
e
x
h
1
13
j
Eh
non-concave
view B: mounting base side
97-12-16
99-12-17
DBS13P: plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm)
SOT141-6
v
M
B
2002 Sep 25
18
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
TDA8358J
SOLDERING
Introduction to soldering through-hole mount
packages
This text gives a brief insight to wave, dip and manual
soldering. A more in-depth account of soldering ICs can be
found in our
"Data Handbook IC26; Integrated Circuit
Packages" (document order number 9398 652 90011).
Wave soldering is the preferred method for mounting of
through-hole mount IC packages on a printed-circuit
board.
Soldering by dipping or by solder wave
The maximum permissible temperature of the solder is
260
C; solder at this temperature must not be in contact
with the joints for more than 5 seconds.
The total contact time of successive solder waves must not
exceed 5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
stg(max)
). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300
C it may remain in contact for up to
10 seconds. If the bit temperature is between
300 and 400
C, contact may be up to 5 seconds.
Suitability of through-hole mount IC packages for dipping and wave soldering methods
Note
1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
PACKAGE
SOLDERING METHOD
DIPPING
WAVE
DBS, DIP, HDIP, SDIP, SIL
suitable
suitable
(1)
2002 Sep 25
19
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
TDA8358J
DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
DATA SHEET STATUS
(1)
PRODUCT
STATUS
(2)
DEFINITIONS
Objective data
Development
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
DEFINITIONS
Short-form specification
The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition
Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications
These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes
Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Philips Semiconductors a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Printed in The Netherlands
753504/02/pp
20
Date of release:
2002 Sep 25
Document order number:
9397 750 09635
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