1999 Dec 30

Philips Semiconductors

Product specification

IC card interface

TDA8004T

FEATURES

3 or 5 V supply for the IC (GND and V

)

Step-up converter for V

generation (separately

powered with a 5 V

10% supply, V

DDP

and PGND)

3 specific protected half duplex bidirectional buffered
I/O lines (C4, C7 and C8)

regulation 5 V

5% on 2

100 nF or 1

100 nF

and 1

220 nF multilayer ceramic capacitors with low

ESR, I

< 65 mA at 4.5 V < V

DDP

< 6.5 V, current

spikes of 40 nAs up to 20 MHz, with controlled rise and
fall times, filtered overload detection approximately
90 mA)

Thermal and short-circuit protections on all card
contacts

Automatic activation and deactivation sequences
(initiated by software or by hardware in the event of a
short-circuit, card take-off, overheating or supply
drop-out)

Enhanced ESD protection on card side (>6 kV)

26 MHz integrated crystal oscillator

Clock generation for the card up to 20 MHz (divided by
1, 2, 4 or 8 through CLKDIV1 and CLKDIV2 signals)

Non-inverted control of RST via pin RSTIN

ISO 7816, GSM11.11 and EMV (payment systems)
compatibility

Supply supervisor for spikes killing during power-on and
power-off

One multiplexed status signal OFF.

APPLICATIONS

IC card readers for banking

Electronic payment

Identification

Pay TV.

GENERAL DESCRIPTION

The TDA8004T is a complete low cost analog interface for
asynchronous smart cards. It can be placed betw the card
and the microcontroller with very few external components
to perform all supply protection and control functions.

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA8004T

SO28

plastic small outline package; 28 leads; body width 7.5 mm

SOT136-1

1999 Dec 30

Philips Semiconductors

Product specification

IC card interface

TDA8004T

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

supply voltage

2.7

6.5

DDP

step-up supply voltage

4.5

6.5

supply current

inactive mode; V

= 3.3 V;

XTAL

= 10 MHz

1.2

active mode; V

= 3.3 V;

XTAL

= 10 MHz; no load

1.5

DDP

step-up supply current

inactive mode; V

DDP

= 5 V;

XTAL

= 10 MHz

0.1

active mode; V

DDP

= 5 V;

XTAL

= 10 MHz; no load

Card supply

card supply voltage including
ripple

< 65 mA

4.75

5.25

AC current spikes of 40 nAs

4.65

5.25

i(ripple)(p-p)

ripple voltage on V

(peak-to-peak value)

20 kHz

f 200 MHz

350

card supply current

from 0 to 5 V

General

CLK

card clock frequency

MHz

deactivation cycle duration

100

tot

continuous total power dissipation

amb

25 to +85

0.56

amb

ambient temperature

+85

1999 Dec 30

Philips Semiconductors

Product specification

IC card interface

TDA8004T

PINNING

SYMBOL

PIN

I/O

DESCRIPTION

CLKDIV1

control with CLKDIV2 for choosing CLK frequency

CLKDIV2

control with CLKDIV1 for choosing CLK frequency

RFU1

reserved for future use (to be connected to V

or microcontroller I/O; active HIGH)

PGND

supply power ground for step-up converter

I/O

capacitance connection for step-up converter (a 100 nF capacitor with ESR < 100 m

must be connected between pins S1 and S2)

DDP

supply power supply voltage for step-up converter

I/O

capacitance connection for step-up converter (a 100 nF capacitor with ESR < 100 m

must be connected between pins S1 and S2)

VUP

I/O

output of step-up converter (a 100 nF capacitor with ESR < 100 m

must be

connected to PGND)

PRES

card presence contact input (active LOW); if PRES or PRES is true, then the card is
considered as present

PRES

card presence contact input (active HIGH); if PRES or PRES is true, then the card is
considered as present

I/O

data line to and from card (C7) (internal 10 k

pull-up resistor connected to V

)

AUX2

I/O

auxiliary line to and from card (C8) (internal 10 k

pull-up resistor connected to V

)

AUX1

I/O

auxiliary line to and from card (C4) (internal 10 k

pull-up resistor connected to V

)

CGND

supply ground for card signals

CLK

clock to card (C3)

RST

card reset (C2)

Supply for card (C1); decouple to CGND with 2

100 nF or 1

100 nF and 1

220 nF

capacitors with ESR < 100 m

(with 220 nF, the noise margin on V

will be higher).

n.c.

not connected

CMDVCC

start activation sequence input from microcontroller (active LOW)

RSTIN

card reset input from microcontroller (active HIGH)

supply supply voltage

GND

supply ground

OFF

NMOS interrupt to microcontroller (active LOW) with 20 k

internal pull-up resistor

connected to V

(refer section "Fault detection")

XTAL1

crystal connection or input for external clock

XTAL2

crystal connection (leave open if an external clock source is used)

I/OUC

I/O

microcontroller data I/O line (internal 10 k

pull-up resistor connected to V

)

AUX1UC

I/O

auxiliary line to and from microcontroller (internal 10 k

pull-up resistor connected to

)

AUX2UC

I/O

auxiliary line to and from microcontroller (internal 10 k

pull-up resistor connected to

)

1999 Dec 30

Philips Semiconductors

Product specification

IC card interface

TDA8004T

FUNCTIONAL DESCRIPTION

Throughout this document, it is assumed that the reader is
familiar with ISO 7816 norm terminology.

Power supply

The supply pins for the IC are V

and GND. V

should

be in the range from 2.7 to 6.5 V. All interface signals with
the system controller are referenced to V

; so, be sure

the supply voltage of the system controller is also V

. All

card contacts remain inactive during powering up or
powering down. The sequencer is not activated until V

reaches V

th2

+ V

hys(th2)

(see Fig.3). When V

falls below

th2

, an automatic deactivation of the contacts is

performed.

For generating a 5 V

5% V

supply to the card, an

integrated voltage doubler is incorporated. This step-up
converter should be separately supplied by V

DDP

and

PGND (from 4.5 to 6.5 V). Due to large transient currents,
the 2

100 nF capacitors of the step-up converter should

have an ESR less than 100 m

and be located as near as

possible to the IC.

The supply voltages V

and V

DDP

may be applied to

the IC in any time sequence.

If a voltage between 7 and 9 V is available within the
application, this voltage may be tied to pin VUP, thus
blocking the step-up converter. In this case, V

DDP

must be

tied to V

and the capacitor between pins S1 and S2 may

be omitted.

Voltage supervisor

This block surveys the V

supply. A defined reset pulse

of approximately 10 ms (t

) is used internally for

maintaining the IC in the inactive mode during powering up
or powering down of V

(see Fig.3).

As long as V

is less than V

th2

+ V

hys(th2)

, the IC will

remain inactive whatever the levels on the command lines.
This also lasts for the duration of t

after V

has reached

a level higher than V

th2

+ V

hys(th2)

The system controller should not try to start an activation
during this time.

When V

falls below V

th2

, a deactivation sequence of the

contacts is performed.

handbook, halfpage

CLKDIV1

CLKDIV2

RFU1

PGND

VDDP

VUP

PRES

I/O

AUX2

AUX1

CGND

AUX2UC

AUX1UC

I/OUC

XTAL2

OFF

GND

XTAL1

VDD

RSTIN

CMDVCC

n.c.

VCC

RST

CLK

TDA8004T

MGM174

Fig.2 Pin configuration.

1999 Dec 30

Philips Semiconductors

Product specification

IC card interface

TDA8004T

handbook, full pagewidth

MGM176

VDD

Vth2

Vhys(th2)

Vth2

ALARM

(internal signal)

Fig.3 ALARM as a function of V

= 10 ms).

Clock circuitry

The clock signal (CLK) to the card is either derived from a
clock signal input on pin XTAL1 or from a crystal up to
26 MHz connected between pins XTAL1 and XTAL2.

The frequency may be chosen at
f

XTAL

via pins CLKDIV1 and

CLKDIV2.

The frequency change is synchronous, which means that
during transition, no pulse is shorter than 45% of the
smallest period and that the first and last clock pulse
around the change has the correct width.

In the case of f

XTAL

, the duty factors are dependent on the

signal at XTAL1.

In order to reach a 45% to 55% duty factor on pin CLK the
input signal on XTAL1 should have a duty factor of
48% to 52% and transition times of less than 5% of the
input signal period.

If a crystal is used with f

XTAL

, the duty factor on pin CLK

may be 45% to 55% depending on the layout and on the
crystal characteristics and frequency.

In the other cases, it is guaranteed between 45% and 55%
of the period.

The crystal oscillator runs as soon as the IC is powered up.
If the crystal oscillator is used, or if the clock pulse on
XTAL1 is permanent, then the clock pulse will be applied
to the card according to the timing diagram of the
activation sequence (see Fig.5).

If the signal applied to XTAL1 is controlled by the system
controller, then the clock pulse will be applied to the card
when the system controller will send it (after completion of
the activation sequence).

Table 1

Clock circuitry definition

CLKDIV1

CLKDIV2

CLK

XTAL

1999 Dec 30

Philips Semiconductors

Product specification

IC card interface

TDA8004T

I/O circuitry

The three data lines I/O, AUX1 and AUX2 are identical.

The Idle state is realized by both lines (I/O and I/OUC)
being pulled HIGH via a 10 k

resistor (I/O to V

and

I/OUC to V

I/O is referenced to V

and I/OUC to V

, thus allowing

operation with V

The first side on which a falling edge occurs becomes the
master. An anti-latch circuit disables the detection of falling
edges on the other line, which becomes a slave.

After a time delay t

d(edge)

(approximately 200 ns), the

N transistor on the slave side is turned on, thus
transmitting the logic 0 present on the master side.

When the master side returns to logic 1, the P transistor on
the slave side is turned on during the time delay t

d(edge)

and

then both sides return to their Idle states.

This active pull-up feature ensures fast LOW-to-HIGH
transitions; it is able to deliver more than 1 mA up to an
output voltage of 0.9V

on a 80 pF load. At the end of the

active pull-up pulse, the output voltage only depends on
the internal pull-up resistor and on the load current (see
Fig.4).

The maximum frequency on these lines is 1 MHz.

Inactive state

After power-on reset, the circuit enters the inactive state. A
minimum number of circuits are active while waiting for the
microcontroller to start a session.

All card contacts are inactive (approximately 200

GND)

I/OUC, AUX1UC and AUX2UC are high impedance
(10 k

pull-up resistor connected to V

)

Voltage generators are stopped

XTAL oscillator is running

Voltage supervisor is active.

Activation sequence

After power-on and after the internal pulse width delay, the
system controller may check the presence of the card with
the signal OFF (OFF = HIGH while CMDVCC is HIGH
means that the card is present; OFF = LOW while
CMDVCC is HIGH means that no card is present).

If the card is in the reader (which is the case if PRES or
PRES is true), the system controller may start a card
session by pulling CMDVCC LOW.

The following sequence then occurs (see Fig.5):

CMDVCC is pulled LOW (t

)

The voltage doubler is started (t

~ t

)

rises from 0 to 5 V with a controlled slope

= t

3T) (I/O, AUX1 and AUX2 follow V

with a

slight delay)

I/O, AUX1 and AUX2 are enabled (t

= t

+ 4T)

CLK is applied to the C3 contact (t

)

RST is enabled (t

= t

+ 7T).

In the timing informations above and below, T is 64 times
the period of the internal oscillator, about 25

The clock may be applied to the card in the following way:

Set RSTIN HIGH before setting CMDVCC LOW and
reset it LOW between t

and t

; CLK will start at this

moment. RST will remain LOW until t

, where RST is

enabled to be the copy of RSTIN. After t

, RSTIN has no

further action on CLK. This is to allow a precise count of
CLK pulses before toggling RST.

If this feature is not needed, then CMDVCC may be set
LOW with RSTIN LOW. In this case, CLK will start at t

and

after t

, RSTIN may be set HIGH in order to get the Answer

To Request (ATR) from the card.

handbook, halfpage

(2)

(1)

t (ns)

(V)

(mA)

FCE270

Fig.4

I/O, AUX1, and AUX2 output voltage and
current as a function of time during a
LOW-to-HIGH transition.

(1) Current.

(2) Voltage.

1999 Dec 30

Philips Semiconductors

Product specification

IC card interface

TDA8004T

handbook, full pagewidth

MGM177

CMDVCC

VUP

VCC

I/O

CLK

RSTIN

RST

high - Z

tact

ATR

OSC_INT/64

Fig.5 Activation sequence.

Active state

When the activation sequence is completed, the
TDA8004T will be in the active state. Data is exchanged
between the card and the microcontroller via the I/O lines.
The TDA8004T is designed for cards without V

(this is

the voltage required to program or erase the internal
non-volatile memory).

Depending on the layout and on the application test
conditions (for example with an additional 1 pF cross
capacitance between C2/C3 and C2/C7) it is possible
that C2 is polluted with high frequency noise from C3. In
this case, it will be necessary to connect a 220 pF
capacitance between C2 and CGND.

It is recommended to:

1. Keep track C3 as far as possible from other tracks

2. Have straight connection between CGND and C5 (the

2 capacitors on C1 should be connected to this ground
track)

3. Avoid ground loops between CGND, PGND and GND

4. Decouple V

DDP

and V

separately; if the 2 supplies

are the same in the application, then they should be
connected in star on the main track.

With all these layout precautions, noise should be at an
acceptable level and jitter on C3 should be less than
100 ps. Refer to

Application Note AN97036 for specimen

layouts

Deactivation sequence

When a session is completed, the microcontroller sets the
CMDVCC line to the HIGH state. The circuit then executes
an automatic deactivation sequence by counting the
sequencer back and ends in the inactive state (see Fig.6):

RST goes LOW

= t

)

CLK is stopped LOW

= t

I/O, AUX1 and AUX2 are output into high-impedance
state

= t

+ T); 10 k

pull-up resistor connected

to V

falls to zero

= t

3T); the deactivation

sequence is completed when V

reaches its inactive

state

VUP falls to zero

= t

+ 5T) and all card contacts

become low-impedance to GND; I/OUC, AUX1UC and
AUX2UC remain pulled up to V

via a 10 k

resistor.

1999 Dec 30

Philips Semiconductors

Product specification

IC card interface

TDA8004T

handbook, full pagewidth

MGE739

CMDVCC

VUP

OSC_INT/64

VCC

I/O

CLK

RST

high - Z

tde

t10

t11

t12

t13

t14

t15

Fig.6 Deactivation sequence.

Fault detection

The following fault conditions are monitored by the circuit:

Short-circuit or high current on V

Removing card during transaction

dropping

Overheating.

There are two different cases (see Fig.7):

1. CMDVCC HIGH: (outside a card session) then, OFF is

LOW if the card is not in the reader and HIGH if the
card is in the reader. A supply voltage drop on V

detected by the supply supervisor, generates an
internal power-on reset pulse, but don't act upon OFF.
The card is not powered-up, so no short-circuit or
overheating is detected.

2. CMDVCC LOW: (within a card session) then, OFF falls

LOW if the card is extracted, or if a short-circuit has
occurred on V

, or if the temperature on the IC has

become too high. As soon as the fault is detected, an
emergency deactivation is automatically performed
(see Fig.8).

When the system controller sets CMDVCC back to
HIGH, it may sense OFF again in order to distinguish
between a hardware problem or a card extraction. If a
supply voltage drop on V

is detected whilst the card

is activated, then an emergency deactivation will be
performed, but OFF remains HIGH.

Depending on the type of card presence switch within the
connector (normally closed or normally open) and on the
mechanical characteristics of the switch, a bouncing may
occur on presence signals at card insertion or withdrawal.

There is no debounce feature in the device, so the
software has to take it into account; however, the detection
of card take off during active phase, which initiates an
automatic deactivation sequence is done on the first
true/false transition on PRES or PRES and is memorized
until the system controller sets CMDVCC HIGH.

So, the software may take some time waiting for presence
switches to be stabilized without causing any delay on the
necessary fast and normalized deactivation sequence.

1999 Dec 30

Philips Semiconductors

Product specification

IC card interface

TDA8004T

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); notes 1 and 2.

Notes

1. All card contacts are protected against any short with any other card contact.

2. Stress beyond these levels may cause permanent damage to the device. This is a stress rating only and functional

operation of the device under this condition is not implied.

HANDLING

Every pin withstands the ESD test according to MIL-STD-883C class 3 for card contacts, class 2 for the remaining.
Method 3015 (HBM; 1500

; 100 pF) 3 pulses positive and 3 pulses negative on each pin referenced to ground.

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

, V

DDP

supply voltage

0.3

voltage on pins: XTAL1, XTAL2, RFU1, RSTIN,
AUX2UC, AUX1UC, I/OUC, CLKDIV1, CLKDIV2,
CMDVCC and OFF

0.3

voltage on card contact pins PRES, PRES, I/O, RST,
AUX1, AUX2 and CLK

0.3

voltage on pin VUP, S1 and S2

stg

IC storage temperature

+125

tot

continuous total power dissipation

amb

25 to +85

0.56

junction temperature

150

es1

electrostatic voltage on pins: I/O, RST, V

, AUX1,

CLK, AUX2, PRES and PRES

es2

electrostatic voltage on all other pins

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

th(j-a)

thermal resistance from junction to ambient

in free air

K/W

1999 Dec 30

Philips Semiconductors

Product specification

IC card interface

TDA8004T

CHARACTERISTICS
V

= 3.3 V; V

DDP

= 5 V; T

amb

= 25

C; all parameters remain within limits but are only statistically tested for the

temperature range; f

XTAL

= 10 MHz; unless otherwise specified; all currents flowing into the IC are positive. When a

parameter is specified as a function of V

or V

, it means their actual value at the moment of measurement.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Temperature

amb

ambient temperature

+85

Supplies

supply voltage

2.7

6.5

DDP

supply voltage for the voltage
doubler

4.5

6.5

o(VUP)

output voltage on pin VUP from
step-up converter

5.5

i(VUP)

input voltage to be applied on VUP
in order to block the step-up
converter

supply current

inactive mode

1.2

active mode; f

CLK

= f

XTAL

;

= 30 pF

1.5

supply current for the step-up
converter

inactive mode

0.1

active mode; f

CLK

= f

XTAL

;

= 30 pF

= 0

= 65 mA

150

th2

threshold voltage on V

(falling)

2.2

2.4

hys(th2)

hysteresis on V

th2

150

width of the internal ALARM pulse

Card supply voltage (V

); note 1

output voltage including ripple

inactive mode

0.1

+0.1

inactive mode; I

= 1 mA

0.1

+0.4

active mode;

< 65 mA DC

4.75

5.25

active mode; single current
pulse of

100 mA; 2

4.65

5.25

active mode; current pulses
of 40 nAs with

< 200 mA; t < 400 ns;

4.65

5.25

i(ripple)(p-p)

peak-to-peak ripple voltage on V

20 kHz

f 200 MHz

350

output current

from 0 to 5 V;

short-circuit to ground

120

slew rate

up and down

0.11

0.17

0.22

1999 Dec 30

Philips Semiconductors

Product specification

IC card interface

TDA8004T

Crystal connections (XTAL1 and XTAL2)

ext

external capacitance on
XTAL1 and XTAL2

depending on specification
of crystal or resonator used

i(XTAL)

crystal input frequency

MHz

IH(XTAL)

HIGH-level input voltage on XTAL1

0.8V

+ 0.2 V

IL(XTAL)

LOW-level input voltage on XTAL1

0.3

0.2V

Data lines (I/O, I/OUC, AUX1, AUX2, AUXUC1 and AUXUC2)

ENERAL

d(edge)

delay between falling edge on pins
I/OUC and I/O (or I/O and I/OUC)
and width of active pull-up pulse

200

I/O(max)

maximum frequency on data lines

MHz

input capacitance on data lines

ATA LINES

; I/O, AUX1

AND

AUX2 (

WITH

PULL

UP RESISTOR CONNECTED TO

)

HIGH-level output voltage on data
lines

no DC load

0.9V

+ 0.1 V

0.75V

+ 0.1 V

LOW-level output voltage on data
lines

I = 1 mA

300

HIGH-level input voltage on data
lines

1.8

+ 0.3 V

LOW-level input voltage on data
lines

0.3

+0.8

inactive

voltage on data lines outside a
session

no load

0.1

I/O

= 1 mA

0.3

edge

current from data lines when active
pull-up active

= 0.9V

; C

= 80 pF

LIH

input leakage current HIGH on data
lines

= V

LOW-level input current on data
lines

= 0 V

600

pu(int)

internal pull-up resistance between
data lines and V

, t

input transition times on data lines

from V

IL(max)

to V

IH(min)

output transition times on data lines

= 80 pF, no DC load;

10% to 90% of V

(see

Fig.9)

0.1

ATA LINES

; I/OUC, AUX1UC

AND

AUX2UC (

WITH

PULL

UP RESISTOR CONNECTED TO

)

HIGH-level output voltage on data
lines

no DC load

0.9V

+ 0.2 V

0.75V

+ 0.2

LOW-level output voltage on data
lines

= 1 mA

300

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1999 Dec 30

Philips Semiconductors

Product specification

IC card interface

TDA8004T

HIGH-level input voltage on data
lines

0.7V

+ 0.3 V

LOW-level input voltage on data
lines

0.3V

LIH

input leakage current HIGH on data
lines

= V

LOW-level input on data lines

= 0 V

600

pu(int)

internal pull-up resistance between
data lines and V

, t

input transition times on data lines

from V

IL(max)

to V

IH(min)

output transition times on data lines

= 30 pF; 10% to 90%

of V

(see Fig.9)

0.1

Internal oscillator

osc(int)

frequency of internal oscillator

2.2

3.2

MHz

Reset output to the card (RST)

o(inactive)

output voltage in inactive mode

no load

0.1

= 1 mA

0.3

d(RSTIN-RST)

delay between pins RSTIN and RST RST enabled

LOW-level output voltage

= 200

0.3

HIGH-level output voltage

200

0.9V

, t

rise and fall times

= 250 pF

0.1

Clock output to the card (CLK)

o(inactive)

output voltage in inactive mode

no load

0.1

= 1 mA

0.3

LOW-level output voltage

= 200

0.3

HIGH-level output voltage

200

0.9V

, t

rise and fall times

= 35 pF; note 2

duty factor (except for f

XTAL

)

= 35 pF; note 2

slew rate (rise and fall)

= 35 pF

0.2

V/ns

Logic inputs (CLKDIV1, CLKDIV2, PRES, PRES, CMDVCC, RSTIN and RFU1); note 3

LOW-level input voltage

0.3V

HIGH-level input voltage

0.7V

LIL

input leakage current LOW

0 < V

< V

LIH

input leakage current HIGH

0 < V

< V

OFF output (OFF is an open drain with an internal 20 k

pull-up resistor to V

)

LOW-level output voltage

= 2 mA

0.4

HIGH-level output voltage

0.75V

Protections

shut-down temperature

135

CC(sd)

shut-down current at V

110

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1999 Dec 30

Philips Semiconductors

Product specification

IC card interface

TDA8004T

Notes

1. To meet these specifications V

should be decoupled to CGND using two ceramic multilayer capacitors of low ESR

with values of either 100 nF or one 100 nF and one 220 nF.

2. The transition times and duty factor definitions are shown in Fig.9;

3. PRES and CMDVCC are active LOW; RSTIN and PRES are active HIGH; for CLKDIV1 and CLKDIV2 see Table 1;

RFU1 must be tied HIGH.

APPLICATION INFORMATION

for the TDA8004T must be the same as for the microcontroller and CLKDIV1, CLKDIV2, RSTIN, PRES, PRES,

AUX1UC, AUX2UC, I/OUC, RFU1, CMDVCC and OFF should be referenced to V

and XTAL1 also when driven by an

external clock.

For optimum layout be sure that there is enough ground area around the TDA8004T and the connector. Place the
TDA8004T very near to the connector, ideally under the connector, and decouple V

and V

DDP

properly.

Refer to

AN97036 for further application information for proper implementation of the TDA8004T.

Timing

act

activation sequence duration

see Fig.5

180

220

deactivation sequence duration

see Fig.6

100

start of the window for sending CLK
to the card

see Fig.5

130

end of the window for sending CLK
to the card

see Fig.5

140

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

(

)

--------------------

handbook, full pagewidth

MGM178

10%

90%

10%

VCC or VDD

(VOH

VOL)/2

Fig.9 Definition of output transition times.

1999 Dec 30

Philips Semiconductors

Product specification

IC card interface

TDA8004T

100 nF

AUX2UC

AUX1UC

I/OUC

XTAL2

XTAL1

OFF

GND

VDD

RSTIN

CMDVCC

n.c.

VCC

RST

CLK

CLKDIV1

CLKDIV2

RFU1

GNDP

VDDP

VUP

PRES

I/O

AUX2

AUX1

CGND

TDA8004T

CARD READ

(Normally closed type)

3.3 V

3.3 V POWERED

MICROCONTROLLER

33 pF

100 nF

220 nF

5 V

100 k

These capacitors
must be placed
near the IC and
have LOW ESR
(Less than 1 cm)

Straight and short
connextions between
CGND, C5 and capacitors
GND. (No loop)

One 100nF
with LOW ESR
near pin 17,

One 100nF or 220nF
with LOW ESR
near C1 contact
(less than 1cm)

C3 should be routed
far from C2, C7, C4 and C8
and, better, surrounded
with ground tracks.

MGM179

More application information on
application report AN97036

VDD for the TDA8004 must be the same as controller
supply voltage, CLKDIV1, CLKDIV2, RSTIN, PRES,
PRES, AUXUC, I/OUC, AUX2UC, RFU1, CMDVCC,
OFF should be referenced to VDD, and also XTAL1
if driven by external clock.

Fig.10 Application diagram.

1999 Dec 30

Philips Semiconductors

Product specification

IC card interface

TDA8004T

SOLDERING

Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"Data Handbook IC26; Integrated Circuit Packages"

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250

C. The top-surface temperature of the

packages should preferable be kept below 230

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

For packages with leads on four sides, the footprint must
be placed at a 45

angle to the transport direction of the

printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320

1999 Dec 30

Philips Semiconductors

Product specification

IC card interface

TDA8004T

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PACKAGE

SOLDERING METHOD

WAVE

REFLOW

(1)

BGA, SQFP

not suitable

suitable

HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS

not suitable

(2)

suitable

PLCC

(3)

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

(3)(4)

suitable

SSOP, TSSOP, VSO

not recommended

(5)

suitable

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

SCA

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

1999

Philips Semiconductors a worldwide company

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

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Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
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Philippines: Philips Semiconductors Philippines Inc.,
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Printed in The Netherlands

545004/25/02/pp

Date of release:

1999 Dec 30

Document order number:

9397 750 06034

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA8004T

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA8004T