Document Outline

• 1 Features
  • 1.1 Hardware
  • 1.2 Software
  • 2 Applications
  • 3 General description
  • 4 Quick reference data
    • Note
      • 1. FMRDS and FMMPX input sensitivity setting �000� (see Table17).
  • 5 Ordering information
  • QFP80
  • SOT3182
• 6 Block diagram
  • Fig.1 Block diagram.
• 7 Pinning
  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
    • Table 1 Explanation of pin types
      • Fig.2 Pin configuration.
• 8 Functional description
  • 8.1 FM and level information processing
  • 8.1.1 Signal path for level information
  • 8.1.2 Signal path from FMMPX input to IAC and stereo decoder
  • 8.1.3 Input sensitivity for FM and RDS signals
  • 8.1.4 ADinput selection switch
  • 8.1.5 Interference absorption circuit
    • Fig.3 Analog input switching circuit.
    • 8.1.5.1 AGC set point (1bit)
    • 8.1.5.2 Threshold sensitivity offset (3bits)
    • 8.1.5.3 Deviation feed-forward factor (3bits)
    • 8.1.5.4 Suppression stretch time (3bits)
    • 8.1.5.5 MPX delay (2bits)
    • 8.1.5.6 Level-IAC threshold (4bits)
    • 8.1.5.7 Level-IAC feed-forward setting (2bits)
    • 8.1.5.8 Level-IAC suppression stretch time (2bits)
    • 8.1.5.9 Dynamic IAC threshold levels
    • 8.1.5.10 IAC testing mode
  • 8.2 Analog source selection and analog-to-digital conversion
  • 8.2.1 Input selection switches
  • 8.2.2 Signal flow of the AM, analog CD and TAPE inputs
  • 8.2.3 The analog CD block
  • 8.2.4 PinVREFAD
  • 8.2.5 PinsVDACN1, VDACN2 andVDACP
    • Fig.4 Analog CD block.
• 8.2.6 Supply of the analog inputs
  • 8.3 Analog outputs
  • 8.3.1 DACs
  • 8.3.2 Upsample filter
  • 8.3.3 Volume control
    • Fig.5 Typical THD+N curve versus output level.
• 8.3.4 Function of pinPOM
  • 8.3.5 Power-off plop suppression
  • 8.3.6 The internal pinVREFDA
  • 8.3.7 Internal DAC current reference
  • 8.3.8 Supply of the analog outputs
  • 8.4 Clock circuit and oscillator
  • 8.4.1 Supply of the crystal oscillator
  • 8.4.2 The phase-locked loop circuit to generate the DSPclock and other derived clocks
    • Fig.6 Block diagram of the oscillator circuit.
  • 8.4.3 The clock block
  • 8.4.4 Synchronization with the core
    • Fig.7 Programmable PLL for DSP clock generation.
• 8.5 Equalizer accelerator circuit
  • 8.5.1 Introduction
  • 8.5.2 EQ circuit overview
    • Table 2 Equalizer port list
  • 8.5.3 Controller and programming circuit
    • Fig.8 Derivation of the gated clock from clkCORE.
• 8.6 The DSPcore
  • 8.7 External control pins and status register
  • 8.8 I2C-bus interface (pinsSCL andSDA)
  • 8.9 I2S-bus inputs and outputs
    • Fig.9 Available serial digital audio data in/output formats.
• 8.10 RDS decoder (pinsRDSCLK andRDSDAT)
  • 8.10.1 Clock and data recovery
  • 8.10.2 Timing of clock and data signals
  • 8.10.3 Buffering of RDS data
    • Fig.10 RDS timing (direct output mode).
    • Fig.11 Interface signals RDS decoder and microcontroller (buffer mode).
• 8.10.4 Buffer interface
  • 8.11 DSP reset
• 9 Limiting values
  • 10 Thermal characteristics
  • 45
  • K/W
• 11 Characteristics
  • Note
    • 1. FMRDS and FMMPX input sensitivity setting �000� (see Table17).
    • Fig.12 Timing of the digital audio data in- and outputs.
• 12 I2C-bus interface and programming
  • 12.1 I2C-bus interface
  • 12.1.1 Characteristics of the I2C-bus
  • 12.1.2 Bit transfer
  • 12.1.3 Start and stop conditions
    • Fig.13 Bit transfer on the I2C-bus.
    • Fig.14 START and STOP condition.
• 12.1.4 Data transfer
  • 12.1.5 Acknowledge
    • Fig.15 Data transfer on the I2C-bus.
    • Fig.16 Acknowledge on the I2C-bus.
• 12.2 I2C-bus protocol
  • 12.2.1 Addressing
  • 12.2.2 Slave address
    • Table 3 Slave address
  • 0
  • 0
  • 1
  • 1
  • 1
  • 0
  • A0
  • R/W
    • 12.2.3 Write cycles
    • 12.2.4 Read cycles
      • Fig.17 Master transmitter writes to the DSP registers.
      • Fig.18 Master transmitter reads from the DSP registers.
      • Fig.19 Definition of timing on the I2C-bus.
      • Table 4 Timing fast I2C-bus (see Fig.19)
• 12.3 Memory map specification and register overview
  • Table 5 Memory map
  • Table 6 Register overview
  • 12.4 Register description
    • Table 7 DCSCTR register (address0FFFH)
  • 1
  • 4
  • 1
  • 1
  • 1
  • 4
  • 4
    • Table 8 DCSDIV register (address0FFEH)
  • 16
    • Note
      • 1. DCS-COEF can be calculated by the multiplication V�215 and then convert this decimal value t...
      • Table 9 AD register (address0FFDH)
  • 3
  • 1
  • 1
  • 4
  • 3
  • 3
  • 1
    • Table 10 LEVELIAC register (address0FFCH)
  • 1
  • 2
  • 5
  • 2
  • 2
  • 4
    • Table 11 IAC register (address0FFBH)
  • 1
  • 3
  • 1
  • 2
  • 3
  • 3
  • 3
    • Table 12 SEL register (address0FFAH)
  • 1
  • 1
  • 1
  • 1
  • 1
  • 1
  • 1
  • 1
  • 1
  • 1
  • 1
  • 1
  • 1
  • 1
  • 1
  • 1
    • Table 13 HOST register (address0FF9H)
  • 3
  • 1
  • 2
  • 3
  • 2
  • 5
    • Table 14 RDSCTRregister (address 0FF3H)
  • 7
  • 1
  • 8
    • 12.5 Detailed register description
      • Table 15 PLL clock division factor (PLL-DIV bits)
  • 0
  • 0
  • 0
  • 0
  • 93
  • 186
  • 0
  • 0
  • 0
  • 1
  • 99
  • 198
  • 0
  • 0
  • 1
  • 0
  • 106
  • 106
  • 0
  • 0
  • 1
  • 1
  • 113
  • 212
  • 0
  • 1
  • 0
  • 0
  • 121
  • 242
  • 0
  • 1
  • 0
  • 1
  • 126
  • 252
  • 0
  • 1
  • 1
  • 0
  • 132
  • 264
  • 0
  • 1
  • 1
  • 1
  • 137
  • 274
  • 1
  • 0
  • 0
  • 0
  • 143
  • 286
  • 1
  • 0
  • 0
  • 1
  • 148
  • 296
  • 1
  • 0
  • 1
  • 0
  • 154 (default)
  • 308
  • 1
  • 0
  • 1
  • 1
  • 159
  • 318
  • 1
  • 1
  • 0
  • 0
  • 165
  • 330
  • 1
  • 1
  • 0
  • 1
  • 170
  • 340
  • 1
  • 1
  • 1
  • 0
  • 176
  • 352
  • 1
  • 1
  • 1
  • 1
  • 181
  • 362
    • Table 16 Representation of division factors F0 and F1
    • Table 17 Volume control of the FMMPX and FMRDS input by the AD register.
  • 0
  • 0
  • 0
  • 65
  • 410
  • 137
  • 0
  • 0
  • 1
  • 78
  • 493
  • 103
  • 0
  • 1
  • 0
  • 93
  • 587
  • 84.8
  • 0
  • 1
  • 1
  • 111
  • 700
  • 74
  • 1
  • 0
  • 0
  • 132
  • 833
  • 67
  • 1
  • 0
  • 1
  • 158
  • 1000
  • 62
  • 1
  • 1
  • 0
  • 188 (default)
  • 1188 (default)
  • 58.4 (default)
  • 1
  • 1
  • 1
  • 225
  • 1387
  • 56
    • Table 18 Dynamic IAC deviation threshold
  • 0
  • 0
  • 43 (default)
  • 0
  • 1
  • 48.5
  • 1
  • 0
  • 58
  • 1
  • 1
  • 65
    • Table 19 IAC-level stretch time
  • 0
  • 0
  • 9
  • 0
  • 1
  • 11 (default)
  • 1
  • 0
  • 13
  • 1
  • 1
  • 15
    • Table 20 IAC-level deviation feed-forward factor
  • 0
  • 0
  • -2 (default)
  • 0
  • 1
  • -1
  • 1
  • 0
  • 0
  • 1
  • 1
  • 1
    • Table 21 Level IAC threshold settings
  • 0
  • 0
  • 0
  • 0
  • level-IAC off (default)
  • 0
  • 0
  • 0
  • 1
  • 0.02
  • 0.0000010
  • 0
  • 0
  • 1
  • 0
  • 0.025
  • 0.0000011
  • 0
  • 0
  • 1
  • 1
  • 0.0316
  • 0.0000100
  • 0
  • 1
  • 0
  • 0
  • 0.04
  • 0.0000101
  • 0
  • 1
  • 0
  • 1
  • 0.05
  • 0.0000110
  • 0
  • 1
  • 1
  • 0
  • 0.063
  • 0.0001000
  • 0
  • 1
  • 1
  • 1
  • 0.08
  • 0.0001010
  • 1
  • 0
  • 0
  • 0
  • 0.1
  • 0.0001101
  • 1
  • 0
  • 0
  • 1
  • 0.126
  • 0.0010000
  • 1
  • 0
  • 1
  • 0
  • 0.16
  • 0.0010100
  • 1
  • 0
  • 1
  • 1
  • 0.2
  • 0.0011010
  • 1
  • 1
  • 0
  • 0
  • 0.25
  • 0.0100000
  • 1
  • 1
  • 0
  • 1
  • 0.316
  • 0.0101000
  • 1
  • 1
  • 1
  • 0
  • 0.4
  • 0.0110100
  • 1
  • 1
  • 1
  • 1
  • 0.5
  • 0.1000000
    • Table 22 IAC delay settings MPX
  • 1
  • 0
  • 2
  • 1
  • 1
  • 3
  • 0
  • 0
  • 4
  • 0
  • 1
  • 5 (default)
    • Table 23 IAC stretch time suppression
  • 1
  • 0
  • 1
  • 0
  • not applicable
  • 1
  • 0
  • 0
  • 1
  • 0
  • 1
  • 1
  • 1
  • 2
  • 1
  • 1
  • 1
  • 0
  • 3
  • 2
  • 0
  • 0
  • 1
  • 4
  • 3
  • 0
  • 0
  • 0
  • 5
  • 4
  • 0
  • 1
  • 1
  • 6
  • 5 (default)
  • 0
  • 1
  • 0
  • 7
  • 6
    • Table 24 IAC deviation feed-forward factor
  • 0
  • 1
  • 1
  • 0.00146
  • 0.000000000110
  • 0
  • 1
  • 0
  • 0.00195
  • 0.000000001000
  • 0
  • 0
  • 1
  • 0.00293
  • 0.000000001100
  • 0
  • 0
  • 0
  • 0.00391
  • 0.000000010000
  • 1
  • 1
  • 1
  • 0.00586
  • 0.000000011000
  • 1
  • 1
  • 0
  • 0.00781
  • 0.000000100000
  • 1
  • 0
  • 1
  • 0.01172 (default)
  • 0.000000110000
  • 1
  • 0
  • 0
  • 0.00000
  • 0.000000000000
    • Table 25 IAC threshold sensitivity
  • 1
  • 0
  • 0
  • 0.027
  • 0.000001110000
  • 1
  • 0
  • 1
  • 0.031 (default)
  • 0.000010000000
  • 1
  • 1
  • 0
  • 0.038
  • 0.000010011100
  • 1
  • 1
  • 1
  • 0.047
  • 0.000011000000
  • 0
  • 0
  • 0
  • 0.055
  • 0.000011100000
  • 0
  • 0
  • 1
  • 0.063
  • 0.000100000000
  • 0
  • 1
  • 0
  • 0.074
  • 0.000100110000
  • 0
  • 1
  • 1
  • 0.085
  • 0.000101100000
    • Table 26 Analog input selection; notes1and2
  • X(3)
  • 0
  • 1
  • 0
  • 0
  • X(3)
  • 0
  • 1
  • 1
  • 0
  • 1
  • X(3)
  • 0
  • X(3)
  • 1
  • X(3)
  • 1
  • 1
  • X(3)
  • X(3)
  • X(3)
  • X(3)
  • X(3)
  • X(3)
  • 1
  • 0
  • X(3)
  • 0
  • X(3)
  • X(3)
    • Note s
      • 1. It is assumed that the AM level input is used for AM reception and the FM level input for FM r...
      • 2. In all the positions it is assumed that pinSELFR is LOW.
      • 3. X=don�t care.
      • 4. In the MICROPHONE position it is assumed that the microphone is connected to the AML input. Wh...
      • Table 27 Cloop mode settings
  • 0
  • -
  • -
  • 1
  • -
  • -
  • -
  • 0
  • 0
  • -
  • 0
  • 1
  • -
  • 1
  • 0
  • -
  • 1
  • 1
    • Table 28 Host input/output data format
  • 0
  • 0
  • 0
  • 1
  • 1
  • 0
  • 1
  • 1
    • Table 29 Audio register data format
  • 0
  • 0
  • 0
  • -
  • 0
  • 1
  • -
  • 1
  • 0
  • -
  • 1
  • 1
  • 1
  • 0
  • 0
    • Table 30 Audio selection register
  • 0
  • 0
  • 0
  • 1
  • 1
  • 0
  • 1
  • 1
• 13 Application information
  • 13.1 Software description
  • 13.2 Power supply connection and EMC
    • Fig.20 Application block diagram.
    • Fig.21 Application diagram (continued in Fig.22).
    • Fig.22 Application diagram (continued from Fig.21).
• 14 Package outline
  • 15 Soldering
  • 15.1 Introduction to soldering surface mount packages
  • 15.2 Reflow soldering
  • 15.3 Wave soldering
  • 15.4 Manual soldering
  • 15.5 Suitability of surface mount IC packages for wave and reflow soldering methods
    • Note s
      • 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, ...
      • 2. These packages are not suitable for wave soldering as a solder joint between the printed-circu...
      • 3. If wave soldering is considered, then the package must be placed at a 45� angle to the solder ...
      • 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or l...
      • 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or large...
• 16 Definitions
  • 17 Life support applications
  • 18 Purchase of Philips I2C components
• NOTES
• NOTES
  • Printed in The Netherlands 545002/01/pp60 Date of release: 1999Aug16 Document order number: 939...