1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

FEATURES

Single-chip solution including FM and vision filters,
analog demodulator and audio switching

Dual standard with automatic selection between PAL
system I and BGH

Suitable for conventional intercarrier PLL-IF
(single SAW) TV/VCR systems

Single low-radiation crystal oscillator for improved EMC

Stereo bitstream audio DACs

Programmable attenuator for matching levels of NICAM
and FM audio sources at the output of the device

Full EBU specification NICAM 728 demodulation and
decoding

Digital Audio Interface conforming with EBU/IEC 958

Automatic mute function which switches from NICAM to
FM sound when NICAM fails

Compatible with either single-ended or differential
DQPSK input signals

Microcomputer controlled via I

C-bus (up to 400 kHz

specification).

APPLICATIONS

Television receivers

Video cassette recorders.

GENERAL DESCRIPTION

Philips Semiconductors have pushed the boundaries of
Stereo Sound further with this addition to the successful
Terrestrial Digital Sound Decoder family. The SAA7284
device is an application specific version of the existing
SAA7283, with guaranteed improved specification on
selected parameters, enabling comparable RF
performance in conventional intercarrier PLL-IF systems,
to that of the SAA7283 in QSS systems.

The SAA7284 takes, as input, a second IF (intercarrier)
Terrestrial TV PAL signal, and performs all the Differential
Quadrature Phase Shift Keying (DQPSK) demodulation,
digital decoding and digital-to-analog conversion
necessary to produce a complete NICAM receiver on a
single integrated circuit.

The demodulator function includes integrated baseband
filters for pulse shaping and unwanted signal rejection,
automatic gain control, a low jitter integrated VCO, digital
monostables for precise data sampling points and a
multi-standard controller to enable automatic locking to
either a PAL system I or PAL system BGH input signal.

The decoder function performs the descrambling,
de-interleaving and reformatting operations required to
recover the original data words.

The data words are processed through a stereo digital
filter, digital de-emphasis network, second order noise
shaper and 256 times oversampling Bitstream audio DAC.

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

SAA7284ZP

SDIP52

plastic shrink dual in-line package; 52 leads (600 mil)

SOT247-1

SAA7284GP

QFP64

plastic quad flat package; 64 leads (lead length 1.95 mm);
body 14

2.8 mm

SOT319-2

1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

BLOCK DIAGRAM

handbook, full pagewidth

QUADRATURE MIXERS, BASEBAND FILTERS

AND

AGC GAIN STAGE

MBH216

PORT2

ADSEL

DOBM

SDA

SCL

DATAOUT

EXTR

FMR

PCLK

OPR

DATAIN

OSC

XTAL

CLKLPF

OPL

FML

EXTL

PORM

PORA

REMVE

PKDET

REMO

CEYE

SEYE

COFF

SOFF

DQPSK

MIXREF

VCLK

VCONT

DDD

SSD

VSSX

VSSF2

VDDF2

VRCF

I REF

VROF

DDF1

VSSF1

VSSDAC

VROA

RCA

VSSA

DDA

MUTE

RESET

SAA7284GP

COSINE

SINE

CARRIER LOOP

PHASE DETECTOR

AND DATA SLICERS

AGC

CONTROLLER

BITRATE

CLOCK

RECOVERY

CARRIER LOOP

QUADRATURE

VCO

CRYSTAL

OSCILLATOR

I C

DAI

DIGITAL FILTER, GAIN,

J17 DE-EMPHASIS

NOISE SHAPER

(RIGHT CHANNEL)

BITSTREAM DAC

(RIGHT CHANNEL)

OUTPUT

SWITCHES

AND

BUFFER

(RIGHT CHANNEL)

NOISE SHAPER

(LEFT CHANNEL)

BITSTREAM DAC
(LEFT CHANNEL)

OUTPUT

SWITCHES

AND

BUFFER

(LEFT CHANNEL)

NICAM 728 DECODER

AND

DEVICE CONTROLLER

(1)

Fig.1 Block diagram (QFP64).

(1) Represents controller bus.

1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

PINNING

SYMBOL

PIN

DESCRIPTION

SDIP52

QFP64

(1)

MUTE

active LOW mute input; function defined by MUTEDEF (control bit in the
I

C-bus register)

DOBM

digital audio interface output that can be 3-stated via I

C-bus

DDA

analog supply voltage for the audio channels

SSA

analog ground connection for the audio channels

RCA

internal audio reference voltage buffer (high-impedance node)

EXTR

external analog input to the right audio channel

FMR

FM sound input to the right audio channel

OPR

analog output from the right audio channel

n.c.

9 and 10

not connected; left open-circuit in application

ROA

internal audio reference voltage buffer output

SSDAC

quiet ground connection to DACs

n.c.

13 and 14

not connected; left open-circuit in application

OPL

analog output from the left audio channel

FML

FM sound input to the left audio channel

EXTL

external analog input to the left audio channel

PORM

active LOW power-on reset mute input; mute cleared by setting silence bit
HIGH in I

C-bus (internal pull-up)

PORA

power-on reset audio select input (internal pull-up)

REMVE

carrier loop-filter connection

REMO

carrier loop-filter output

SEYE

sine channel eye pattern output for monitoring

SOFF

sine channel offset compensator capacitor output

SSF1

demodulator ground connection 1

VCLK

carrier loop VCO clock output for monitoring

DDF1

demodulator supply voltage 1

VCONT

carrier loop VCO control voltage input

MIXREF

mixer voltage reference or input when using differential DQPSK signal

DQPSK

DQPSK input signal

COFF

cosine channel offset compensator capacitor output

CEYE

cosine channel eye pattern output for monitoring

PKDET

AGC peak detector storage capacitor output

ROF

internal demodulator reference voltage buffered output

REF

internal demodulator reference current output

RCF

internal demodulator reference voltage unbuffered output

DDF2

demodulator supply voltage 2

SSF2

demodulator ground connection 2

n.c.

not connected; left open-circuit in application

CLKLPF

clock loop-phase comparator output

1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

FUNCTIONAL DESCRIPTION

DQPSK demodulation

UADRATURE MIXERS

BASEBAND FILTERS AND AUTOMATIC

GAIN CONTROL

(AGC)

The DQPSK signal is fed into two differential input mixers,
where it is mixed with quadrature phases generated by the
carrier-loop quadrature VCO. The quadrature signals
modulated onto the NICAM carrier are thus recovered.

The mixers can be driven by either a single-ended or
differential source. In single-ended mode, the device is
driven directly from the sound IF down-converter into the
DQPSK input pin, with the MIXREF pin decoupled.
In differential mode, the signal is applied between the
DQPSK and MIXREF pins.

The outputs from the mixers are then fed into a
pulse-shaping filter, and FM/vision filter stage with
improved colour rejection to allow suitable performance
with SAW filters. The signal from the filtering stages is then
fed into the AGC, which ensures that the phase
comparator gain remains constant, irrespective of the
input signal level. This is important to maintain the stability
of Costas loop PLL.

AGC

CONTROLLER

The AGC controller monitors the I and Q channel signals
at the input to the carrier loop-phase comparator and
generates a reference voltage to set the AGC output level.

YE BUFFER

A differential to the single-ended converter provides the
baseband signal as an output at the pins CEYE and SEYE
for the I and Q channels respectively for eye-height
monitoring.

IT RATE CLOCK RECOVERY

The I and Q channels are processed using edge detectors
and monostables, which generate a signal with a coherent
component at the data symbol rate. The outputs from the
I and Q channel monostables are each compared with the
clock derived from PCLK (364 kHz nominal), the resultant
output is used to derive a 3-state control signal used to
control two current sources at the CLKLPF output.
This error signal is loop filtered and used to control the
master clock oscillator. The bit rate clock, PCLK, and
symbol clock are derived from the master clock.

NICAM 728 decoding

ECODING FUNCTIONS

The device performs all decoding functions in accordance
with the EBU NICAM 728 specification. After locking to the
frame alignment word, the data is de-scrambled by
application of the defined pseudo random binary
sequence, and the device synchronizes to the periodic
frame flag bit C0.

The relevant control information and scale factor word is
extracted, and with the integrated RAM the data is
de-interleaved and the scale factor word is extracted, and
expanded to 14 bits. Parity checking on the eleventh bit of
each sample word is carried out to reveal any sound
sample errors, which if detected are flagged, with the last
good sample being held.

Automatic muting

Enable when AMDIS = LOW. The I

C-bus section has two

registers which define an upper and lower limit for the
automatic muting function. When the number of errors
within a 128 ms period exceeds the number stored in the
upper error limit register, then the automatic muting will
switch the device output to the FM input, (dependent on
the relevant control bits in the I

C-bus) and mute (set to

zero) the data input to the filter (in that order). When the
error count in a 128 ms period is less than the value stored
in the lower error limit register then the data into the filter
is uninterrupted, and the device output is switched back to
the DAC (dependent on the value of the relevant control
bits in the I

C-bus). During the muting operation the

open-drain pin MUTE is pulled LOW and the AM bit in the
status-byte is set HIGH. Figure 4 shows the dependency
of the automatic muting function on error_count, RSSF,
C4OV, output state and application mode. The automatic
muting function, if enabled, will override user mute via the
MUTE pin/bit.

When the transmission is DATA format or currently
undefined format (C3 = logic 1) the device will
automatically switch to the FM inputs regardless of
RSSF/C4OV states, and whether the automatic muting
function AMDIS is enabled or disabled.

1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

User mute

The error counter is an 8-bit counter which locks at
count 255. The counter is reset and its output sent to the
I

C-bus every 128 ms. This enables the user to interrogate

the number of errors occurring within a 128 ms period.
The user can then mute the device by pulling pin MUTE
LOW (this function is also provided by the MUTE bit in the
I

C-bus) or setting SILENCE bit LOW in I

C-bus to switch

input of audio switching buffers to analog ground.

Switching buffers

The analog switches select between the output of the
DACs, the FM input and an external input (EXT).
Switching is controlled by bits in the I

C-bus and internal

switching function. The external analog inputs should be

1.1 V (RMS) at the input pin, and the output buffers have

a voltage drive of 1 V (RMS).

NICAM/FM audio level matching

Differing audio headroom and alignment levels occur
between systems I and BGH, due to the differing systems
and broadcast standards. In order to match the NICAM
and FM audio output levels without requiring application
changes, the device will automatically switch in 4.6 dB
attenuation network in the NICAM path for system BGH
(this can be disabled by setting the NICLEV bit LOW in
I

C-bus). A programmable attenuation network in the FM

path only, controlled by bits in I

C-bus, provides additional

flexibility for user to match FM and NICAM audio levels
(see Table 9).

Power-on reset state

Two pins control the initial set-up of the device during
power-on reset.

PORA (Power-On Reset Audio)

When pulled LOW the device will be configured with a
12 dB gain in the oversampling filter and the C4OV bit in
the I

C-bus will be set HIGH. This pin when HIGH will

configure the device with a 6 dB gain in the
oversampling filter and will set C4OV bit in the I

C-bus

LOW.

PORM (Power-On Reset Mute)

This pin when LOW will mute the output of the device at
power-on by setting the SILENCE bit in the I

C-bus

LOW. To put the device back into a normal mode of
operation the SILENCE bit in the I

C-bus must be set

HIGH.

1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

C-BUS FORMATS

The SAA7284 contains an I

C-bus slave transceiver (up to 400 kHz) permitting a master device to:

Read decoder status information derived from the transmitted digital audio signal

Read an error count byte to determine the bit error rate for user mute purposes and to indicate quality of NICAM signal

Write control codes to select PAL I or PAL BGH configurations

Write control codes to select the available analog switching configurations

Write upper and lower error count limits for automatic muting function

Read additional transmitted data bits. Their purpose has yet to be defined but accessibility is provided to allow future
services to be implemented in receiver software.

C-bus slave address

An address select pin (ADSEL) is provided to allow selection of one of two different slave addresses. The logic state of
the ADSEL pin is reflected in the least significant bit of the I

C-bus slave address.

Slave address = 101101X (R/W) [ADSEL = 1, address = B6 (R/W) ADSEL = 0, address = B4 (R/W)].

Table 1

SAA7284 slave address

The SAA7284 does not acknowledge the I

C-bus general call address.

Slave receiver format

The slave receiver format is shown in Table 2.

Table 2

Slave receiver format

Table 3

Explanation of Table 2

The sub-address is auto-incremented by the SAA7284, for each data byte received. When the sub-address is equal to
04 (HEX), on reception of the next data byte, the sub-address will reset to 00 (HEX).

BITS

selected by ADSEL

read/write

START

slave_addr

ACK

sub_addr

ACK

data_byte

ACK

n-bytes

data_byte

ACK

STOP

ITEM

DESCRIPTION

START

C-bus start condition

Slave_addr

101101XW

logic 0 when ADSEL = 0; logic 1 when ADSEL = 1

logic 0, I

C-bus write to slave receiver

ACK

C-bus acknowledge condition generated by slave receiver

Sub_addr

sub-address range 00 to 04 (HEX)

Data_byte

data byte transmitted to slave receiver

STOP

C-bus stop condition

1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

C-bus slave receiver register map

Table 4

Slave receiver data byte

SUB-ADDRESS

000

M1/M2

DMSEL

SSWIT3

SSWIT2

SSWIT1

PORT2

MUTEDEF

AMDIS

001

EMAX7

EMAX6

EMAX5

EMAX4

EMAX3

EMAX2

EMAX1

EMAX0

010

EMIN7

EMIN6

EMIN5

EMIN4

EMIN3

EMIN2

EMIN1

EMIN0

011

C4OV

MUTE

SILENCE

DAIE

FM3

FM2

FM1

FM0

100

ASYS

BG/I

NICLEV

STLOCK

M1/M2

This bit selects either mono channel M1 or M2 to be the
output on the left and right channel dependent on the
transmitted control bits C1 and C2 indicating a mono
transmission and the value of bit DMSEL (see Table 5).
Power-on resets to logic 1.

DMSEL

DMSEL is the dual mono selection bit, for transmissions
consisting of two independent mono signals. Selection is
in conjunction with M1/M2 (see Table 5). Power on resets
to logic 0.

SSWIT1, SSWIT2

AND

SSWIT3

These bits control the analog switching, selecting between
the FM, external, and NICAM signals. With the NICAM
source the signals select whether the de-emphasis is
performed and what gain is applied after the filtering and
de-emphasis stage. The signal states and their meaning
are listed in Table 7. Power-on resets to 010 with PORA
pin HIGH, and to 011 with PORA pin LOW.

PORT2

PORT2 controls a bit out, providing direct access to a
dedicated output pin (PORT2) via the I

C-bus.

See Table 6. Power-on resets to logic 0.

MUTEDEF

This defines the operation of the user definable MUTE pin
or MUTE I

C-bus bit when it is pulled LOW externally or set

LOW in the I

C-bus respectively.

When this bit is HIGH, pulling the MUTE pin/I

C-bus bit

LOW will mute (set to zero) the digital data and switch the
output to the FM input, depending on relevant control bits
(see Table 8). When this bit is LOW, pulling the MUTE
pin/I

C-bus bit LOW will only mute the digital data under

the same conditions. Power-on resets to LOW.

AMDIS

This bit enables and disables the automatic mute function.
Power-on resets to enabled = LOW.

EMAX7

EMAX0

This is the upper error limit register which defines the
number of errors in 128 ms period which will cause
automatic mute to switch IN. User definable, but power-on
resets to 50 (HEX).

EMIN7

EMIN0

This is the lower error limit register which defines the
number of errors in 128 ms period which will cause
automatic mute to switch OUT. User definable, but
power-on resets to 14 (HEX).

C4OV

When set LOW this bit overrides the status of the
transmitted C4-bit when muting. When this bit is HIGH
muting takes place in accordance with EBU specification.
Power-on resets to HIGH when the PORA pin is held LOW
during power-up, and power-on resets to LOW when
PORA is HIGH.

MUTE

This reflects the function of the MUTEB pin. When this bit
is set LOW the external MUTEB pin is pulled LOW and the
action is dependent on the MUTEDEF bit (see Table 8).
Power-on resets to HIGH.

SILENCE

When set LOW this bit silences the outputs of the device
by switching the input of the audio switching buffers to
analog ground. When the PORM pin is held LOW at
power-on reset the silence bit is initialized to zero.
With PORM bit HIGH the silence bit is initialized HIGH.

1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

DAIE

When set HIGH this bit switches in the Digital Audio
Interface output to the DOBM pin. When set LOW the
DOBM output is 3-stated. Power-on resets to HIGH.

FM3

FM0

These bits set the level of attenuation of the FM audio
signal (see Table 9). Power-on resets 0000 = 0 dB
attenuation.

ASYS

When this bit is HIGH it activates the automatic standard
switch mode. When set LOW, the standard must be set by
the BG/I bit. Power-on resets to HIGH.

BG/I

When this bit is HIGH it switches the DQPSK demodulator
to system BGH and attenuates the digital audio level by

4.6 dB (if NICLEV is set HIGH). When LOW, the DQPSK
demodulator switches to system I (with no 4.6 dB
attenuation). Power-on resets to HIGH.

NICLEV

When this bit is set LOW it overrides the 4.6 dB NICAM
audio level compensation, irrespective of whether the
device is in automatic or manual system mode. When set
HIGH the 4.6 dB compensation level is applied in
system BGH. Power-on resets to HIGH.

STLOCK

When STLOCK is set HIGH it will stop the automatic
system switch after the device has achieved an INSYNC
condition, should the demodulator lose lock at any time.
This minimizes the re-acquisition time. When set LOW the
device will be permitted to change system after an
INSYNC condition has been reached. Power-on resets to
LOW.

Table 5

Output as a function of M1/M2 and DMSEL

DMSEL

M1/M2

FUNCTION

selects DIGITAL; L = M2, R = M2

selects DIGITAL; L = M1, R = M1

selects DIGITAL; L = M2, R = M1

selects DIGITAL; L = M1, R = M2

Table 6

Port 2 control

PORT2

PIN OUTPUT STATE

LOW

HIGH

Table 7

SSWIT signal states and function

Note

1. Where X = don't care.

SSWIT3

SSWIT2

SSWIT1

FUNCTION

NICAM source de-emphasis switched out, no gain

NICAM source de-emphasis switched in, no gain

NICAM source de-emphasis switched in, +6 dB gain; power-on reset when
PORA = HIGH

NICAM source de-emphasis switched in, +12 dB gain; power-on reset when
PORA = LOW

(1)

external inputs switched in, no change to previous de-emphasis/gain setting

FM inputs switched in, no change to previous de-emphasis/gain setting

1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

Table 8

Action of pulling MUTE pin/I

C-bus bit LOW

Note

1. With MUTE pin/i

C-bus bit pulled LOW. If user has manually selected FM or NICAM inputs, no switching will occur.

Table 9

FM attenuation control

Slave transmitter format

The slave transmitter format is shown in Table 10.

Table 10 Slave transmitter format

TRANSMITTED

C4 BIT (RSSF)

C4OV

TRANSMISSION MODE

OUTPUT ACTION

(1)

MUTEDEF = 1

MUTEDEF = 0

1 or 0

stereo/mono/dual mono with L and R = M1

mute digital data
and switch to FM

mute digital data
only

1 or 0

dual mono with M2 selected in either L or R

no action

all modes

no action

all modes

mute digital data
and switch to FM

mute digital data
only

FM ATTENUATION (dB)

FM3

FM2

FM1

FM0

Not defined

START

slave_addr

ACK

data_byte

ACK

n-bytes

data_byte

ACK

STOP

1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

Table 11 Explanation of Table 10

C slave transmitter register map

The bus master can perform single-byte, two-byte, three-byte, four-byte or five-byte read in the order shown in Table 12.

Table 12 Slave transmitter data byte

ITEM

DESCRIPTION

START

C-bus start condition

Slave_addr

101101XR

logic 0 when ADSEL = 0; logic 1 when ADSEL = 1

logic 1, I

C-bus read from slave transmitter

ACK

C-bus acknowledge condition generated by slave receiver

Data_byte

data byte transmitted from slave receiver

ACK

master device negative acknowledge to indicate last byte

STOP

C-bus stop condition

BYTE

STATUS BYTE 1

PONRES

S/M

D/S

VDSP

RSSF

CFC

ERROR BYTE

ERR7

ERR6

ERR5

ERR4

ERR3

ERR2

ERR1

ERR0

AD BYTE 0

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

AD BYTE 1

OVW

SAD

CI1

CI2

AD10

AD9

AD8

STATUS BYTE 2

BG/I

PONRES

When set HIGH this bit indicates that a power-on reset has
occurred. It is cleared after the status byte has been read.

S/M

This bit gives the stereo or mono broadcast indication.
Set HIGH indicates stereo transmission.

D/S

When HIGH this bit indicates a dual mono broadcast.

VDSP

When this bit is HIGH, it indicates that the digital data
transmission is a sound source. When LOW the
transmission is either data or undefined format.

RSSF

This bit reflects the state of the C4 bit in the NICAM
transmission. When set LOW, the FM sound content does
not match the digital transmission, and switching to FM by
automatic mute or setting MUTE LOW is prevented
(if C4OV = HIGH).

When HIGH this bit indicates that the device has both
frame and C0 (16 frame) synchronization.

When HIGH this bit indicates that the automatic mute
function has switched from NICAM to FM. When LOW the
automatic mute function has not activated a switch.

CFC

When LOW this bit indicates a configuration change at the
C0 (16 frame) boundary. It is reset after reading the status
byte.

ERR7

ERR0

These bits indicate the number of errors occurring in the
previous 128 ms period.

AD7

AD0

These bits contain the eight least significant additional
data bits.

1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

OVW

This bit is set when new additional data bits are written to
the I

C-bus without the previous bits being read.

SAD

This bit is set HIGH when new additional data is written
into the I

C-bus, and cleared by the action of reading the

data.

CI1

AND

CI2

These are the CI bits decoded by majority logic from the
parity checks of the last ten samples in a frame.

AD10, AD9

AND

AD8

These are the three most significant additional data bits.

C1, C2

AND

These are the transmitted control bits, see Table 13.

BG/I

When set HIGH this bit indicates that the DQPSK
demodulator is switched to system BGH. When LOW,
indicates that DQPSK demodulator is switched to
system I.

Indicator bits

Table 13 is the truth table for the indicator bits.

Table 13 Indicator bits functional truth table

TRANSMISSION

S/M

D/S

VDSP

Stereo

M1 + M2

M1 + data

Transparent data

Any currently undefined combination of C1, C2 and C3

Decoder unsynchronized (OS = logic 0)

1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

DIGITAL AUDIO INTERFACE IEC/EBU 958

Block structure

The output is grouped into a block of 192 consecutive
frames providing, for each channel the 192 channel status
data bits. The start of a block is designated by a special
sub-frame preamble.

Frame structure

Each frame is uniquely composed of two sub-frames.
The rate of transmission of frames corresponds exactly to
the source sampling frequency. In the 2-channel
operation, samples taken from both channels are
transmitted by time multiplexing in consecutive
sub-frames. Sub-frames related to Channel 1 (left or `A'
channel in stereophonic operation and primary channel in
monophonic operation) normally use preamble M.
However the preamble is changed to preamble B once
every 192 frames. This defines the block structure used to
organize the channel status information. Sub-frames of
Channel 2 (right or `B' channel in stereophonic operation
and secondary channel in monophonic operation) always
use preamble W.

Sub-frame structure

Each frame is divided into 32 time-slots numbered 0 to 31.

Time-slots 0 to 3 carry one of three permitted preambles.
These are used to affect synchronization of sub-frames,
frames and blocks.

Time-slots 4 to 27 carry the audio sample word in linear
two's complement representation. The most significant bit
is carried by time-slot 27.

Time-slot 28 carries the validity flag associated with the
audio sample word. This flag is set to logic 0 if the audio
sample is reliable. If set to logic 1 then the sample is
unreliable.

Time-slot 29 carries one bit of the user data channel.
In this application this is not used and so is set to logic 0.

Time-slot 30 carries one bit of the channel status word
associated with the audio channel transmitted in the same
sub-frame.

Time-slot 31 carries a parity bit such that time-slots 4 to 31
inclusive will carry an even number of ones and an even
number of zeros.

Fig.5 Frame format.

handbook, full pagewidth

MLB155

channel 1

sub-frame

channel 2

channel 1

channel 2

channel 1

channel 2

sub-frame

frame 0

start of block

frame 1

frame 191

Fig.6 Sub-frame structure.

handbook, full pagewidth

MLB156

sync

preamble

logical 0 bits

audio sample word

S
B

U C

S
B

validity flag

user data = logic 0

channel status

parity bit

11 12

1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

Channel coding

Time-slots are encoded as biphase mark data. Each bit
transmitted is represented by a symbol comprising two
consecutive binary states. The first state of a symbol is
always different from the second state of the previous
symbol. The second state of the symbol is identical to the
first if the bit being transmitted is logic 0, however it is
different if the bit is logic 1 (see Table 14).

Table 14 Channel coding

Preambles

Preambles are specific patterns providing synchronization
and identification of the sub-frames and blocks.

A set of three preambles is used. These preambles are
transmitted in the time allocated to four time-slots and are
represented by eight successive states. The first state of
the preamble is always different from the second state of
the previous symbol. Depending on this state the
preambles are as shown in Table 15.

PRECEDING STATE

TRANSMITTED BIT

CHANNEL CODING

Table 15 Preambles

The preambles preceding each digital audio sample are
used to indicate the beginning of a sample as follows:

Preamble B indicates the start of Channel A data and
the beginning of a block

Preamble M indicates the start of Channel A data but
not the beginning of a block

Preamble W indicates the start of Channel B data.

Channel status

The channel status information is organized in 192-bit
words. The first bit of each word is carried in the frame with
Preamble B. The 192-bit word is organized into sections
as shown in Table 16.

PRECEDING STATE

PREAMBLE

CHANNEL CODING

11101000

00010111

11100010

00011101

11100100

00011011

Table 16 Channel status codes

BIT

CODE

DESCRIPTION

consumer

sound data

digital copy permitted

3 and 4

indicates digital de-emphasis switched in

indicates digital de-emphasis switched out

6 and 7

8 to 15

00110001

category code

16 to 19

0000

source code (don't care)

20 to 23

0000

channel number (don't care)

24 to 27

1100

sampling frequency (32 kHz)

28 and 29

clock accuracy (level II)

30 to 191

all 0s

1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

LIMITING VALUES

In accordance with the Absolute Maximum Rating Systems (IEC 134).

Notes

1. All V

and V

connections must be made externally to the same power supply.

2. Electrostatic handling is equivalent to discharging a 100 pF capacitor via a 1.5 k

series resistor with a 15 ns rise

time.

3. Electrostatic handling is equivalent to discharging a 200 pF capacitor via a 0

series resistor with a 15 ns rise time.

QUALITY AND RELIABILITY

This device will meet Philips Semiconductors General Quality Specification for Business group

"Consumer Integrated

Circuits SNW-FQ-611-Part E".

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

DDF1

, V

DDF2

, V

DDA

supply voltage (all supplies)

note 1

0.3

+6.5

SSF1

, V

SSF2

, V

SSA

ground supply voltage

SSD

0.5 V

SSD

+ 0.5 V

I(max)

maximum input voltage (any input)

O(max)

maximum output voltage

IOK

DC input or output diode current

O(max)

output current (each output)

amb

ambient operating temperature

+70

stg

storage temperature

+125

electrostatic handling

stat(HBM)

Human Body Model

note 2

2000

+2000

stat(MM)

Machine Model

note 3

200

+200

1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

SYSTEM PERFORMANCE

Bit Error Rate (BER)

Table 17 shows input signal conditions which typically produce bit error rates of less than 10

. Signal levels given in dB

are related to the picture carrier reference level (0 dB) and based on the output level of the set up as shown in Fig.8.
All measurements are at RF and using Philips Semiconductors SAA7284 Applications Board.

Table 17 System performance

Notes

1. Measurements made with colour bar at 100% modulation.

a) FM level =

10 dB system I;

13 dB system BG.

b) NICAM level =

20 dB (unless otherwise specified).

2. 10 dB sound shelf with extended bandwidth for NICAM signal.

3. 14 dB sound shelf with extended bandwidth for NICAM signal.

Acquisition time

Maximum acquisition time = 1 s, measured from power-on to reset in-sync condition achieved.

INPUT SIGNAL CONDITIONS

(1)

SYSTEM I

SYSTEM BG

UNIT

SAW A

(2)

SAW B

(2)

SAW C

(3)

Picture carrier RF level (FM deviation =

50 kHz)

NICAM level with respect to picture carrier (FM deviation =

50 kHz)

FM overmodulation

>120

>100

kHz

1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

CHARACTERISTICS

= 4.5 to 5.5 V; T

amb

20 to +70

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Digital supplies (note 1)

DDD

digital supply voltage

4.5

5.0

5.5

SSD

digital ground supply voltage

DDD

digital supply current

Audio supplies (note 1)

DDA

audio supply voltage

4.5

5.0

5.5

SSA

audio ground supply voltage

SSDAC

DAC ground supply voltage

DDA

audio supply current

Demodulator supplies (note 1)

DDF1

1st front-end supply voltage

4.5

5.0

5.5

SSF1

1st front-end ground supply
voltage

DDF1

1st front-end supply current

DDF2

2nd front-end supply voltage

4.5

5.0

5.5

SSF2

2nd front-end ground supply
voltage

DDF2

2nd front-end supply current

125

Digital inputs

DATAIN (TTL/CMOS

COMPATIBLE INPUT LEVELS

)

LOW level input voltage

0.8

HIGH level input voltage

2.0

input leakage current

+10

input capacitance

ADSEL, PORM

AND

PORA (TTL/CMOS

COMPATIBLE INPUT LEVELS WITH INTERNAL PULL

)

LOW level input voltage

0.8

HIGH level input voltage

2.0

i(pu)

input pull-up resistance

input capacitance

RESET

AND

SCL (CMOS/I

C-

BUS INPUT LEVELS WITH SCHMITT TRIGGER

)

LOW level input voltage

1.5

HIGH level input voltage

3.0

hys

hysteresis

0.05V

input leakage current

+10

input capacitance

1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

Digital input/output

SDA (I

C-

BUS LEVELS WITH SCHMITT TRIGGER

OPEN

DRAIN OUTPUT

)

LOW level input voltage

1.5

HIGH level input voltage

3.0

hys

hysteresis

0.05V

input leakage current

+10

input capacitance

LOW level output voltage

= +3 mA

0.4

load capacitance

active pull-up

400

passive pull-up

200

MUTE (TTL/CMOS

COMPATIBLE INPUT LEVELS

OPEN

DRAIN OUTPUT WITH INTERNAL PULL

)

LOW level input voltage

0.8

HIGH level input voltage

2.0

input capacitance

LOW level output voltage

= +3 mA

0.4

HIGH level output voltage

3 mA

2.4

load capacitance with active
pull-up

input impedance

Digital outputs

PORT2, PCLK

AND

DATAOUT (

PUSH

PULL OUTPUT

)

LOW level output voltage

= +2 mA

0.4

HIGH level output voltage

2 mA

2.4

load capacitance

DOBM (3-

STATE PUSH

PULL OUTPUT

)

LOW level output voltage

= +2 mA

0.4

HIGH level output voltage

2 mA

2.4

load capacitance

3-state leakage current

= 0 to V

+10

ANALOG SECTION (measured at V

= 5 V; T

amb

= 25

Demodulator analog references

RCF

OUTPUT

output signal voltage

supply dependent

0.5V

DDF2

input capacitance

ROF

OUTPUT

output signal voltage

defined by V

RCF

0.5V

DDF2

input capacitance

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

REF

OUTPUT

output signal voltage

defined by V

RCF

0.5V

DDF2

input capacitance

sink

output sink current

with external 10 k

resistor from pin to
V

SSF2

250

Signal path analog inputs

DQPSK

AND

MIXREF

input resistance

12.5

iDQPSK(rms)

NICAM input signal voltage V

nom

(RMS value)

10 dB SAW sound
shelf

24.5

14 dB SAW sound
shelf

15.5

iDR

AGC range

with respect to
V

iDQPSK

; 10 dB SAW

+10

with respect to
V

iDQPSK

; 14 dB SAW

+10

iCUM(rms)

cumulative input signal voltage
(RMS value)

note 2

464

input capacitance

Baseband outputs

CEYE

AND

SEYE

o(p-p)

eye pattern output signal voltage
(peak-to-peak value)

in-lock; system I;
note 3

1.25

in-lock; system B/G;
note 3

1.79

I/Q

channel matching

20log

CEYE

SEYE

)

COFF

AND

SOFF

offset compensator DC output
voltage

defined by V

RCF

0.5V

DDF2

Baseband filters

YSTEM

pass band cut-off attenuation

= 6552 MHz

+ 182 kHz

1.9

3.1

4.6

FMr

FM rejection

= 6.0 MHz

50 kHz

FMomr

FM rejection (overmodulated FM)

= 6.0 MHz

80 kHz

CCr

colour-carrier rejection

= 4.43 MHz

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

YSTEM

BGH

pass band cut-off attenuation

= 5850 MHz

+ 182 kHz

1.7

3.1

4.5

FMr

FM rejection

= 5.5 MHz

50 kHz

FMomr

FM rejection (overmodulated FM)

= 5.5 MHz

80 kHz

CCr

colour-carrier rejection

= 4.43 MHz

Baseband demodulator output

REMO

output voltage limits

0.2

0.5

carrier loop-phase detector gain

system I

1.2

V/rad

system B/G

0.9

V/rad

carrier loop pull-in frequency

kHz

offset

carrier loop-phase detector offset

phase shift = 45

deg

carrier loop bandwidth
(natural frequency)

kHz

Baseband remodulator filter feedback

REMVE

carrier loop filter virtual earth
voltage

defined by V

RCF

0.5V

DDF2

Fine frequency calibration current (on to REMVE node)

source

output source current

sink

output sink current

3-state leakage current

0.25

+0.25

fstep

fine frequency calibration step

0.8

kHz

Voltage controlled oscillator

VCONT

input signal voltage

0.5

input capacitance

VCO (

MEASURED AT V

CLK

)

VCO

VCO frequency after DAC
calibration

SYS

= 6552 MHz

(system I) or
f

SYS

= 5.85 MHz

(system BGH)

SYS

+ 75

kHz

VCO frequency after fine
frequency calibration

SYS

+ 4

kHz

VCO

VCO slope

system I

139

186

232

kHz/V

system B/G

191

255

319

kHz/V

DAC

STEP

VCO calibrating DAC step size

+30

+50

kHz

ItoQ

in-phase to quadrature phase
accuracy

deg

VCO phase jitter

note 4

8.1

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

Clock recovery loop and crystal oscillator

XTAL

input capacitance

bias

DC bias voltage

3.63

OSC

osc(p-p)

oscillator voltage amplitude
(peak to peak value)

1.4

bias

DC bias voltage

2.33

small signal voltage gain

1.0

V/V

output capacitance

CRYSTAL SPECIFICATION

(

FUNDAMENTAL MODE

)

crystal input frequency

8.192

MHz

load capacitance

series capacitance

parallel capacitance

pulling sensitivity

determined by C

C1 and C0

26.25

/pF

resonance resistance

DLD

resonance resistance; drive level
dependency

120

ageing

/year

range

temperature range

+25

+70

adjustment tolerance

drift

across T

range

CLOCK RECOVERY LOOP CURRENT SOURCE

(CLKLPF)

3-state leakage current at

phase shift

0.5

CLKLPF

0.5; note 5

phase comparator
transconductance

0.5

CLKLPF

0.5; note 5

63.5

A/rad

Analog references

RCA

OUTPUT

output signal voltage

supply dependent

0.5V

DDA

input capacitance

ROA

OUTPUT

output signal voltage

defined by V

RCA

0.5V

DDA

input capacitance

Digital filter

output sample frequency

128

kHz

pass band ripple

at 0 Hz to 15 kHz

0.01

SBA

stop band attenuation

at f

17 kHz

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

Digital de-emphasis

DEV

deviation from ideal

0.09

FM audio inputs

FML

AND

FMR (

SELECTED VIA

C-

BUS CONTROL

)

input impedance

0 dB FM attenuation
set

12 dB FM

attenuation set

160

output gain

programmable in
1 dB steps

0 to 12

output gain accuracy

0.5

+0.5

ain(rms)

input voltage level (RMS value)

1.1

S/N

signal-to-noise ratio

THD

total harmonic distortion

EXT audio input

EXTL

AND

EXTR (

SELECTED VIA

C-

BUS CONTROL

)

input impedance

output gain

output gain accuracy

ain(rms)

input voltage level (RMS value)

1.1

S/N

signal-to-noise ratio

THD

total harmonic distortion

NICAM internal DAC (selected via I

C-bus control)

o(rms)

NICAM output voltage level
(RMS value)

0 dB; V

ROA

= 2.5 V

0.94

1.06

THD+N

total harmonic distortion plus
noise

notes 6 and 7

DIGS

digital silence level

MUTE on

AUDIOS

audio silence level

SILENCE on = 0

Audio outputs

OPL

AND

OPR

output load capacitance

300

output load resistance

CHM

channel matching

0 dB, 1 kHz

0.5

+0.5

PSRR

power supply rejection ratio

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

Notes

1. It is assumed that all supplies are externally connected at the same source, and consequently that maximum and

minimum values apply simultaneously to each supply.

2. Cumulative input level based on FM at 0 dB and NICAM at

10 dB with respect to picture carrier.

3. The signal amplitude present at the SEYE and CEYE pins depends on whether the demodulator is in or out-of-lock.

When out-of-lock, the signal at the pins is

2 times the in-lock situation.

4. VCO jitter is measured in System I over 100 cycles of the VCO clock.

5. With 10 k

resistor from I

REF

to V

SSF2

6. Audio performance is limited by the dynamic range of the NICAM 728 system. Due to compansion, the quantization

noise is never lower than

62 dB with respect to the input level.

7. Measured with a

30 dB, 1 kHz NICAM 728 input signal.

8. Note that a transmitter must internally provide at least a hold time to bridge the undefined region (max. 300 ns) of the

falling edge of SCL.

9. If a fast I

C-bus device is used in an up to 100 kbit/s I

C-bus system, then the requirement t

SU;DAT

250 ns is always

fulfilled if this device cannot stretch the LOW level of the SCL signal. If a device stretches the LOW level of the SCL
signal, then data to SDA must be asserted (t

RD(max)

+ t

SU;DAT

) = 1000 + 250 = 1250 ns before the SCL signal is

released to be compatible with the up to 100 kbit/s I

C-bus specification.

Timing (all timing values refer to V

and V

levels)

DATAIN

WITH RESPECT TO

PCLK (see Fig.9)

SU;DAT

data set-up time

100

HD;DAT

data hold time

250

SDA

WITH RESPECT TO

SCL(see Fig.10)

SCL

SCL clock frequency

400

kHz

BUF

bus free time

1300

HD;STA

START code hold time

600

LOW

SCL clock LOW time

1300

HIGH

SCL clock HIGH time

600

SU;STA

START code set-up time

600

HD;DAT

data hold time

note 8

SU;DAT

data set-up time

note 9

100

SDA and SCL rise time

300

SDA and SCL fall time

300

SU;STO

STOP code set-up time

600

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

APPLICATION INFORMATION

handbook, full pagewidth

DATAOUT

EXTR

FMR

PCLK

OPR

n.c.

DATAIN

n.c.

OSC

XTAL

n.c.

CLKLPF

n.c.

OPL

FML

EXTL

PORM

PORA

REMVE

PKDET

REMO

DDD

SSD

SSX

SSF2

DDF2

RCF

REF

ROF

SSDAC

ROA

RESET

TEST

SAA7284

n.c.

CEYE

SEYE

COFF

SOFF

DQPSK

MIXREF

VCLK

VCONT

VDDF1

VSSF1

n.c.

PORT2

ADSEL

DOBM

SDA

SCL

VRCA

SSA

VDDA

MUTE

n.c.

MBH225

100

SSF2

DDF2

2.2

100

220

100

10 k

22 k

330 nF

22 nF

SSF2

100 pF

1 M

8.192 MHz

6.8

BB405

SSF2

100 nF

SSD

BAW62

680 k

470 nF

DDD

SSD

DDD

SSA

SSD

100

SSA

100

SSA

DDA

digital

audio

interface

SCL

SDA

SSD

I C bus

connector

1 M

SSA

10 k

audio

left

100

SSA

1.8 k

47 nF

33 k

1 M

SSA

10 k

audio

right

220

EXTL

FML

FMR

EXTR

220

SSA

SSF2

100

SSF1

1 k

SSF1

390 pF

SSF1

100

SSF1

2.2

DDF1

DQPSK input

V (5 V)

supply

connector

Fig.11 Application diagram for QFP64.

1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

SOLDERING

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

SDIP

OLDERING BY DIPPING OR BY WAVE

The maximum permissible temperature of the solder is
260

C; solder at this temperature must not be in contact

with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg max

). If the

printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

EPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300

C it may remain in

contact for up to 10 seconds. If the bit temperature is
between 300 and 400

C, contact may be up to 5 seconds.

QFP

EFLOW SOLDERING

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

"Quality

Reference Handbook" (order code 9397 750 00192).

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary from
50 to 300 seconds depending on heating method.
Typical reflow temperatures range from 215 to 250

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheat for 45 minutes at 45

AVE SOLDERING

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.

The footprint must be at an angle of 45

to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured. Maximum permissible solder
temperature is 260

C, and maximum duration of package

immersion in solder is 10 seconds, if cooled to less than
150

C within 6 seconds. Typical dwell time is 4 seconds

at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

EPAIRING SOLDERED JOINTS

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320

1996 Oct 24

Philips Semiconductors

Preliminary specification

Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems

SAA7284

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PURCHASE OF PHILIPS I

C COMPONENTS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

C components conveys a license under the Philips' I

C patent to use the

components in the I

C system provided the system conforms to the I

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors a worldwide company

SCA52

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811

Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341

Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327

Portugal: see Spain

Romania: see Italy

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 247 9145, Fax. +7 095 247 9144

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Slovenia: see Italy

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494

South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 829 1849

Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 3 301 6312, Fax. +34 3 301 4107

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 632 2000, Fax. +46 8 632 2745

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2686, Fax. +41 1 481 7730

Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66,
Chung Hsiao West Road, Sec. 1, P.O. Box 22978,
TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381

Uruguay: see South America

Vietnam: see Singapore

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

Argentina: see South America

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101, Fax. +43 1 60 101 1210

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773

Belgium: see The Netherlands

Brazil: see South America

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700

Colombia: see South America

Czech Republic: see Austria

Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 1949

Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580/xxx

France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300

Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240

Hungary: see Austria

India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.
Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722

Indonesia: see Singapore

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,
Tel. +972 3 645 0444, Fax. +972 3 649 1007

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381

Middle East: see Italy

Printed in The Netherlands

537021/1200/01/pp40

Date of release: 1996 Oct 24

Document order number:

9397 750 01426

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SAA7284GP

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SAA7284GP