Document Outline
- FEATURES
- DESCRIPTION
- QUICK REFERENCE DATA
- ORDERING INFORMATION
- BLOCK DIAGRAM
- PINNING
- QUALITY AND RELIABILITY
- LIMITING VALUES
- CHARACTERISTICS
- TIMING CHAIN
- ON-CHIP MEMORY
- Page memory organization
- Extension packet memory organization
- ENHANCED MODE
- VPT data memory organization
- CLOCK SYSTEMS
- CHARACTER SETS
- APPLICATION INFORMATION
- PACKAGE OUTLINES
- SOT240-1
- SOT247-1
- SOT319-2
- SOLDERING
- DEFINITIONS
- LIFE SUPPORT APPLICATIONS
DATA SHEET
Preliminary specification
Supersedes data of June 1994
File under Integrated Circuits, IC02
1996 Nov 04
INTEGRATED CIRCUITS
SAA5281
Integrated Video input processor
and Teletext decoder (IVT1.8*)
1996 Nov 04
2
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
FEATURES
Complete Teletext and VPS decoding in a single
package
Built-in 8K
8 memory for up to 8 page storage
Enhanced mode allows 7 Fastext pages and 8 pages of
TOP to be captured
Ability to request only subtitle pages
Acquisition and decoding of VPS data
Data valid output available to indicate reception of
error-free VPS or packet 8/30/2 data
Software and hardware compatible with SAA5246 and
SAA5248
Meshing display within boxes
Separate data checking algorithms and pointers for
each acquisition channel
24 : 18 Hamming checker
Automatic packet 26 extension character processing
Indication of Line 23 for external use
13.5 MHz clock output to drive external microcontroller
Detection of Spanish transmissions to disable
flicker-stopper
Compatible with Philips' one-chip TV IC (TDA836X) for
scan-locking applications.
DESCRIPTION
The IVT1.8* is a single-chip Teletext decoder IC for
decoding 625-line based World System Teletext
transmissions. The device is based on IVT1.0VPS and has
reception facilities for the 5 MHz biphase VPS signal. It is
intended for use in video recorders, in particular to
implement the VPT facility (VCR programming via
Teletext). With suitable software both VPT standards
(EBU PDC System A and System B) can be
accommodated to allow operation from any European VPT
transmission. Automatic processing of packet 26
transmissions is also possible. No external memory is
required as an 8K
8 DRAM is included on-chip for up to
8 page storage. An enhanced mode allows 7 Fastext
pages to be stored, with one chapter used to store
extension packets.
QUICK REFERENCE DATA
ORDERING INFORMATION
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
V
DD
supply voltage
4.5
5.0
5.5
V
I
DD
supply current
-
75
150
mA
V
sync
sync voltage amplitude
0.1
0.3
0.6
V
V
vid(p-p)
video input voltage amplitude
(peak-to-peak value)
0.7
1.0
1.4
V
f
xtal
crystal frequency
-
27
-
MHz
T
amb
operating ambient temperature
-
20
-
+70
C
TYPE NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
SAA5281P
DIP48
plastic shrink dual in-line package; 32 leads (400 mil)
SOT240-1
SAA5281ZP
SDIP52
plastic shrink dual in-line package; 52 leads (600 mil)
SOT247-1
SAA5281GP
QFP64
plastic quad flat package; 64 leads
(lead length 1.95 mm); body 14
20
2.8 mm
SOT319-2
1996 Nov 04
3
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
BLOCK DIAGRAM
Fig.1 Block diagram; pin numbers for DIP48 (SOT240-1).
handbook, full pagewidth
MBD783
ANALOG
REFERENCE
GENERATOR
ANALOG
TO
DIGITAL
CONVERTER
INPUT
CLAMP
AND SYNC
SEPARATOR
ANALOG
OUTPUT
BUFFER
27 MHz
CLOCK
GENERATOR
7
8
12
36
2
3
37
11
4
DISPLAY CLOCK
PHASE-LOCKED
LOOP
13
TELETEXT
OR
VPS CONTROL
DATA SLICER
AND CLOCK
REGENERATOR
14
25
5
TIMING
CHAIN
44
SERIAL-TO
-PARALLEL
CONVERTER
TELETEXT
AQUISITION
AND DECODING
VPS
ACQUISITION
AND
DECODING
INTERFACE
I C-BUS
2
23
24
24 TO 18
HAMMING
DECODER
PACKET 26
PROCESSING
ENGINE
21
POWER-ON
RESET
DRAM
REFRESH
AND
TIMING
8K x 8
DRAM
DISPLAY
22
19
20
18
15
16
17
1
10
VDD1
VDD2
Y
BLAN
COR
RGBREF
R
G
B
ODD/EVEN
(or DV)
REF
IREF
6
9
VSS1
CVBS
BLACK
STTV/LFB
VSS2
VSS3
CLK EN
OSCOUT
OSCIN
OSCGND
CLK O/P
POL
VCR/FFB
LINE 23
SDA
SCL
SAA5281
MEMORY
INTERFACE
1996 Nov 04
4
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
PINNING
SYMBOL
PIN
DESCRIPTION
SOT240-1 SOT247-1 SOT319-2
V
DD1
1
52
11
+5 V supply 1
OSCOUT
2
1
13
27 MHz crystal oscillator output
OSCIN
3
2
14
27 MHz crystal oscillator input
OSCGND
4
3
15
0 V crystal oscillator ground
V
SS1
5
4 and 5
16
0 V ground
REF+
6
6
18
positive reference voltage for ADC; this pin should be connected
to ground via a 100 nF capacitor
BLACK
7
8
19
video black level storage input/output; this pin should be
connected to ground via a 100 nF capacitor
CVBS
8
9
20
composite video input; a positive-going 1 V (peak-to-peak) input
is required, connected via a 100 nF capacitor
IREF
9
10
21
reference current input, connected to ground via a 27 k
resistor
V
DD2
10
11
22
+5 V supply 2
POL
11
12
23
STTV/LFB/FFB polarity selection input
STTV/LFB
12
13
24
sync to TV output line flyback input; function controlled by an
internal register bit (scan sync mode)
VCR/FFB
13
14
27
PLL time constant switch/field input; function controlled by an
internal register bit (scan sync mode)
V
SS2
14
15
28
0 V ground; connected to V
SS1
for normal operation
R
15
16
30
dot rate character output of the RED colour information
G
16
17
32
dot rate character output of the GREEN colour information
B
17
18
33
dot rate character output of the BLUE colour information
RGBREF
18
19
34
input DC voltage to define the output high level on the RGB pins
BLAN
19
20
35
dot rate fast blanking output
COR
20
21
36
programmable output to provide contrast reduction of the TV
picture for mixed text and picture displays or when viewing
newsflash/subtitle pages;
open-drain output
ODD/EVEN
(or DV)
21
22
37
in ODD/EVEN mode a 25 Hz output synchronized with the CVBS
input field sync pulses to produce a non-interlaced display by
adjustment of the vertical deflection currents; in DV mode a VPT
data valid signal is used to indicate reception of error-free VPS or
8/30 format 2 data
Y
22
23
38
dot rate character output of teletext foreground colour information;
open-drain output
SCL
23
24
39
serial clock input for I
2
C-bus; it can still be driven HIGH during
power-down of the device
SDA
24
25
40
serial data port for the I
2
C-bus, open-drain output; it can still be
driven HIGH during power-down of the device
V
SS3
25
26
44
0 V ground
1996 Nov 04
5
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
i.c.
26 to 35,
38 to 43,
45 to 48
27 to 32,
35 to 38,
41 to 46,
48 to 51
1 to 3,
5 to 8,
45 to 53,
55, 61,
63 to 64
internally connected; normally open-circuit
CLK EN
36
39
56
clock enable input to enable the clock output (CLP O/P pin 37);
internal pull-down normally disables clock
CLK O/P
37
40
59
13.5 MHz clock output to drive an external microcontroller
LINE 23
44
47
4
output for indication of Line 23 for use with external circuitry
n.c.
-
7, 33, 34
9, 10, 12,
17, 25, 26,
29, 31,
41 to 43,
54, 57, 58,
60, 62
not connected; normally open-circuit
SYMBOL
PIN
DESCRIPTION
SOT240-1 SOT247-1 SOT319-2
1996 Nov 04
6
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Fig.3 Pin configuration; SOT247-1 (SDIP52).
handbook, halfpage
1
2
3
4
5
6
7
8
9
10
11
12
13
40
39
38
37
36
35
34
33
32
31
30
29
28
27
14
15
16
17
18
19
20
22
23
24
25
26
21
42
41
43
44
45
46
47
48
49
50
51
52
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
CLK O/P
LINE 23
CLK EN
i.c.
i.c.
n.c.
n.c.
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
V SS3
OSCOUT
OSCIN
OSCGND
REF+
n.c.
BLACK
CVBS
IREF
V DD2
POL
V SS1
V SS1
STTV/LFB
VCR/FFB
V SS2
R
G
B
RGBREF
BLAN
COR
ODD/EVEN
(or DV)
Y
SCL
SDA
i.c.
i.c.
i.c.
VDD1
MBD785
SAA5281
Fig.2 Pin configuration; SOT240-1 (DIP48).
handbook, halfpage
1
2
3
4
5
6
7
8
9
10
11
12
13
40
39
38
37
36
35
34
33
32
31
30
29
28
27
14
15
16
17
18
19
20
22
23
24
26
25
21
42
41
43
44
45
46
47
48
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
CLK O/P
LINE 23
CLK EN
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
V SS3
SAA5281
OSCOUT
OSCIN
OSCGND
REF+
BLACK
CVBS
IREF
V DD2
POL
V SS1
STTV/LFB
VCR/FFB
V SS2
R
G
B
RGBREF
BLAN
COR
Y
SCL
SDA
ODD/EVEN
(or DV)
VDD1
MBD784
1996 Nov 04
7
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Fig.4 Pin configuration; SOT319-2 (QFP64).
handbook, full pagewidth
SAA5281
MBH665
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
VDD1
VSS1
OSCOUT
i.c.
i.c.
i.c.
LINE 23
i.c.
i.c.
i.c.
i.c.
n.c.
n.c.
n.c.
n.c.
OSCIN
OSCGND
BLACK
B
RGBREF
BLAN
COR
Y
SCL
SDA
n.c.
n.c.
n.c.
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
CLK EN
CLK O/P
i.c.
n.c.
n.c.
n.c.
n.c.
n.c.
i.c.
i.c.
VSS3
CVBS
IREF
POL
n.c.
n.c.
n.c.
n.c.
STTV/LFB
R
G
VCR/FFB
V
DD2
V
SS2
REF
+
ODD/EVEN
(or DV)
1996 Nov 04
8
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
QUALITY AND RELIABILITY
This device will meet Philips Semiconductors General Quality Specification for Business group
"Consumer Integrated
Circuits SNW-FQ-611-Part E". The principal requirements are shown in Tables 1 to 4.
Group A
Table 1
Acceptance tests per lot
Group B
Table 2
Processability tests (by package family)
Group C
Table 3
Reliability tests (by process family)
Table 4
Reliability tests (by device type)
Notes to Tables 1 to 4
1. ppm = fraction of defective devices, in parts per million.
LTPD = Lot Tolerance Percent Defective.
FPM = fraction of devices failing at test condition, in Failures Per Million.
FITS = Failures In Time Standard.
TEST
REQUIREMENTS
(1)
Mechanical
cumulative target:
<
100 ppm
Electrical
cumulative target:
<
100 ppm
TEST
REQUIREMENTS
(1)
Solderability
<
7% LTPD
Mechanical
<
15% LTPD
Solder heat resistance
<
15% LTPD
TEST
CONDITIONS
REQUIREMENTS
(1)
Operational life
168 hours at T
j
= 150
C
<
1500 FPM; equivalent to
<
100 FITS at T
j
= 70
C
Humidity life
temperature, humidity, bias
1000 hours, 85
C, 85% RH
(or equivalent test)
<
2000 FPM
Temperature cycling performance
T
stg(min)
to T
stg(max)
<
2000 FPM
TEST
CONDITIONS
REQUIREMENTS
(1)
ESD and latch-up
ESD Human body model
2000 V, 100 pF, 1.5 k
<
15% LTPD
ESD Machine model
200 V, 200 pF, 0
<
15% LTPD
latch-up 100 mA, 1.5
V
DD
(absolute maximum)
<
15% LTPD
1996 Nov 04
9
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
LIMITING VALUES
In accordance with Absolute Maximum Rating System (IEC 134).
CHARACTERISTICS
V
DD
= 5 V
10%; T
amb
=
-
20 to +70
C; pin numbers refer DIP48 package; unless otherwise specified.
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
V
DD
supply voltage (all supplies)
-
0.3
+6.5
V
V
I
input voltage (any input)
-
0.3
V
DD
+ 0.5
V
V
O
output voltage (any output)
-
0.3
V
DD
+ 0.5
V
I
O
output current (each output)
-
10
mA
I
IOK
DC input or output diode current
-
20
mA
T
amb
operating ambient temperature
-
20
+70
C
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
DD
supply voltage
4.5
5.0
5.5
V
I
DDtot
total supply current
-
75
150
mA
Inputs
CVBS
V
sync
sync voltage amplitude
0.1
0.3
0.6
V
V
burst(p-p)
colour burst amplitude
(peak-to-peak value)
0.0
0.3
4.0
V
t
d(sync)
delay from CVBS to TCS
output from STTV buffer
(nominal video, average of
leading/trailing edge)
-
150
0
+150
ns
t
d(sync)
change in sync delay between
all black and all white video
input at nominal levels
0
-
25
ns
V
vid(p-p)
video input voltage amplitude
(peak-to-peak value)
0.7
1.0
1.4
V
V
dat(text)
teletext data voltage amplitude
0.29
0.46
0.71
V
f/f
display PLL capture range
7
-
-
%
Z
source
source impedance
-
-
250
V
I
input switching voltage level of
sync separator
1.7
2.0
2.3
V
Z
I
input impedance
2.5
5.0
-
k
C
I
input capacitance
-
-
10
pF
IREF
R
gnd
resistor to ground
-
27
-
k
V
i
input voltage
-
0.5V
DD
-
V
1996 Nov 04
10
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
POL
V
IL
LOW level input voltage
-
0.3
-
+0.8
V
V
IH
HIGH level input voltage
2.0
-
V
DD
+ 0.5
V
I
LI
input leakage current
V
I
= 0 to V
DD
-
10
-
+10
A
C
I
input capacitance
-
-
10
pF
LFB
V
IL
LOW level input voltage
-
0.3
-
tbf
V
V
IH
HIGH level input voltage
tbf
-
V
DD
+ 0.5
V
I
LI
input leakage current
V
I
= 0 to V
DD
-
10
-
+10
A
I
Imax
maximum input current
note 1
-
1
-
+1
mA
t
dLFB
delay between LFB front edge
and input video line sync
-
250
-
ns
VCR/FFB
V
IL
LOW level input voltage
-
0.3
-
+0.8
V
V
IH
HIGH level input voltage
2.0
-
V
DD
+ 0.5
V
I
LI
input leakage current
V
I
= 0 to V
DD
-
10
-
+10
A
I
Imax
maximum input current
note 1
-
1
-
+1
mA
RGBREF
V
IL
LOW level input voltage
-
0.3
-
V
DD
V
I
LI
input leakage current
V
I
= 0 to V
DD
-
10
-
+10
A
SCL
V
IL
LOW level input voltage
-
0.3
-
+1.5
V
V
IH
HIGH level input voltage
3.0
-
V
DD
+ 0.5
V
I
LI
input leakage current
V
I
= 0 to V
DD
-
10
-
+10
A
C
I
input capacitance
-
-
10
pF
f
clk
clock frequency
0
-
100
kHz
t
r
input rise time
between 10% and 90%
-
-
2
s
t
f
input fall time
between 90% and 10%
-
-
2
s
Inputs/outputs
C
RYSTAL OSCILLATOR
(OSCIN; OSCOUT)
V
osc(p-p)
oscillator voltage amplitude
(peak-to-peak value)
-
1.0
-
V
G
v
small signal voltage gain
-
1.0
-
G
m
mutual conductance
5.0
-
-
mS
C
I
input capacitance
-
-
10
pF
C
fb
feedback capacitance
-
1
-
pF
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
1996 Nov 04
11
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
BLACK
C
black
storage capacitor to ground
-
100
-
nF
V
black
black level voltage for nominal
sync amplitude
1.8
2.15
2.5
V
I
LI
input leakage current
V
I
= 0 to V
DD
-
10
-
+10
A
SDA (
OPEN
-
DRAIN INPUT
/
OUTPUT
)
V
IL
LOW level input voltage
-
0.3
-
+1.5
V
V
IH
HIGH level input voltage
3.0
-
V
DD
+ 0.5
V
V
OL
LOW level output voltage
I
OL
= 3 mA
0
-
0.5
V
I
LI
input leakage current
V
I
= 0 to V
DD
-
10
-
+10
A
C
I
input capacitance
-
-
10
pF
C
L
load capacitance
-
-
400
pF
t
r
input rise time
between 10% and 90%
-
-
2
s
t
f
input fall time
between 90% and 10%
-
-
2
s
t
f
output fall time
between 3 V and 1 V
-
-
200
ns
Outputs
STTV
G
sttv
gain of STTV relative to video
input
0.9
1.0
1.1
V
tcs
TCS voltage amplitude
0.2
0.3
0.45
V
V
tcs
DC shift between TCS output
and nominal video output
-
-
0.15
V
I
O
output drive current
-
-
3.0
mA
C
L
load capacitance
-
-
100
pF
R, G
AND
B
V
OL
LOW level output voltage
I
OL
= 2 mA
0
-
0.2
V
V
OH
HIGH level output voltage
I
OH
=
-
1.6 mA;
V
RGBREF
<
V
DD
-
2 V;
note 2
V
RGBREF
-
0.25
V
RGBREF
V
RGBREF
+ 0.5
V
|
Z
o
|
output impedance
-
-
200
C
L
load capacitance
-
-
50
pF
t
r
output rise time
between 10% and 90%
-
-
20
ns
t
f
output fall time
between 90% and 10%
-
-
20
ns
BLAN
V
OL
LOW level output voltage
I
OL
= 1.6 mA
0
-
0.4
V
V
OH
HIGH level output voltage
I
OH
=
-
0.2 mA
1.1
-
-
V
I
OH
= 0 mA
-
-
2.8
V
C
L
load capacitance
-
-
50
pF
t
r
output rise time
between 10% and 90%
-
-
20
ns
t
f
output fall time
between 90% and 10%
-
-
20
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
1996 Nov 04
12
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Notes
1. This current is the maximum allowed into the inputs when line and field flyback signals are connected to these inputs.
Series current limiting resistors must be used to limit the input currents to
1 mA.
2. Voltage level V
OH
for R, G and B outputs is taken to be the mean value during the output HIGH time. If higher R, G
and B voltage V
OH
levels are required RGBREF voltage level may be raised and a pull-up resistor used at each of
these pins provided current specification (I
OL
) is not exceeded.
ODD/EVEN
OR
DV
V
OL
LOW level output voltage
I
OL
= 1.6 mA
0
-
0.4
V
V
OH
HIGH level output voltage
I
OH
=
-
1.6 mA
V
DD
-
0.4
-
V
DD
V
C
L
load capacitance
-
-
120
pF
t
r
output rise time
between 0.6 V and
2.2 V
-
-
50
ns
t
f
output fall time
between 0.6 V and
2.2 V
-
-
50
ns
COR
AND
Y (
OPEN
-
DRAIN OUTPUTS
)
V
OH
HIGH level pull-up output
voltage
-
-
V
DD
V
V
OL
LOW level output voltage
I
OL
= 2 mA
0
-
0.4
V
I
OL
= 5 mA
0
-
1.0
V
C
L
load capacitance
-
-
25
pF
t
f
output fall time
load resistor of 1.2 k
to V
DD
; measured
between V
DD
-
0.5 V
and 1.5 V
-
-
50
ns
I
LO
output leakage current
V
I
= 0 to V
DD
-
10
-
+10
A
t
skew
skew delay between display
outputs R, G, B, COR, Y and
BLAN
-
-
20
ns
I
2
C-bus timing (see Fig.5)
t
LOW
SCL clock LOW time
4.0
-
-
s
t
HIGH
SCL clock HIGH time
4.0
-
-
s
t
SU;DAT
data set-up time
250
-
-
ns
t
HD;DAT
data hold time
170
-
-
ns
t
SU;STO
set-up time from clock HIGH
to STOP
4.0
-
-
s
t
BUF
START set-up time following a
STOP
4.0
-
-
s
t
HD;STA
START hold time
4.0
-
-
s
t
SU;STA
START set-up time following a
clock LOW-to-HIGH transition
4.0
-
-
s
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
1996 Nov 04
13
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Fig.5 I
2
C-bus timing.
handbook, full pagewidth
MBC764
t BUF
t f
t HIGH
t SU;DAT
t SU;STO
t HD;DAT
t SU;STA
t r
t LOW
t HD;STA
SDA
SCL
SDA
TIMING CHAIN
Fig.6 Display output timing (a) line rate (b) field rate.
(1) Also BLAN in character and box blanking.
handbook, full pagewidth
0
4.66
0
0
LSP
MLA662 - 1
(TCS)
16.67
41
R, G, B, Y
(1)
R, G, B, Y
(1)
display period
display period
lines 42 to 291 inclusive (and 355 to 604 inclusive interlaced)
291
312
line numbers
56.67
s
40
s
64
s
1996 Nov 04
14
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
handbook, full pagewidth
0
4.66
0
2.33
0
32
34.33
27.33
32
64
s
59.33
621
(308)
622
(309)
623
(310)
624
(311)
625
(312)
1
2
3
456
7
308
309
310
311
312
1
2
3
4
5
6
7
309
310
311
312
313
314 (1)
315 (2)
316 (3)
317 (4)
318 (5)
319 (6)
320 (7)
LSP
(Line Sync Pulse)
EP
(Equalizing Pulse)
BP
(Broad Pulse)
TCS interlaced
TCS interlaced
TCS non-interlaced
MLA037 - 2
64
s
64
s
LSP,
EP and
BP are combined to give
TCS as shown. All timings are measured from falling edge of LSP.
Line numbers placed in the middle of the line.
Equivalent count numbers in brackets.
Fig.7 Composite sync waveforms.
1996 Nov 04
15
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Fig.8
ODD/EVEN timing.
handbook, full pagewidth
621
622
623
624
(311)
(310)
(308)
(309)
625
(312)
1
2
3
4
5
6
309
310
312
313
314 (1)
315 (2)
316 (3)
317 (4)
318 (5)
319 (6)
311
2
s
2
s
ODD / EVEN output
(normal sync mode
when VCS to SCS
mode active)
ODD / EVEN output
(normal sync mode)
TCS interlaced
MLA416 - 2
48
s
30
s
16
s
(1)
7
ODD / EVEN output
(slave sync mode)
320 (7)
SECOND FIELD START (ODD)
FIRST FIELD START (EVEN)
ODD / EVEN output
(normal sync mode
when VCS to SCS
mode active)
ODD / EVEN output
(normal sync mode)
TCS interlaced
ODD / EVEN output
(slave sync mode)
30
s
(1)
Line numbers placed in the middle of the line.
Equivalent count numbers in brackets.
(1)
Or 62
s if Register
1 D2.D1.D0 equals 1
1
1.
1996 Nov 04
16
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
ON-CHIP MEMORY
Page memory organization
The organization of the page memory is illustrated by Fig.9. The IVT1.8* provides an additional row as compared with
first generation decoders; this brings the display format up to 40 characters by 25 rows. Rows 0 to 23 form the teletext
page; row 24 is the extra row available for software generated status messages and FLOF/FASTEXT prompt
information.
Fig.9 Basic page memory organization.
handbook, full pagewidth
MBD789
7 characters
for status
8 characters
always rolling
(time)
fixed character
written by IVT hardware:
alphanumerics white for normal;
alphanumerics green when looking
for display page
7
1
8
24
24 characters from page header
rolling when display page looked for
5
to
20
0
1
2
3
4
ROW
21
22
23
24
25
MAIN PAGE DISPLAY AREA
PACKET X / 22
PACKET X / 23
PACKET X / 24 STORED HERE IF R0D7 = 1
10
14
10 bytes for
received
page information
if enabled 14 bytes reserved in
chapter 5 for VPS data
R
EMARK TO
Fig.9
Row 0
Row 0 is for the page header. The first seven characters
(0 to 6) are free for status messages. Character 8 is an
alphanumeric white or green control character, written
automatically by IVT1.8* to give a green rolling header
when a page is being looked for. The last eight characters
are for rolling time.
Row 25
The first 10 bytes of row 25 contain control data relating to
the received page as shown in Table 5. The remaining
14 bytes are free for use by the microcomputer.
1996 Nov 04
17
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 5
Row 25 received control data format
ROW 25
D0
PU0
PT0
MU0
MT0
HU0
HT0
C7
C11
MAG0
0
D1
PU1
PT1
MU1
MT1
HU1
HT1
C8
C12
MAG1
0
D2
PU2
PT2
MU2
MT2
HU2
C5
C9
C13
MAG2
0
D3
PU3
PT3
MU3
C4
HU3
C6
C10
C14
0
0
D4
HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER FOUND
0
D5
0
0
0
0
0
0
0
0
0
PBLF
D6
0
0
0
0
0
0
0
0
0
0
D7
0
0
0
0
0
0
0
0
0
0
Column
0
1
2
3
4
5
6
7
8
9
Table 6
Page number and sub-code for Table 5
BIT NAME
DESCRIPTION
Page number
MAG
magazine
PU
page units
PT
page tens
PBLF
page being looked for
FOUND
LOW for page has been found
HAM.ER
Hamming error in corresponding byte
Page sub-code
MU
minutes units
MT
minutes tens
HU
hours units
HT
hours tens
C4 to C14
transmitted control bits
1996 Nov 04
18
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Extension packet memory organization
When in normal extension packet enabled mode the rows of information are organized as illustrated in Fig.10.
Row 23 of the extension page, as shown in Fig.10, contains packet 8/30. Packet 8/30 is mapped into the IVT1.8* memory
as follows:
8 / 30 / 0 and 8 / 30 / 1 to Chapter 4 Row 23
8 / 30 / 2 and 8 / 30 / 3 to Chapter 5 Row 23
8 / 30 / 4 to 8 / 30 / 15 to Chapter 6 Row 23.
Fig.10 Organization of the extension memory.
(1) Row 25 reserved for VPS data in Chapter 5.
handbook, full pagewidth
PACKETS X/26/0 to X/26/14
PACKET X/28/2
PACKETS X/27/0 to X/27/1
PACKETS X/27/4 to X/27/5
PACKET X/24 IF R0D7 = 0
PACKET X/25
PACKET X/28/0
PACKET 8/30
PACKET X/28/1
RESERVED
ROW
0
to
14
15
16
17
18
19
20
21
22
23
24
25
MBD791
(1)
1996 Nov 04
19
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
E
NHANCED MODE
In enhanced mode, the number of extension packets captured is reduced to the minimum required for FASTEXT
operation. The first seven chapters can then be used for storage, using the system of pointers. The arrangement of
extension packets is shown in Fig.11.
When in enhanced mode and extension packets are disabled, normal 8-page mode is in operation, but the X/26 engine
is enabled (unlike normal 8-page mode).
Fig.11 Organization of the extension memory in enhanced mode.
handbook, halfpage
MBD788
PACKETS 8 / 30 / 0,1
PACKETS 8 / 30 / 2,3
PACKETS 8 / 30 / 4 to 15
17
16
18
ROW
not used
19 to 24
not used
not used
CHAPTER 6 PACKETS 27 / 0
CHAPTER 6 PACKET 24
14
13
15
12
CHAPTER 5 PACKETS 27 / 0
CHAPTER 5 PACKET 24
11
10
CHAPTER 4 PACKETS 27 / 0
CHAPTER 4 PACKET 24
9
8
CHAPTER 3 PACKETS 27 / 0
CHAPTER 3 PACKET 24
7
6
CHAPTER 2 PACKETS 27 / 0
CHAPTER 2 PACKET 24
5
4
CHAPTER 1 PACKETS 27 / 0
CHAPTER 1 PACKET 24
3
2
CHAPTER 0 PACKETS 27 / 0
CHAPTER 0 PACKET 24
1
0
1996 Nov 04
20
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
VPT data memory organization
To simplify the software for dual-standard VPT decoders,
the VPS data from line 16 is stored in row 25 of Chapter 5
of the page memory, and is aligned to match the
packet 8/30 format 2 data as far as possible. The 8/30
format 2 packet is Hamming coded and by setting the
appropriate register control bit the data is stored after
hardware Hamming correction. There are 4 data bits
stored in each column address of memory with an
additional Hamming error bit. The data equivalent to the
VPS signal is found in columns 12 to 19.
Although the VPS data is not Hamming protected, it is
stored with 4 data bits per column address in the same
way with an additional biphase error bit. The extra space
in Row 25 is allocated to two more Line 16 words.
They are Word 15 (reserved) and Word 4 (Program
Source Identification, ASCII sequential) which may be
useful for future applications. Details of the memory
organization are shown in Fig.12.
The stored data can be read from memory via the I
2
C-bus
in the normal way. Multiple reception/majority error
correction of the VPS data is the responsibility of the
control software, the device simply stores the data as
transmitted after biphase decoding.
As both VPS and 8/30/2 signals are stored in separate
memory locations, it is possible to deal with future
situations where both System A and System B
transmissions may be present on the same TV channel,
the defaults and level of service chosen by the control
software.
Fig.12 Detailed memory organization.
handbook, full pagewidth
MBD787
2
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
B11
B12
B13
B14
B15
b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25
initial page
D
received page information
column
8/30/2
VPS
22
21
23
24
25
26
27
28
29
30
11
12
13
14
15
16
17
18
19
column
8/30/2
VPS
0
20
status display
B4
B5
1996 Nov 04
21
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Register maps
IVT1.8* mode registers R0
to
R13 are shown in Table
7. R0
to
R10, R12 and R13 are WRITE only; R11 is READ/WRITE, R11B is read only.
Register map (R3), for page requests, is shown in detail in Table
11.
T
able 7
Register map (notes
1
t
o
4
)
REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
NAME
No.
Advanced control
0
X/24 POS
FREE RUN
PLL
AUTO
ODD/EVEN
DISABLE
HDR ROLL
CBB SLA
VE
SYNC
DISABLE
ODD/EVEN
VCR MODE
R1
1/R1
1B
SELECT
Mode
1
VCS T
O
SCS
7 + P/ 8-BIT
ACQ
ON/OFF
EXT PKT
ENABLE
DEW/ FULL
FIELD
TCS ON
T1
T0
Page request
address
2
HAM CHECK
27, 8/30
BANK
SELECT A2
ACQ CCT A1
ACQ CCT A0
0
SC2
SC1
SC0
Page request data
3
---
PRD4
PRD3
PRD2
PRD1
PRD0
Display chapter
4
---
-
FREEZE
HEADER
ONL
Y
A2
A1
A0
Display control
(normal)
5
BKGND OUT
BKGND IN
COR OUT
COR IN
TEXT OUT
TEXT IN
PON OUT
PON IN
Display control
(newsflash /subtitle)
6
BKGND OUT
BKGND IN
COR OUT
COR IN
TEXT OUT
TEXT IN
PON OUT
PON IN
Display mode
7
STATUS
BTM/T
OP
CURSOR ON
CONCEAL/
REVEAL ON
T
OP/BTM
HALF
SINGLE/
DOUBLE
HEIGHT
BOX ON 24
BOX ON 1
to 23
BOX ON 0
Active chapter
8
---
VPS ENABLE
CLEAR
MEM
A2
A1
A0
Cursor row
9
---
R4
R3
R2
R1
R0
Cursor column
10
--
C5
C4
C3
C2
C1
C0
Cursor data
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Device status
1
1
B
625/525
SYNC
ROM VER R4
ROM VER R3
ROM
VER
R2
ROM VER
R1
ROM
VER R0
TEXT
SIGNAL
QUALITY
VCS
SIGNAL
QUALITY
Advanced control 2A
12
H3
H2
H1
H0
S3
S2
S1
S0
Advanced control 2B
13
ENHANC
MODE
CURSOR
FREEZE/
DEVICE
IDENT
MESHING
ENABLE
VPS ENABLE
POINTS
ENABLE
HAM
CHECK
2
4:1
8
DISABLE
PKT X/26
AUT
O
DISPLA
Y
PKT X/24
1996 Nov 04
22
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Notes to Table 7
1. The dash (
-
) indicates these bits are inactive and must be written to logic 0 for future compatibility.
2. Certain registers are auto-incremented following an I
2
C-bus transmission byte. These are Register R0 to R3,
R4 to R7 and R8 to R12 or R13.
3. All bits in Registers R0 to R13 are cleared to logic 0 on power-up except bits D0 and D1 of Registers R1, R5 and R6
which are set to logic 1.
4. All memory is cleared to space (00100000) on power-up, except Row 0 Column 7 Chapter 0, which is alpha white
(00000111) as the acquisition circuit is enabled but all pages are on hold.
Table 8
Register description
REGISTER BIT D0 TO D7
FUNCTION
R0 AVANCED CONTROL - auto-increments to Register 1
R11/R11B SELECT
Selects reading of R11 if LOW or R11B if HIGH.
VCR MODE
If logic 1 selects short time constant mode of PLL.
DISABLE ODD/EVEN
Forces ODD/EVEN output LOW when logic 1 (see Table 9).
CBB SLAVE SYNC
When set will modify internal slave sync timing to allow connection to sandcastle of
Philips one-chip TV IC (TDA8362).
DISABLE HDR ROLL
Stops the display update of rolling time and green rolling header during page
requests when logic 1. Time updates on page reception only.
AUTO ODD/EVEN
If logic 1 then ODD/EVEN output only active when no TV picture displayed
(see Table 9).
FREE RUN PLL
Will force the display PLL to free run at 6 MHz when logic 1.
X/24 POS
Automatic display of FASTEXT prompt row when logic 1. Will also cause Row 24
data transmitted by packet 26 to be written to display, rather than extension
memory.
R1 MODE - auto-increments to Register 2
T0, T1
Interlace/non-interlace 312/313 line control (see Table 10).
TCS ON
Text composite sync or direct sync select (see Table 10 for FFB mode selection).
DEW/FULL FIELD
Field-flyback or full-channel mode.
EXT PKT ENABLE
Enables reception and storage of extension packets when logic 1.
ACQ ON/OFF
Acquisition circuits turned off when logic 1.
7 + P/8-BIT
7 bits with parity checking or 8-bit mode.
VCS TO SCS
Connects VCS from video sync separator to display field sync detector to enable
stable display of 60 Hz status messages when logic 1.
R2 PAGE REQUEST ADDRESS - auto-increments to Register 3
SC0 to SC2
Start column for page request data (see Table 11).
0
Must be logic 0 for normal operation.
ACQ CCT A0, A1
Selects one of four acquisition circuits.
BANK SELECT A2
Selects bank of four pages being addressed for acquisition.
HAM CHECK 27, 8/30
8/4 Hamming check packet 27 and 8/30 data.
R3 PAGE REQUEST DATA - does not auto-increment
PRD0 to PRD4
See Table 11.
1996 Nov 04
23
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
R4 DISPLAY CHAPTER - auto-increments to Register 5
A0 to A2
Selects one of 8 display chapters.
FREEZE HEADER ONLY
Freezes the rolling header, but (unlike R0D4) allows the time to roll.
R5 NORMAL DISPLAY CONTROL - auto-increments to Register 6
R6 NEWSFLASH/SUBTITLE DISPLAY CONTROL - auto-increments to Register 7; note 1
PON
Picture on.
TEXT
Text on.
COR
Contrast reduction on.
BKGND
Background colour on.
R7 DISPLAY MODE - does not auto-increment
BOX ON 0
Boxing function allowed on Row 0.
BOX ON 1 to 23
Boxing function allowed on Rows1 to 23.
BOX ON 24
Boxing function allowed on Row 24.
SINGLE/DOUBLE HEIGHT
To display double height text.
TOP/BTM HALF
To select bottom half of page when DOUBLE HEIGHT is logic 1.
CONCEAL/REVEAL ON
To reveal concealed text.
CURSOR ON
To display cursor.
STATUS BTM/TOP
Row 25 displayed above or below the main text.
R8 ACTIVE CHAPTER - auto-increments to Register 9
A0 to A2
Active chapter for data written to or read from memory via the I
2
C-bus.
CLEAR MEM
When set to logic 1, clears the display memory. This bit is automatically reset.
VPS ENABLE
VPS acquisition enabled when logic 1.
R9 CURSOR ROW - auto-increments to Register 10
R0 to R4
Active row for data written to or read from memory via the I
2
C-bus.
R10 CURSOR COLUMN - auto-increments to Register 11 or 11B
C0 to C5
Active column for data written to or read from memory via the I
2
C-bus.
R11 CURSOR DATA - does not auto-increment
D0 to D7
Data read from/written to memory via I
2
C-bus, at location pointed to by R9 and
R10. This location automatically increments each time R11 is accessed.
R11B DEVICE STATUS - does not auto-increment
VCS SIGNAL QUALITY
Indicates that the video signal quality is good and PLL is phase-locked to input
video when logic 1.
TEXT SIGNAL QUALITY
If a good teletext signal is being received then logic 1.
ROM VER R0 to R4
Indicated language/ROM variant. For Western European is logic 0. R3 and R4 are
set HIGH if R13 D6 is logic 1.
625/525 SYNC
If the input video is a 525 line signal then logic 1.
R12 ADVANCED CONTROL 2A - does not auto-increment
S0 to S3, H0 to H3
Each acquisition channel can be programmed to process its page in one of four
ways as shown in Table 12.
REGISTER BIT D0 TO D7
FUNCTION
1996 Nov 04
24
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Note
1. These functions have IN and OUT referring to inside and outside the boxing function respectively.
Table 9
ODD/EVEN selection
Table 10 Interlace/non-interlace 312/313 line control and ODD/EVEN field detection option
Notes
1. X = don't care.
2. Reverts to interlaced mode if a newsflash or subtitle is being displayed.
R13 ADVANCED CONTROL 2B - does not auto-increment
AUTO DISPLAY PKT X/24
Status row will show the contents of the row of the extension memory (packet 24)
when logic 1.
DISABLE PKT X/26
Output taken from processing engine written to the display memory when logic 0.
Operates independent of the acquisition.
HAM CHECK 24 : 18
When logic 1 all packet 26 data is stored in extension memory unchecked.
POINTS ENABLE
Enable for acquisition pointers when logic 1.
VPS ENABLE
VPS acquisition enabled when logic 1.
MESHING ENABLE
Enables meshing display function in box mode.
CURSOR FREEZE/
DEVICE IDENT
When logic 1, cursor position not updated even if active row and column change.
This bit will also cause R3 and R4 of the ROM code in Register R11B to be set
HIGH. This allows software to identify the device as an IVT1.8*. An internal `1.8
mode' flag is also set, which enables the operation of R0D4, R4D4 and the subtitle
bit in R3.
ENHANC MODE
When logic 1, extension packet data is mapped into the last chapter. Only packet
24, 27/0 and 8/30 are stored. Chapters 0 to 6 can then be used for page storage. If
extension packets are not enabled, 8 pages are stored as normal, but X/26 engine
is enabled.
AUTO
ODD/EVEN
DISABLE
ODD/EVEN
RESULT
0
0
ODD/EVEN output continuous
0
1
ODD/EVEN statically LOW
1
1
ODD/EVEN active only when no TV picture displayed
1
1
DV output to indicate reception of error-free 8/30/format 2 packet or VPS line
TCS ON
FFB MODE
(1)
T1
T0
RESULT
X
0
0
interlaced 312.5/312.5 lines
X
0
1
non-interlaced 312/313 lines (note 2)
X
1
0
non-interlaced 312/313 lines (note 2)
0
1
1
SCS (scan composite sync) mode: FFB leading edge in first broad pulse of field
1
1
1
SCS (scan composite sync) mode: FFB leading edge in second broad pulse of field
REGISTER BIT D0 TO D7
FUNCTION
1996 Nov 04
25
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 11 Register map for page requests (R3); notes 1 to 6
Notes
1. Abbreviations are as given in Table 6 except for DO CARE bits and CH = chapter address for acquisition chapter.
2. When the DO CARE bit is set to logic 1 this means the corresponding digit is to be taken into account for page
requests. If the DO CARE bit is set to logic 0 the digit is ignored. This allows, for example, normal or timed page
selection.
3. If HOLD is set LOW, the page is held and not updated.
4. Columns auto-increment on successive I
2
C-bus transmission bytes.
5. The SUBTITLE bit is only present when the device is in `1.8 mode' (i.e. R13D6 has been set HIGH).
6. X = don't care.
Table 12 Acquisition channel programming
Note
1. These register bits operate in conjunction with 7 + P/ 8-BIT (Register 1, Bit D6) which will over-ride the choice of data
checker if set, setting all channels to 8-bit only. If this bit is not set H0 to H3 and S0 to S3 will determine the data
checking (default to 7-bit + parity).
START
COLUMN
PRD4
PRD3
PRD2
PRD1
PRD0
0
DO CARE
Magazine
HOLD
MAG2
MAG1
MAG0
1
DO CARE
Page tens
PT3
PT2
PT1
PT0
2
DO CARE
Page units
PU3
PU2
PU1
PU0
3
DO CARE
Hours tens
SUBTITLE
X
HT1
HT0
4
DO CARE
Hours units
HU3
HU2
HU1
HU0
5
DO CARE
Minutes tens
X
MT2
MT1
MT0
6
DO CARE
Minutes units
MU3
MU2
MU1
MU0
7
X
X
CH2
CH1
CH0
H0 to H3
(1)
S0 to S3
(1)
CHECKING ALGORITHM FOR ACQUISITION CHANNEL X
0
0
7-bit + parity for whole page
0
1
8-bit for whole page
1
0
8/4 Hamming check for whole page
1
1
mixed 8/4 Hamming (columns 0 to 7, 20 to 27) and 7-bit + parity
(columns 8 to 19, 28 to 39)
1996 Nov 04
26
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
CLOCK SYSTEMS
Crystal oscillator
The crystal is a conventional Colpitts 3-pin design
operating at 27 MHz. The oscillator is sinusoidal and
linear, with a controlled output amplitude. This reduces the
radiated and conducted level of the 27 MHz fundamental
frequency, and reduces the power dissipation in the quartz
crystal. It is capable of oscillating with both fundamental
and third overtone mode crystals. External components
should be used to suppress the fundamental output of the
third overtone as illustrated in Fig.13. The crystal
characteristics are given in Table 13.
Table 13 Crystal characteristics (see Fig.13)
SYMBOL
PARAMETER
TYP.
MAX.
UNIT
Crystal (27 MHz, 3rd overtone)
C1
series capacitance
1.7
-
pF
C0
parallel capacitance
5.2
-
pF
C
L
load capacitance
20
-
pF
R
r
resonance resistance
-
50
R1
series resistance
20
-
X
a
ageing
-
5
10
-
6
year
-
1
X
j
adjustment tolerance
-
25
10
-
6
X
d
drift
-
25
10
-
6
Fig.13 Crystal oscillator application diagram for SOT240-1; pins in parenthesis are for SOT247-1.
handbook, full pagewidth
3
2
SAA5281
MBD786
4
1
8.2 pF
CRYSTAL
OSCILLATOR
100 nF
15 pF
1 nF
3.3
H
3.3 k
(52)
(1)
(2)
(3)
OSCGND
OSCIN
OSCOUT
V
DD1
27 MHz
3rd
overtone
1996 Nov 04
27
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
CHARACTER SETS
The WST specification allows the selection of national
character sets via the page header transmission bits,
C12 to C14. The basic 96 character sets differ only in
13 national option characters as indicated in the
Tables 21, 22 and 23 with reference to their table position
in the basic character matrix illustrated in Table 20.
The IVT1.8* automatically decodes transmission bits
C12 to C14. Tables 14, 15 and 16 illustrate the character
matrixes.
Character bytes are listed as transmitted from b1 to b7.
Meshing
This is an alternative method of displaying teletext
subtitles, or similar boxed text superimposed on the TV
picture and operates by showing reduced contrast TV
pictures in place of the (black) background within the
boxed area. The Meshing effect is produced by toggling
the BLAN signal from IVT at pixel rate. By starting at the
same point each field, and toggling the start position each
line, a chequered pattern will result. This allows movement
to be seen behind the text information. The MESH
OFF/ON bit in Register 13 D5 controls this function.
Normally at zero, compatibility with IVT1.0 is maintained.
Fig.14 Character format.
handbook, full pagewidth
MLA663
alphanumerics and
graphics 'space'
character
0000010
alphanumerics
character
1011010
alphanumerics or
blast-through
alphanumerics
character
0001001
alphanumerics
character
1111111
contiguous
graphics character
1111111
separated
graphics character
1111111
separated
graphics character
0110111
contiguous
graphics character
0110111
background
colour
display
colour
=
=
1996 Nov 04
28
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 14 SAA5281P/E character data input decoding, West European languages; notes 1 to 9
For character version number (11000) see Register 11B.
handbook, full pagewidth
MBA429
normal
height
b
4
b
3
b
2
b
1
b
5
b6
b
7
b
8
0
1
2
2a
3
3a
4
5
6
6a
7
7a
8
9
12
13
14
15
column
r
o
w
B
I
T
S
0
0
0
0
0
0
0
1
0 or 1
0
1
0
0
0
1
1
0 or 1
0
1
1
0
0
1
1
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
0
0
1
1
1
14
1 1 1 0
SO
hold
graphics
15
1 1 1 1
SI
release
graphics
11
1 0 1 1
start box
ESC
12
1 1 0 0
black
back -
ground
13
1 1 0 1
double
height
new
back -
ground
10
1 0 1 0
end box
separated
graphics
9
1 0 0 1
steady
contiguous
graphics
8
1 0 0 0
flash
conceal
display
7
0 1 1 1
alpha -
numerics
white
graphics
white
6
0 1 1 0
alpha -
numerics
cyan
graphics
cyan
5
0 1 0 1
alpha -
numerics
magenta
graphics
magenta
4
0 1 0 0
alpha -
numerics
blue
graphics
blue
3
0 0 1 1
alpha -
numerics
yellow
graphics
yellow
2
0 0 1 0
alpha -
numerics
green
graphics
green
0
0 0 0 0
alpha -
numerics
black
graphics
black
1
0 0 0 1
alpha -
numerics
red
graphics
red
(2)
(2)
(2)
(2)
(1)
(2)
(2)
(1)
(2)
(1)
1996 Nov 04
29
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 15 SAA5281P/H character data input decoding, East European languages; notes 1 to 9
For character version number (11001) see Register 11B.
handbook, full pagewidth
MLA961
normal
height
b
4
b
3
b
2
b
1
b
5
b6
b
7
b
8
0
1
2
2a
3
3a
4
5
6
6a
7
7a
8
9
12
13
14
15
column
r
o
w
B
I
T
S
0
0
0
0
0
0
0
1
0 or 1
0
1
0
0
0
1
0
0 or 1
0
1
1
0
0
1
1
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
0
0
1
1
1
14
1 1 1 0
SO
hold
graphics
15
1 1 1 1
SI
release
graphics
11
1 0 1 1
start box
ESC
12
1 1 0 0
black
back -
ground
13
1 1 0 1
double
height
new
back -
ground
10
1 0 1 0
end box
separated
graphics
9
1 0 0 1
steady
contiguous
graphics
8
1 0 0 0
flash
conceal
display
7
0 1 1 1
alpha -
numerics
white
graphics
white
6
0 1 1 0
alpha -
numerics
cyan
graphics
cyan
5
0 1 0 1
alpha -
numerics
magenta
graphics
magenta
4
0 1 0 0
alpha -
numerics
blue
graphics
blue
3
0 0 1 1
alpha -
numerics
yellow
graphics
yellow
2
0 0 1 0
alpha -
numerics
green
graphics
green
0
0 0 0 0
alpha -
numerics
black
graphics
black
1
0 0 0 1
alpha -
numerics
red
graphics
red
(2)
(2)
(2)
(2)
(1)
(2)
(2)
(1)
(2)
(1)
1996 Nov 04
30
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 16 SAA5281P/T character data input decoding, West European and Turkish languages; notes 1 to 9
For character version number (11010) see Register 11B.
handbook, full pagewidth
MBA431
normal
height
b
4
b
3
b
2
b
1
b
5
b6
b
7
b
8
0
1
2
2a
3
3a
4
5
6
6a
7
7a
8
9
12
13
14
15
column
r
o
w
B
I
T
S
0
0
0
0
0
0
0
1
0 or 1
0
1
0
0
0
1
1
0 or 1
0
1
1
0
0
1
1
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
0
0
1
1
1
14
1 1 1 0
SO
hold
graphics
15
1 1 1 1
SI
release
graphics
11
1 0 1 1
start box
ESC
12
1 1 0 0
black
back -
ground
13
1 1 0 1
double
height
new
back -
ground
10
1 0 1 0
end box
separated
graphics
9
1 0 0 1
steady
contiguous
graphics
8
1 0 0 0
flash
conceal
display
7
0 1 1 1
alpha -
numerics
white
graphics
white
6
0 1 1 0
alpha -
numerics
cyan
graphics
cyan
5
0 1 0 1
alpha -
numerics
magenta
graphics
magenta
4
0 1 0 0
alpha -
numerics
blue
graphics
blue
3
0 0 1 1
alpha -
numerics
yellow
graphics
yellow
2
0 0 1 0
alpha -
numerics
green
graphics
green
0
0 0 0 0
alpha -
numerics
black
graphics
black
1
0 0 0 1
alpha -
numerics
red
graphics
red
(2)
(2)
(2)
(2)
(1)
(2)
(2)
(1)
(2)
(1)
1996 Nov 04
31
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 17 SAA5281P/R character data input decoding, Baltic and Cyrillic languages; notes 1 to 9
For character version number (00101) see Register 11B.
handbook, full pagewidth
normal
height
b
4
b
3
b
2
b
1
b
5
b6
b
7
b
8
0
1
2
2a
3
3a
4
5
6
6a
7
7a
8
9
12
13
14
15
column
r
o
w
B
I
T
S
0
0
0
0
0
0
0
1
0 or 1
0
1
0
0
0
1
1
0 or 1
0
1
1
0
0
1
1
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
0
0
1
1
1
14
1 1 1 0
SO
hold
graphics
15
1 1 1 1
SI
release
graphics
11
1 0 1 1
start box
TWIST
12
1 1 0 0
black
back -
ground
13
1 1 0 1
double
height
new
back -
ground
10
1 0 1 0
end box
separated
graphics
9
1 0 0 1
steady
contiguous
graphics
8
1 0 0 0
flash
conceal
display
7
0 1 1 1
alpha -
numerics
white
graphics
white
6
0 1 1 0
alpha -
numerics
cyan
graphics
cyan
5
0 1 0 1
alpha -
numerics
magenta
graphics
magenta
4
0 1 0 0
alpha -
numerics
blue
graphics
blue
3
0 0 1 1
alpha -
numerics
yellow
graphics
yellow
2
0 0 1 0
alpha -
numerics
green
graphics
green
0
0 0 0 0
alpha -
numerics
black
graphics
black
1
0 0 0 1
alpha -
numerics
red
graphics
red
MBA648 - 1
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
1996 Nov 04
32
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 18 SAA5281P/L character data input decoding, Arabic and Hebrew languages; notes 1 to 9
For character version number (00100) see Register 11B.
handbook, full pagewidth
MLA963 - 1
normal
height
b
4
b
3
b
2
b
1
b
5
b6
b
7
b
8
0
1
2
2a
3
3a
4
5
6
6a
7
7a
8
9
12
13
14
15
column
r
o
w
B
I
T
S
0
0
0
0
0
0
0
1
0 or 1
0
1
0
0
0
1
0
0 or 1
0
1
1
0
0
1
1
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
14
1 1 1 0
SO
hold
graphics
15
1 1 1 1
SI
release
graphics
11
1 0 1 1
start box
TWIST
12
1 1 0 0
black
back -
ground
13
1 1 0 1
double
height
new
back -
ground
10
1 0 1 0
end box
separated
graphics
9
1 0 0 1
steady
contiguous
graphics
8
1 0 0 0
flash
conceal
display
7
0 1 1 1
alpha -
numerics
white
graphics
white
6
0 1 1 0
alpha -
numerics
cyan
graphics
cyan
5
0 1 0 1
alpha -
numerics
magenta
graphics
magenta
4
0 1 0 0
alpha -
numerics
blue
graphics
blue
3
0 0 1 1
alpha -
numerics
yellow
graphics
yellow
2
0 0 1 0
alpha -
numerics
green
graphics
green
0
0 0 0 0
alpha -
numerics
black
graphics
black
1
0 0 0 1
alpha -
numerics
red
graphics
red
0
1
1
0
0 or 1
1
1
0
0
1
1
1
0 or 1
1
1
1
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
1996 Nov 04
33
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 19 SAA5281P/K character data input decoding, French and Arabic languages; notes 1 to 9
For character version number (00100) see Register 11B.
handbook, full pagewidth
MLA972 - 1
normal
height
b
4
b
3
b
2
b
1
b
5
b6
b
7
b
8
0
1
2
2a
3
3a
4
5
6
6a
7
7a
8
9
12
13
14
15
column
r
o
w
B
I
T
S
0
0
0
0
0
0
0
1
0 or 1
0
1
0
0
0
1
0
0 or 1
0
1
1
0
0
1
1
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
14
1 1 1 0
SO
hold
graphics
15
1 1 1 1
SI
release
graphics
11
1 0 1 1
start box
TWIST
12
1 1 0 0
black
back -
ground
13
1 1 0 1
double
height
new
back -
ground
10
1 0 1 0
end box
separated
graphics
9
1 0 0 1
steady
contiguous
graphics
8
1 0 0 0
flash
conceal
display
7
0 1 1 1
alpha -
numerics
white
graphics
white
6
0 1 1 0
alpha -
numerics
cyan
graphics
cyan
5
0 1 0 1
alpha -
numerics
magenta
graphics
magenta
4
0 1 0 0
alpha -
numerics
blue
graphics
blue
3
0 0 1 1
alpha -
numerics
yellow
graphics
yellow
2
0 0 1 0
alpha -
numerics
green
graphics
green
0
0 0 0 0
alpha -
numerics
black
graphics
black
1
0 0 0 1
alpha -
numerics
red
graphics
red
0
1
1
0
0 or 1
1
1
0
0
1
1
1
0 or 1
1
1
1
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
1996 Nov 04
34
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Notes to Tables 14, 15, 16, 17, 18 and 19
1. These control characters are reserved for compatibility with other data codes.
2. These control characters are presumed before each row begins.
3. Control characters shown in Columns 0 and 1 are normally displayed as spaces.
4. Characters may be referred to by column and row (for example 2/5 refers to %).
5. Black represents displayed colour. White represents background.
6. The SAA5281 national option characters are illustrated in Tables 21, 22 and 23.
7. Characters 8/6, 8/7, 9/5, 9/6 and 9/7 are special characters for combining with character 8/5 (E, H and T codes only).
Characters 5/12, 5/13, 5/14 and 5/15 are combined with 5/11 (S code only).
8. National option characters will be displayed according to the setting of control bits C12 to C14. These will be mapped
into the basic code table into positions shown in Tables 21, 22 and 23.
9. Columns 2a, 3a, 6a and 7a are displayed in graphics mode.
1996 Nov 04
35
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
T
able 20
SAA5281 basic character matrix; note
1
Note
1.
Where NC = national option character position.
full pagewidth
MLA630
2/1
2/0
2/8
3/0
3/8
4/0
4/8
5/0
5/8
7/8
6/8
7/0
NC
6/0
NC
2/9
3/1
3/9
4/1
4/9
5/1
5/9
6/1
6/9
7/1
7/9
2/2
2/10
3/2
3/10
4/2
4/10
5/2
5/10
6/2
6/10
7/2
7/10
2/11
3/3
3/11
4/3
4/11
5/3
6/3
6/11
7/3
2/12
3/4
3/12
4/4
4/12
5/4
6/4
6/12
7/4
2/5
2/13
3/5
3/13
4/5
4/13
5/5
6/5
6/13
7/5
2/6
2/14
3/6
3/14
4/6
4/14
5/6
6/6
7/6
2/7
2/15
3/7
3/15
4/7
4/15
5/7
6/7
6/15
7/7
7/15
2/3
NC
5/11
NC
5/12
NC
5/13
NC
5/14
NC
5/15
NC
7/11
NC
7/12
NC
7/13
NC
7/14
NC
2/4
NC
1996 Nov 04
36
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 21 SAA5281P/E national option character set
Table 22 SAA5281P/H national option character set
handbook, full pagewidth
MLB458
LANGUAGE
C12 C13 C14
PHCB
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
FRENCH
ITALIAN
SWEDISH
GERMAN
ENGLISH
2 / 3
2 / 4
4 / 0
5 / 11 5 / 12 5 / 13 5 / 14 5 / 15
6 / 0
7 / 11 7 / 12 7 / 13 7 / 14
CHARACTER POSITION (COLUMN / ROW)
SPANISH
1
0
1
(1)
(1) PHCB are the Page Header Control Bits. Other combinations default to English.
handbook, full pagewidth
MLA966
LANGUAGE
C12 C13 C14
PHCB
(1)
0
0
0
0
0
1
0
1
0
1
0
1
1
1
0
1
1
1
RUMANIAN
CZECHOSLOVAKIA
SERBO-CROAT
SWEDISH
GERMAN
POLISH
2 / 3
2 / 4
4 / 0
5 / 11 5 / 12 5 / 13 5 / 14 5 / 15
6 / 0
7 / 11 7 / 12 7 / 13 7 / 14
CHARACTER POSITION (COLUMN / ROW)
(1) PHCB are the Page Header Control Bits. Other combinations default to German. Only the above characters change with the PHCB. All other
characters in the basic set are shown in Table 20.
1996 Nov 04
37
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 23 SAA5281P/T national option character set
andbook, full pagewidth
MBA430
LANGUAGE
C12 C13 C14
PHCB
(1)
0
0
0
0
0
1
1
1
0
0
1
1
1
0
0
1
0
1
SPANISH
FRENCH
ITALIAN
TURKISH
GERMAN
ENGLISH
2 / 3
2 / 4
4 / 0
5 / 11 5 / 12 5 / 13 5 / 14 5 / 15
6 / 0
7 / 11 7 / 12 7 / 13 7 / 14
CHARACTER POSITION (COLUMN / ROW)
(1) PHCB are the Page Header Control Bits. Other combinations default to English. Only the above characters change with the PHCB. All other
characters in the basic set are shown in Table 20.
1996 Nov 04
38
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 24 SAA5281P/R national option character set
(1) PHCB are the Page Header Control Bits. Other combinations default to Estonian.
handbook, full pagewidth
LANGUAGE
C12 C13 C14
PHCB
(1)
0
1
0
0
1
1
1
0
0
RUSSIAN
LETTISH /
LITHUANIAN
ESTONIAN
2 / 3
2 / 4
4 / 0
5 / 11 5 / 12 5 / 13 5 / 14 5 / 15
6 / 0
7 / 11 7 / 12 7 / 13 7 / 14
CHARACTER POSITION (COLUMN / ROW)
MEA597
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1996 Nov 04
39
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 25 SAA5281P/K national option character set
(1) PHCB are the Page Header Control Bits. Other combinations default to French.
handbook, full pagewidth
MLA968 - 1
LANGUAGE
(C12, C13, C14)
PHCB
(1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
2
3
4
5
6
7
2
3
4
5
6
7
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ARABIC
FRENCH
1 0 0
1 1 1
1996 Nov 04
40
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 26 SAA5281P/L national option character set
(1) PHCB are the Page Header Control Bits. Other combinations default to Hebrew English.
handbook, full pagewidth
MLA967
LANGUAGE
(C12, C13, C14)
PHCB
(1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
2
3
4
5
6
7
2
3
4
5
6
7
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ARABIC
HEBREW/ENGLISH
1 0 1
1 1 1
1996 Nov 04
41
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
APPLICATION INFORMATION
Fig.15 Application diagram for SDIP52, SOT247-1.
handbook, full pagewidth
MBD790
1
100 nF
10
k
15
pF
8.2
pF
22 nF
3.3
3.3
H
27 MHz 3rd
overtone
2
3
4
5
6
7
100 nF
8
100 nF
9
100 nF
10
27 k
11
33
F
100
nF
12
5 V
CVBS
13
14
1.5 k
330 nF
15
1 k
16
17
18
19
20
21
22
SYNC
R
G
B
23
24
25
26
BLAN
COR
ODD/EVEN
COR
ODD/EVEN
SAA5281
27
28
29
30
31
32
33
34
35
36
37
39
38
40
41
42
43
44
45
46
47
48
49
50
52
51
5 V
5 V
83C654
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
27
28
29
30
31
32
33
34
35
36
37
39
38
40
26
25
24
23
22
21
1
SDA
SCL
220
220
link
options
4.7 k
4.7 k
5 V
LINE 23
470
5 V
PDI
PL out
PON
5 V
5 V
PCF8572
PCF8582
18
27
36
45
5 V
3.3
nF
56
k
5 V
address
select
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
CLK O/P
LINE 23
CLK EN
i.c.
i.c.
n.c.
n.c.
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
V
SS3
OSCOUT
OSCIN
OSCGND
REF+
n.c.
BLACK
CVBS
IREF
V
DD2
POL
V
SS1
V
SS1
STTV/LFB
VCR/FFB
V
SS2
R
G
B
RGBREF
BLAN
Y
SCL
SDA
i.c.
i.c.
i.c.
V
DD1
i.c.
F
F
V
SS
XTAL1
XTAL2
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P1.5
SCL
SDA
RST
P1.1
P1.2
P1.3
P1.4
P1.0
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
DD
P0.0
P0.1
P0.2
P0.3
V
P0.4
P0.5
P0.6
P0.7
EA
ALE
PSEN
1996 Nov 04
42
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
PACKAGE OUTLINES
UNIT
A
max.
1
2
b
1
c
D
E
e
M
H
L
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT240-1
92-11-17
95-01-25
A
min.
A
max.
b
Z
max.
w
M
E
e
1
1.4
1.14
0.53
0.38
0.36
0.23
62.60
61.60
14.22
13.56
3.90
3.05
0.254
2.54
15.24
15.88
15.24
18.46
15.24
2.1
4.9
0.36
4.06
0.055
0.045
0.021
0.015
0.014
0.009
2.46
2.42
0.56
0.53
0.15
0.12
0.01
0.10
0.60
0.63
0.60
0.73
0.60
0.083
0.19
0.014
0.16
M
H
c
(e )
1
M
E
A
L
seating plane
A
1
w
M
b
1
e
D
A
2
Z
48
1
25
24
b
E
pin 1 index
0
5
10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
(1)
(1)
(1)
DIP48: plastic dual in-line package; 48 leads (600 mil)
SOT240-1
1996 Nov 04
43
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
UNIT
b
1
c
E
e
M
H
L
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
DIMENSIONS (mm are the original dimensions)
SOT247-1
90-01-22
95-03-11
b
max.
w
M
E
e
1
1.3
0.8
0.53
0.40
0.32
0.23
47.9
47.1
14.0
13.7
3.2
2.8
0.18
1.778
15.24
15.80
15.24
17.15
15.90
1.73
5.08
0.51
4.0
M
H
c
(e )
1
M
E
A
L
seating plane
A
1
w
M
b
1
D
A
2
Z
52
1
27
26
b
E
pin 1 index
0
5
10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
(1)
(1)
D
(1)
Z
e
A
max.
1
2
A
min.
A
max.
SDIP52: plastic shrink dual in-line package; 52 leads (600 mil)
SOT247-1
1996 Nov 04
44
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
UNIT
A
1
A
2
A
3
b
p
c
E
(1)
e
H
E
L
L
p
Q
Z
y
w
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
0.25
0.05
2.90
2.65
0.25
0.50
0.35
0.25
0.14
14.1
13.9
1
18.2
17.6
1.4
1.2
1.2
0.8
7
0
o
o
0.2
0.1
0.2
1.95
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
1.0
0.6
SOT319-2
92-11-17
95-02-04
D
(1)
(1)
(1)
20.1
19.9
H
D
24.2
23.6
E
Z
1.2
0.8
D
e
E
A
1
A
L
p
Q
detail X
L
(A )
3
B
19
y
c
E
H
A
2
D
Z D
A
Z E
e
v
M
A
1
64
52
51
33
32
20
X
pin 1 index
b
p
D
H
b
p
v
M
B
w
M
w
M
0
5
10 mm
scale
QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT319-2
A
max.
3.20
1996 Nov 04
45
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
"IC Package Databook" (order code 9398 652 90011).
Soldering by dipping or by wave
The maximum permissible temperature of the solder is
260
C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
stg max
). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Repairing soldered joints
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300
C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400
C, contact may be up to 5 seconds.
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Purchase of Philips I
2
C components conveys a license under the Philips' I
2
C patent to use the
components in the I
2
C system provided the system conforms to the I
2
C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1996 Nov 04
46
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
NOTES
1996 Nov 04
47
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
NOTES
Internet: http://www.semiconductors.philips.com
Philips Semiconductors a worldwide company
Philips Electronics N.V. 1996
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
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Printed in The Netherlands
537021/1200/02/pp48
Date of release: 1996 Nov 04
Document order number:
9397 750 01461
PDF 
ZIP