DATA SHEET
Preliminary specification
File under Integrated Circuits, IC02
1996 Oct 28
INTEGRATED CIRCUITS
SAA4996H
Motion Adaptive Colour Plus And
Control IC (MACPACIC) for
PALplus
1996 Oct 28
2
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And
Control IC (MACPACIC) for PALplus
SAA4996H
CONTENTS
1
FEATURES
2
GENERAL DESCRIPTION
3
QUICK REFERENCE DATA
4
ORDERING INFORMATION
5
BLOCK DIAGRAMS
6
PINNING
7
FUNCTIONAL DESCRIPTION
7.1
Introduction
7.1.1
Data processing
7.1.2
Control
7.2
General requirements
7.3
Hardware configurations and delays
7.3.1
Full PALplus module (see Fig.5)
7.3.2
Stand-alone MACPACIC (see Fig.6)
7.4
Analog processing in front of the PALplus
module
7.5
Block diagram
7.6
Luminance and helper processing
7.6.1
Input range
7.7
Luminance processing
7.7.1
Luminance helper processing
7.8
Output signals
7.9
Measurements
7.9.1
Line 22 offset reference measurement
7.9.2
Line 23 and 623 amplitude reference
measurement
7.9.3
Noise measurement in line 23 and 623
7.10
Automatic gain and offset control
7.10.1
SNERT control bits influencing the AGC and
AOC
7.10.2
Gain control
7.10.3
Offset control
7.10.4
Helper amplitude and bandwidth control
7.11
Output range
7.12
Chrominance
7.12.1
Input range
7.12.2
Chrominance processing
7.12.3
Output signals
7.12.4
Output range
7.13
Chrominance motion detection
7.14
Intelligent residual cross-luminance reduction
(IRXR)
7.15
Control
7.15.1
Input reference signals
7.15.2
Functional description
7.15.3
SNERT interface (see application note
AN95XXX)
8
TEST
8.1
Boundary scan test
8.1.1
Identification codes
9
DC CHARACTERISTICS
10
AC CHARACTERISTICS
10.1
Clock buffers
11
LIST OF ABBREVIATIONS
12
PACKAGE OUTLINE
13
SOLDERING
13.1
Introduction
13.2
Reflow soldering
13.3
Wave soldering
13.4
Repairing soldered joints
14
DEFINITIONS
15
LIFE SUPPORT APPLICATIONS
1996 Oct 28
3
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
SAA4996H
1
FEATURES
Motion adaptive colour plus decoding
Helper AGC/AOC
Helper decompanding
Memory controlling
VERIC controlling.
2
GENERAL DESCRIPTION
The SAA4996H (MACPACIC) performs the Motion
Adaptive Colour Plus (MACP) processing which is a
dedicated field comb filter technique exploited for the
PALplus system.
The integrated circuit is especially designed to be used in
conjunction with the SAA4997H Vertical Reconstruction IC
(VERIC) to decode the transmitted PALplus video signals
in PALplus colour TV receivers.
In addition, a hardware configuration `stand-alone
MACPACIC' with only two field memories (FM1 and FM4)
is also possible. In this condition no helper lines are
processed and no vertical reconstruction is applied.
This configuration enables the Motion Adaptive Colour
Plus processing to be performed in non PALplus receivers.
3
QUICK REFERENCE DATA
4
ORDERING INFORMATION
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
V
DD
digital supply voltage
4.75
5.25
V
T
amb
operating ambient temperature
0
+70
C
T
die
die temperature
-
+125
C
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
SAA4996H
QFP100
plastic quad flat package; 100 leads (lead length 1.95 mm);
body 14
20
2.7 mm; high stand-off height
SOT317-1
1996 Oct 28
5
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
SAA4996H
handbook, full pagewidth
3
EVEN_FIELD
Mpip
VA_AI
DSP
LINE
COUNTER
9 BIT
PRE
CLK
CLK_16I
PIXEL
DECODER
PIXEL
COUNTER 2
10 BIT
LINE
DECODER
PC1
EVEN_FIELD
PC2
WE_MA
11
H / V
LOGIC
TEST AND BST
PRE
EN
PRE
EN
LC_ACQ
LC_DSP
9
9
CLK_16I
VA_FRONT
VA_RES
CLAMP
A
CQ
LINE
COUNTER
9 BIT
WE_FRONT
WeShift16_0,1
WeStrtH,V
WeStpH,V
36
FILM
INTPOL
Mpip
FilmOn
InvO/E
MacpOn
MotVis0,1
SNERT_RST
SNERT_CL
SNERT_DA
HREF_MA
CLAMP
2 CLK_16
DELAY
FilmOn
HlpM0,1
2
Mpip
CLK_16I
CLK_16B1
CLK_16B2
CLK_16B3
CLK_32B1
CLK_32B2
CLK_32B3
CLK_32
CLK_16
Mpip
VA_AI_DIFF
Mpip
VA_AI_DIFF
PC1
CLP_DIFF
LD = 1
LD = 1
VA_AI
CLP_DIFF
VA_RES
VA_FR_DEL
IVericN
IVericN
VA_RES
IVericN
Mpip
0
1
0
1
WE_MA
CLK_16I
CLK_32I
3
VaDel0-2
VA_FR_DEL
IVericN
InvO/E
VA_AI_DIFF
IVericN
MUX1
1
0
SEL
MUX2
1
0
SEL
WE_MA
GENERATION
PC2_PRE
line2_every_field
VA_FRONT
DELAY
CLK_16I
CLK_16I
CLK_16I
CLK_16I
CLK_16I
FIELD LENGTH
MEASUREMENT,
FIELD
DETECTION,
VA_AI DELAY
(1/2 LINE)
CLK_16I
CLK_32I
RSTW_FM23
WE_FM3
WE_FM2
RE_FM1
WE_FM1
RST_FM14
RE_FM4
WE_FM4
16/32 MHz
CONVERTER
EVEN_FIELD
22Valid
HlpM0,1
2
Preset
VaDel0-2
HlpM0,1
Control 4:
SelSdYl0,1,
NmYl0,1,
Rha/Rhb0-2
Control 5:
BOH0-2,
VAA0,1,
NAIRXR
SEL_SD_YL0,1,
7
Control 6:
7
2
3
2
Interlace,
EnPreEvFld,
PreEvFld
EnIRXR
MacpYhThr1-3
HlpRedThr1-5,
64
IrxrThr1-4,
FixHlpMain
40
Control 3:
22/23/623Valid,
IMacpacicN,
IVericN
5
TDO_MA
H_RE / WE
V_RE / WE
6
LD = 2
CLOCK
BUFFER
VERIC
CONTR
OL
DECODER
6
10
PRE
CLK
PIXEL
COUNTER 1
10 BIT
LD = 2
TRSTN
TDI
TMS
TCK
TEST1
TEST2
TEST3
line2_every_field
SNERT INTERFACE
MHA137
Fig.2 Block diagram of the control part.
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