Philips Semiconductors

Product specification

Digital equalization for the tape
drive processing of the DCC system

SAA2032

February 1995

FEATURES

Analog-to-digital conversion, demultiplexing,
equalization and zero crossing of time multiplexed
analog read amplifier signal

Microcontroller interface

Search mode envelope, label and virgin detection of the
AUX channel

Search mode tape speed measurement

Simplified external biassing

Reduced power consumption

Analog eye output

4 V nominal operating voltage capability.

GENERAL DESCRIPTION

Performing the Digital Equalizing function in the Digital
Compact Cassette (DCC) system, the SAA2032 is
intended for use in conjunction with the SAA2022, read
amplifier TDA1317 or TDA1318.

ORDERING INFORMATION

Note

1. When using reflow soldering it is recommended that the Dry Packing instructions in the

Quality Reference Pocketbook

are followed. The pocketbook can be ordered using the code 9398 510 34011.

EXTENDED TYPE

NUMBER

PACKAGE

PINS

PIN POSITION

MATERIAL

CODE

SAA2032GP

QFP 1

plastic

SOT205AG

February 1995

Philips Semiconductors

Product specification

Digital equalization for the tape
drive processing of the DCC system

SAA2032

PINNING

SYMBOL

PIN

DESCRIPTION

DIGEYE

serial data output for eye pattern

RDSYNC

SYNC data for Read Amplifier (push-pull output)

RDCLK

data clock for Read Amplifier (push-pull output)

TEST1

test 1; to be connected to V

VIN

analog time multiplexed input from Read Amplifier

REFN

lower reference voltage (+1 V) for ADC

REFP

upper reference voltage (+3.1 V) for ADC

SSA

analog ground (0 V)

BIASA

bias current for ADC (sinks current from V

DDAD

via 33 k

)

SSAD

supply ground (0 V) for ADC

DDAD

supply voltage (+5 V) for ADC

supply voltage (+5 V)

supply ground (0 V)

SSA

supply ground (0 V)

ANEYE

analog eye voltage output

n.c.

not connected

supply ground (0 V)

TEST4

test 4; do not connect

TEST5

test 5; do not connect

TEST6

test 6; do not connect

TEST7

test 7; do not connect

CH0

channel 0 output for SAA2022 (DCC Drive Signal Processing) (push-pull output)

CH1

channel 1 output for SAA2022 (push-pull output)

CH2

channel 2 output for SAA2022 (push-pull output)

CH3

channel 3 output for SAA2022 (push-pull output)

CH4

channel 4 output for SAA2022 (push-pull output)

CH5

channel 5 output for SAA2022 (push-pull output)

CH6

channel 6 output for SAA2022 (push-pull output)

CH7

channel 7 output for SAA2022 (push-pull output)

AUX

AUX channel output for SAA2022 (push-pull output)

LTDATA

microcontroller I/O data interface (3-state push-pull output and input; CMOS levels)

LTENDEQ

microcontroller interface enabling (CMOS input levels)

LTCNT1

microcontroller interface; mode control 1 (CMOS input levels)

LTCNT0

microcontroller interface; mode control 0 (CMOS input levels)

LTCLK

microcontroller bit-clock interface (CMOS input levels)

VIRGIN

search mode virgin detection output

LABEL

search mode label detection output

AENV

search mode auxiliary detection output

supply ground (0 V)

Philips Semiconductors

Product specification

Digital equalization for the tape
drive processing of the DCC system

SAA2032

February 1995

FUNCTIONAL DESCRIPTION

Operating Modes

DEQ operating modes are programmed via the LT
interface:

ORMAL

A/D conversion

Demultiplexing

Equalization

Zero crossing.

in this mode the SAA2032 performs the equalization and
slicing of the eight data channels and the auxiliary channel.
The eight data channels have a bit-rate of 96 kbits/s while
the auxiliary channel has a bit-rate of 12 kbits/s.

The SAA2032 input is a time-multiplexed analog signal
from the Read Amplifier. The signal contains ten time slots,
of which nine are used. The Read Amplifier and the
SAA2032 synchronize with the RDCLK and RDSYNC
signals generated by the SAA2032.

Following A/D conversion and demultiplexing the nine
channels are equalized. The encoding of the equalizing
coefficients (12 per channel) are not fixed and must be
loaded via the LT interface before operation.

The nine equalized output signals are up-sampled by a
factor of 10 with the resulting signals fed to the slicer. The
slicer output is applied to the SAA2022.

EST

A/D conversion

Demultiplexing

Equalization

Zero crossing

Eye-pattern.

Same as normal mode. In addition the digital and analog
eye-pattern outputs are enabled. The eye-pattern output
corresponds to one of the equalized channel outputs.

EARCH

A/D conversion

Envelope detection

Tape search and speed measurement.

In the search mode the analog input signal from the Read
Amplifier is not the multiplexed signal but only the auxiliary
channel signal.

Following A/D conversion the envelope of this signal is
filtered and sliced. This forms the Alternating Envelope
AENV output. The LABEL and VIRGIN outputs are
detected from this and the tape search speed measured.

In the OFF mode the RDSYNC and RDCLK signals are
HIGH, the EYE outputs are disabled and the channel and
auxiliary outputs (CH0 to CH7 and AUX) are 3-stated.

Read Amplifier interface

The interface between the Read Amplifier and the
SAA2032 consists of three signals:

VIN from Read Amplifier to SAA2032; time
multiplexed data.

RDSYNC from SAA2032 to Read Amplifier;
synchronization between Read Amplifier multiplexer
and SAA2032 demultiplexer.

RDCLK from SAA2032 to Read Amplifier; data clock
for Read Amplifier multiplexer.

The multiplexed VIN output of the Read Amplifier changes
to another channel at the rising edge of RDCLK. RDSYNC
synchronizes the Read Amplifier VIN output: if RDSYNC is
HIGH, the rising edge of the RDCLK will select the AUX
channel.

Figures 4 and 5 show the relationship between the
SAA2032 and the Read Amplifier.

SAA2022 interface

The interface with the SAA2022 consists of the 9 data
output signals CH0 to CH7, AUX.

Table 1

Dependency of Read Amplifier on
operational mode.

Label and virgin detection interface

When the DCC player is in its search mode, the tape is
fast-wound while the head retains tape contact. The
SAA2032 can be made to operate in the search mode and
the information will be read from the auxiliary tape track.

OPERATIONAL MODE

RDSYNC

RDCLK

Normal

YES

Test

YES

HIGH

YES

Off

HIGH

February 1995

Philips Semiconductors

Product specification

Digital equalization for the tape
drive processing of the DCC system

SAA2032

The following three signals are generated:

LABEL: label detection (HIGH if label is detected).

VIRGIN: virgin tape detection (HIGH if virgin tape
is detected).

AENV: alternating envelope (sliced envelope).

AENV, LABEL and VIRGIN are disabled in normal or off
modes. LABEL, VIRGIN and AENV are LOW.

AENV, LABEL and VIRGIN are enabled when the
SAA2032 is in search mode.

The device detects the envelope AENV of the auxiliary
track at search speeds between 3 and 50 times normal
speed. If AENV is continuously HIGH (label detection),
LABEL will be HIGH.

When AENV is continuously LOW (virgin tape detection)
VIRGIN will be HIGH.
Figures 6, 7 and 8 show the relationship between AENV,
VIRGIN and LABEL.

Labelled tape-speed calculation

When the DCC player is in its search mode, the tape
speed increases. LABEL information is encoded
throughout its length. To examine the length of a label, the

tape speed must be known. In search mode the SAA2032
assesses the speed of labelled tapes. The microcontroller
obtains this information via the LT-interface.

The speed information is encoded in 3 variables:

SVF Speed Validation Flag (HIGH if invalid).

SC (4..0) Speed counter.

SR (1..0) Speed Range.

If SC = 0 then search speed > 51.2.

With SR = 0, 1, 2 or 3 and SC = 0 to 31.

If SVF = 1 then SR and SC values are invalid.

Appendix 1 gives a table of the search mode speed
control.

Microcontroller (LT) Interface

The SAA2032 is able to exchange information with the
microcontroller via the LT-interface. The microcontroller
performs as master, the SAA2032 as slave.

Figure 9 gives the operation of the LT-interface.

Search speed

51.2

-----------

x normal speed.

Fig.4 Signals on interface between Read Amplifier and SAA2032.

RDCLK

RDSYNC

VIN

MCD477

CH7 AUX

***

CH0

CH3 CH4 CH5 CH6 CH7 AUX

***

CH0

CH2

CH1

Philips Semiconductors

Product specification

Digital equalization for the tape
drive processing of the DCC system

SAA2032

February 1995

Mode Settings Load (LTCNT = 11) (See Fig.10)

The 8-bits transmitted under 'mode settings load' control
both the 'operation mode' and the 'data exchange type'.

Table 3

Mode settings; 'operation mode'.

Table 4

Mode settings; 'data exchange type'.

Remark post condition: after every communication
sequence the data exchange type must be set to "read
coefficient data".

OPERATION MODE

normal

test

off

DATA

EXCHANGE

TYPE

write

coefficient

data

read

coefficient

data

read

envelope

data

Fig.10 Mode settings load (LTCNT = 11).

MSB

LSB

MCD480

data

exchange

type

operation

mode

Address Information Load (LTCNT = 10) (See Fig.11)

A channel/tap combination can be selected through this
type of data exchange.

Co-efficient Data Load (LTCNT = 00) (See Fig.12)

This type of data exchange will overwrite the equalizer tap
coefficient of the current selected channel/tap
combination.

The coefficient data for tap <0000> of the auxiliary channel
should always be zero.

Data Read (LTCNT = 01) (See Fig.13)

This type of data exchange will send information from the
LTDATA register in the SAA2032 to the microcontroller.
Data in the LTDATA register depends upon the current
data exchange type.

LTDATA interpretation:

coefficient data: two's complement coefficient data

tape speed data

d7 = SVF flag

d6 to d2 = SC4 to SC0

d1, d0 = SR1, SR0.

Tape speed data format is shown in Fig.14.

February 1995

Philips Semiconductors

Product specification

Digital equalization for the tape
drive processing of the DCC system

SAA2032

Eye pattern output

To test equalization performance it is possible to output the
equalized channels. For this purpose one analog and two
digital output signals are provided. Selection of the EYE
pattern output is determined by the last channel address
sent to the SAA2032.

DIGEYE: serial data line for 8-bits output value

VAL: validation signal for data bits

ANEYE: analog eye voltage output.

The eye outputs are enabled in test mode.

Table 5

Eye outputs.

The internal number representation in the SAA2032 is in
two's complement. The format of the selected 8-bits will be
converted to the off-set-binary format. This means that the
MSB of the two's complement number has been inverted.
This 8-bit number is shifted out via the DIGEYE output.

Figure 17 gives the eye pattern output timing.

OPERATION MODE

DIGEYE

ANEYE

Normal

LOW

HIGH

Test

ENABLED

LOW

HIGH

Off

LOW

HIGH

Fig.17 Timing diagram.

MEA662 - 1

stable

data

t h

tsu

tclk

RDCLK

DIGEYE

LSB

MSB

(inverted)

LSB

DIGEYE

RDCLK

VAL

t val

t eye

val

= 1/4 clock period; pulse width HIGH.

> 60 ns; minimum set-up time data before clock.

> 5 ns; minimum hold time data after clock.

clk

= 1/f

clk

= 3.072 MHz; nominal DIGEYE clock frequency.

eye

= 1/f

eye

= 307.2 kHz; nominal DIGEYE clock frequency.

February 1995

Philips Semiconductors

Product specification

Digital equalization for the tape
drive processing of the DCC system

SAA2032

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. Input voltage should not exceed 6.5 V unless otherwise specified.

2. Equivalent to discharging a 100 pF capacitor through a 1.5 k

series resistor.

3. Equivalent to discharging a 200 pF capacitor through a 0

series resistor.

DC CHARACTERISTICS

= 3.8 to 5.5 V; T

amb

40 to +85

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

supply voltage

0.5

+6.5

input voltage

note 1

0.5

+ 0.5

supply current in V

100

supply current in V

100

input current

output current

tot

total power dissipation

550

stg

storage temperature

+150

amb

operating ambient temperature

+85

es1

electrostatic handling

note 2

1500

+1500

es2

electrostatic handling

note 3

+70

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

supply voltage

3.8

5.0

5.5

DDAD

supply voltage for ADC

note 1

3.8

5.0

5.5

supply current

= 5 V; note 2

= 3.8 V; note 2

DDAD

supply current for ADC

DDAD

= 5 V

DDAD

= 3.8 V

operating current

note 3

1.3

1.9

3.4

Inputs f24, LTCLK, LTCNT0, LTCNT1 and LTENDEQ

LOW level input voltage

0.3V

HIGH level input voltage

0.7V

input current

= 0 V; T

amb

= 25

= V

; T

amb

= 25

Input REFP

refp

reference voltage

2.7

3.1

3.4

Input REFN

refn

reference voltage

0.7

1.0

1.4

February 1995

Philips Semiconductors

Product specification

Digital equalization for the tape
drive processing of the DCC system

SAA2032

Notes

1. V

DDAD

should never be lower than V

0.2 V.

2. For load impedances in a typical application circuit.

3. Operating reference current for the specified range of V

refp

allowing for the tolerance on the internal resistor.

4. For outputs DIGEYE, RDSYNC, RDCLK, CH0 to CH7, AUX and VAL the maximum load current is 1 mA. For ANEYE

output the maximum load current is 10

A. For VIRGIN, LABEL and AENV the maximum load current is 2 mA.

Inputs REFP and REFN

ref

reference voltage difference
between REFP and REFN

2.1

2.7

Input VIN

I(p-p)

input voltage (peak-to-peak)

refn

refp

input current

100

Digital outputs

LOW level output voltage

note 4

0.4

HIGH level output voltage

note 4

0.5

Output ANEYE

output voltage

note 4

DDAD

output voltage range

note 4

1.1

Input/output LTDATA

LOW level output voltage

3 mA

0.4

HIGH level output voltage

= 2 mA

0.5

leakage current with outputs
in 3-state

= 0 V; T

amb

= 25

= V

; T

amb

= 25

LOW level input voltage

0.3V

HIGH level input voltage

0.7V

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

February 1995

Philips Semiconductors

Product specification

Digital equalization for the tape
drive processing of the DCC system

SAA2032

AC CHARACTERISTICS

= 3.8 to 5.5 V; T

amb

40 to 85

C; unless otherwise specified.

Note

1. LOW-to-HIGH transition.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

VIN

input capacitance

All digital inputs

input capacitance

Clock input f24

clock frequency

24.576

MHz

pulse width LOW or HIGH

Inputs LTCLK, LTENDEQ, LTCNT0 and LTCNT1

set-up time to f24

note 1

hold time from f24

note 1

All outputs

input capacitance

load capacitance

propagation delay time from f24

note 1

Input/output LTDATA

input capacitance

load capacitance

propagation delay time from f24

set-up time to f24

note 1

hold time from f24

note 1

February 1995

Philips Semiconductors

Product specification

Digital equalization for the tape
drive processing of the DCC system

SAA2032

CONVERTER CHARACTERISTICS

= 3.8 to 5.5 V; T

amb

40 to 85

C; unless otherwise specified.

Notes

1. V

refp

is supplied externally.

refn

is derived internally and set to

refp

refn

must be decoupled externally at pin 6 via a 100 nF capacitor.

2. Signal level (f

)

20 dB, at any DC level within the input voltage range.

3. The output impedance of the analog input signal source must be <150

4. Load impedance

1 M

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Analog-to-Digital Converter; VIN

resolution

bits

conversation data available after

effective input bandwidth

6-bit resolution
at f

= 3.1 MHz

0.5

MHz

differential non-linearity

0.99

LSB

refn

reference voltage at VREFN

note 1

0.7

1.0

1.4

refp

reference voltage at VREFP

2.7

3.1

3.4

ref

reference voltage difference
between REFP and REFN

2.1

2.7

input voltage

refn

refp

S+THD/N

signal-to-total harmonic
distortion and noise ratio

note 2

input capacitance

input current (DC)

note 3

100

Digital-to-analog converter; output ANEYE

resolution

bits

output voltage

note 4

DDAD

output voltage range

note 4

1.1

February 1995

Philips Semiconductors

Product specification

Digital equalization for the tape
drive processing of the DCC system

SAA2032

APPENDIX 1

Search Mode Speed Control Interface

In search mode the SAA2032 measures the tape speed. The tape speed is encapsulated in the variables:

SVF Speed Validation Flag; is HIGH if NOT valid

SC Speed Counter

SR Speed Range.

The values in Table 6 represent the speed in multiples of the nominal tape speed of 4.76 cm/s.

Table 6

Speed in multiples of nominal tape speed.

SC[4 .. 0]

SR[1 .. 0]

REMARKS

>51.20

>102.40

>204.80

>409.60

shift to higher speed range

51.20

102.40

204.80

409.60

25.60

51.20

102.40

204.80

17.07

34.13

68.27

136.53

12.80

25.60

51.20

102.40

10.24

20.48

40.96

81.92

8.53

17.07

34.13

68.27

7.31

14.63

29.26

58.51

6.40

12.80

25.60

51.20

normal working area

5.69

11.38

22.76

45.51

5.12

10.24

20.48

40.96

4.65

9.31

18.62

37.24

4.27

8.53

17.07

34.13

3.94

7.88

15.75

31.51

3.66

7.31

14.63

29.26

3.41

6.83

13.65

27.31

3.20

6.40

12.80

25.60

3.01

6.02

12.05

24.09

February 1995

Philips Semiconductors

Product specification

Digital equalization for the tape
drive processing of the DCC system

SAA2032

SOLDERING

Quad flat-packs

Y WAVE

During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150

C within 6 s.

Typical dwell time is 4 s at 250

A modified wave soldering technique is recommended
using two waves (dual-wave), in which, in a turbulent wave
with high upward pressure is followed by a smooth laminar
wave. Using a mildly-activated flux eliminates the need for
removal of corrosive residues in most applications.

Y SOLDER PASTE REFLOW

Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and vapour-
phase reflow. Dwell times vary between 50 and 300 s
according to method. Typical reflow temperatures range
from 215 to 250

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45

EPAIRING SOLDERED JOINTS

(

BY HAND

HELD SOLDERING

IRON OR PULSE

HEATED SOLDER TOOL

)

Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300

C. When using proper tools, all other pins can be

soldered in one operation within 2 to 5 s at between 270
and 320

C. (Pulse-heated soldering is not recommended

for SO packages.)

For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.

February 1995

Philips Semiconductors

Product specification

Digital equalization for the tape
drive processing of the DCC system

SAA2032

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress rating only and operation of
the device at these or at any other conditions above those given in the Characteristics sections of the specification is
not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

The Digital Compact Cassette logo is a registered trade mark of Philips Electronics N.V.

Philips Semiconductors a worldwide company

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Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc,

106 Valero St. Salcedo Village, P.O. Box 911, MAKATI,
Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474

Portugal: Av. Eng. Duarte Pacheco 6, 1009 LISBOA Codex,

Tel. (01)683 121, Fax. (01)658 013

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. (65)350 2000, Fax. (65)251 6500

South Africa: 195-215 Main Road, Martindale,

P.O. Box 7430,JOHANNESBURG 2000,
Tel. (011)470-5433, Fax. (011)470-5494

Spain: Balmes 22, 08007 BARCELONA,

Tel. (03)301 6312, Fax. (03)301 42 43

Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM,

Tel. (0)8-632 2000, Fax. (0)8-632 2745

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. (01)488 2211, Fax. (01)481 7730

Taiwan: 69, Min Sheng East Road, Sec 3, P.O. Box 22978,

TAIPEI 10446, Tel. (2)509 7666, Fax. (2)500 5899

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

60/14 MOO 11, Bangna - Trad Road Km. 3
Prakanong, BANGKOK 10260,
Tel. (2)399-3280 to 9, (2)398-2083, Fax. (2)398-2080

Turkey: Talatpasa Cad. No. 5, 80640 LEVENT/ISTANBUL,

Tel. (0212)279 2770, Fax. (0212)269 3094

United Kingdom: Philips Semiconductors Limited, P.O. Box 65,

Philips House, Torrington Place, LONDON, WC1E 7HD,
Tel. (071)436 41 44, Fax. (071)323 03 42

United States: INTEGRATED CIRCUITS:

811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. (800)234-7381, Fax. (708)296-8556
DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd.,

P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404,
Tel. (800)447-3762 and (407)881-3200, Fax. (407)881-3300

Uruguay: Coronel Mora 433, MONTEVIDEO,

Tel. (02)70-4044, Fax. (02)92 0601

For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BAF-1,
P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. +31-40-724825

SCD28

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Philips Semiconductors

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Document Outline

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Document Outline

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