Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

February 1994

FEATURES

Integrated error correction encoder/decoder function
with Digital Compact Cassette (DCC) optimized
algorithms

Control of capstan servo during recording and after
recording by microcontroller

Frequency and phase regulation of capstan servo
during playback

Choice of two Dynamic Random Access Memory
(DRAM) types operating in page mode

Scratch pad RAM area available to microcontroller in
system DRAM

Low power standby mode

S interface

Microcontroller interface for high-speed transfer burst
rates up to 170 kbytes per second

SYSINFO and AUXILIARY data flags on microcontroller
interface

Protection against invalid AUXILIARY data

+4 V operating voltage capability.

GENERAL DESCRIPTION

Performing the tape formatting and error correction
functions for DCC applications, the SAA2022 can be used
in conjunction with the PASC (SAA2002/SAA2012), tape
equalization (SAA2032), read amplifier (TDA1317 or
TDA1318) and write amplifier (TDA1316 or TDA1319)
circuits to implement a full signal processing system.

ORDERING INFORMATION

Note

When using reflow soldering it is recommended that the Dry Packing instructions in the

"Quality Reference

Pocketbook" are followed. The pocketbook can be ordered using the code 9398 510 34011.

EXTENDED TYPE

NUMBER

PACKAGE

PINS

PIN POSITION

MATERIAL

CODE

SAA2022GP

QFP

(1)

plastic

SOT208A

February 1994

Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

PINNING

SYMBOL

PIN

DESCRIPTION

LTREF

timing reference for microcontroller interface

LTDATA

data for microcontroller interface (3-state; CMOS levels)

LTCNT1

control for microcontroller interface

LTCNT0

control for microcontroller interface

LTCLK

bit clock for microcontroller interface

LTEN

enable for microcontroller interface

SS2

supply ground (0 V)

DD2

supply voltage (+5 V)

RASN

DRAM row address strobe

WEN

DRAM write enable

DRAM data (MSB); 3-state output; TTL compatible input

DRAM data; 3-state output; TTL compatible input

DRAM data (LSB); 3-state output; TTL compatible input

CASN

DRAM column address strobe

OEN

DRAM output enable

DRAM address (MSB)

DRAM address

DRAM address (LSB)

SS3

supply ground (0 V)

DD3

supply voltage (+5 V)

WCLOCK

clock for write amplifier transfers

WDATA

write amplifier serial data

SPEED

capstan phase information

SPDF

capstan frequency information

PINO1

Port expander output 1

TAUX

AUX channel input from SAA2032

TCH7

main data channel 7, input from SAA2032

TCH6

main data channel 6, input from SAA2032

TCH5

main data channel 5, input from SAA2032

TCH4

main data channel 4, input from SAA2032

TCH3

main data channel 3, input from SAA2032

TCH2

main data channel 2, input from SAA2032

February 1994

Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

TCH1

main data channel 1, input from SAA2032

TCH0

main data channel 0, input from SAA2032

SS1

supply ground (0 V)

DD1

supply voltage (+5 V)

CLK24

24.576 MHz clock from SAA2002

TEST0

test select LSB; do not connect

TEST1

test select MSB; do not connect

PWRDWN

sleep mode selection

RESET

reset input with hysteresis and pull-down resistor

PINI

Port expander input

PINO2

Port expander output 2

PINO3

Port expander output 3

AZCHK

azimuth check (channels 0 and 7)

TEST2

symbol error rate measurement output

TEST3

do not connect

MCLK

master clock output (6.144 MHz)

SBMCLK

master clock for SB-I

S-interface

SBEF

byte error SB-I

S-interface

SS4

supply ground (0 V)

DD4

supply voltage (+5 V)

SBWS

word select SB-I

S-interface; 3-state output; CMOS levels

SBCL

bit clock SB-I

S-interface; 3-state output; CMOS levels

SBDA

data line SB-I

S-interface; 3-state output; CMOS levels

SBDIR

direction SB-I

S-interface

URDA

unusable data SB-I

S-interface

SYMBOL

PIN

DESCRIPTION

Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

February 1994

The SAA2022 provides the following functions:

In Playback Modes

Tape channel data and clock recovery

10 to 8 demodulation

Data placement in DRAM

C1 and C2 error correction decoding

S-interfacing to SB-I

S-bus

Interfacing to microcontroller for SYSINFO and
AUX data

Capstan control for tape deck.

In Record Modes

S-interfacing to SB-I

S-bus

C1 and C2 error correction encoding

Formatting for tape transfer

8 to 10 modulation

Interfacing to microcontroller for SYSINFO and
AUX data

Capstan control for tape deck, programmable by
microcontroller.

Operational Modes

The 3 basic modes of operation are:

DPAP - Main data (audio) and SYSINFO play, AUX play

DRAR - Main data (audio) and SYSINFO record,
AUX record

DPAR - Main data (audio) and SYSINFO play,
AUX record.

Hardware Interfacing

RESET

This is an active HIGH input signal which resets the
SAA2022 and brings it into its default mode, DPAP. This
should be connected to the system reset, which can be
driven by the microcontroller. The duration of the reset
pulse should be at least 15

s. This pin has an internal

pull-down resistor of between 20 k

and 125 k

PWRDWN

This pin is an active HIGH signal which places the
SAA2022 in a "SLEEP" mode. When the SAA2022 is in
"SLEEP" mode and the CLK24 is either held HIGH or held
LOW, there is no activity in the device, thus resulting in
no EMI and a low power dissipation (typically <10% of
operational dissipation). This pin should be connected to
the DCC power-down signal, which can be driven by the
system microcontroller.

To enter the "SLEEP" mode the SAA2022 should reset
and hold reset. After a delay of at least 15

s the

PWRDWN pin should be brought HIGH after which the
state of the reset pin is "don't care". The power dissipation
is reduced further when the CLK24 input signal stops.

When recovering from "SLEEP" mode the PWRDWN pin
should be driven LOW and the chip reset with a pulse of at
least 15

s duration.

CLK24

This is the 24.576 MHz clock input and should be
connected directly to the SAA2002 CLK24 pin.

Connections to SAA2032

TCH0

TCH7

AND

TAUX

These lines are the equalized and clipped (to V

) tape

channel inputs and should be connected to the SAA2032
pins TCH0 to TCH7 and TAUX.

Sub-band I

S-bus Connections

The timing for the SB-I

S-interface is given in Figs 4 to 9.

Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

February 1994

SBMCLK

This is the sub-band master clock input for the
SB-I

S-interface. The frequency of this signal is nominally

6.144 MHz. This pin should be connected to the SBMCLK
pin of the SAA2002.

SBDIR

This output pin is the sub-band I

S-bus direction signal, it

indicates the direction of transfer on the SB-I

S-bus.

A logic 1 indicates a SAA2022 to SAA2002 transfer
(audio play) whilst a logic 0 is output for a SAA2002 to
SAA2022 transfer (audio record). This pin connects
directly to the SBDIR pin on the SAA2002.

SBCL

This input/output pin is the bit clock line for the
SB-I

S-interface to the SAA2002. Is has a nominal

frequency of 768 kHz.

SBWS

This input/output pin is the word select line for the
SB-I

S-interface to the SAA2002. It has a nominal

frequency of 12 kHz.

SBDA

This input/output pin is the serial data line for the
SB-I

S-interface to the SAA2002.

SBEF

This active HIGH output pin is the error per byte line for the
SB-I

S-interface to the SAA2002.

URDA

This active HIGH output pin indicates that the main data
(audio), the SYSINFO and the AUXILIARY data are not
usable, regardless of the state of the corresponding
reliability flags. The state of this pin is reflected in the
URDA bit of STATUS byte 0, which can be read by the
microcontroller. This pin should be connected directly to
the URDA pin of the SAA2002. URDA is activated as a
result of a reset, a mode change from DRAR to DPAP, or
if the SAA2022 has had to resynchronize with the incoming
data from tape.

The position of the first SB-I

S-bytes in a tape frame is

shown in Fig.10.

February 1994

Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

Fig.11 DRAM timing read cycle.

MEA702

MCLK

RASN

CASN

D0...D3

A0...A7 (A8)

OEN

WEN

1 read cycle = 651 ns

ROW

COLUMN #0

COLUMN #1

COLUMN #2

DRAM Interface

The SAA2022 has been designed to operate with
64 k

4-bit or 256 k

4-bit DRAMs operating in page

mode, with an access time of 80 to 100 ns. The timing for
read, write and refresh cycles is shown in Figs 11 to 13.

CASN

This output pin is the column address strobe (active LOW)
for the DRAM, it connects directly to the column address
strobe pin of the DRAM.

RASN

This output pin is the row address strobe (active LOW) for
the DRAM, it connects directly to the row address strobe
pin of the DRAM.

OEN

This pin provides the output enable (active LOW) for the
DRAM, it connects directly to the output enable pin of the
DRAM.

WEN

This output pin provides the write enable (active LOW) for
the DRAM, it connects directly to the write enable pin of the
DRAM.

These output pins are the multiplexed column and row
address lines for the DRAM. When the 64 k

4-bit DRAM

is used, pins A0 to A7 should be connected to the DRAM
address input pins, and pin A8 should be left unconnected.
When using the 256 k

4-bit DRAM then address pins

A0 to A8 should be connected to the address input pins of
the DRAM.

February 1994

Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

Fig.13 DRAM refresh cycle.

MEA704 - 1

MCLK

RASN

CASN

D0...D3

A0...A7 (A8)

OEN

WEN

1 refresh cycle = 651 ns

ROW

Tape deck capstan control interface

SPEED

This signal is a pulse width modulated output that may be
used to control the tape deck capstan. The period of the
SPEED signal is 41.66

s and the nominal duty cycle is

50%.

There are 4 modes of operation for the SPEED signal
which can be selected by the programmed settings of

CSPD (microcontroller capstan speed), ENFREG

(enable frequency regulation) and ENEFREG (enable
extended frequency regulation) flags.

SPDF

CSPD = logic 0 this pin outputs a pulse width

modulated measurement of the main data channel bit
rates and may be used in combination with the SPEED
signal to control the tape deck capstan. The period of the

SPDF signal is 5.2

s. The duty cycle of SPDF can vary

from 0% at +6.5% deviation to 100% at

6.5% deviation. If

the deviation = 0% then the duty cycle of SPDF is 50%.

Microcontroller Interface

LTREF

The SAA2022 divides time into segments of 42.67 ms
nominal duration which are counted in modulo 4. The
LTREF active LOW output pin can be connected directly to
the interrupt input of the microcontroller and indicates the
start of a time segment. It goes LOW for 5.2

s once every

42.66 ms and can be used for generating interrupts. Note
if a resync occurs then the time between the occurrences
of LTREF can vary. The function and programming of the
other interface lines LTCNT0, LTCNT1, LTEN, LTCLK and
LTDATA are described in the pinning and programming
sections.

February 1994

Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

Fig.15 AZCHK timing.

handbook, full pagewidth

MEA705

(8 periods MCLK)

1.3

This is a measure of the azimuth error.

Duration of the one tape block

5.3 ms

AZCHK

Test Pins

TEST0, TEST1, TEST2

AND

TEST 3

These input pins are for test use only and for normal
operation should not be connected.

AZCHK

This output pin indicates the occurrence of a tape channel
sync symbol on tape channels TCH0 and TCH7. The
separation between the pulses for the TCH0 and TCH7
channels gives a measure of the azimuth error between
the tape and head alignment (see Fig.15).

Port Expansion Pins

PINI

This input pin is connected directly to the PINI bit in the
STATUS byte 1, it can be read by the microcontroller, and
may be used for any CMOS level compatible input signals.

PINO1

This output pin is connected directly to the PINO1 bit of the
SETTINGS byte 1 register and can be set or reset by the
microcontroller.

PINO2

This output pin is connected directly to the PINO2 bit of the
SETTINGS byte 1 register and can be set or reset by the
microcontroller.

PINO3

This output pin is connected directly to the PINO3 bit of the
SETTINGS byte 1 register and can be set or reset by the
microcontroller.

Power Supply Pins

DD1

DD4

These are the +5 V power supply pins which must all be
connected. Decoupling of V

SS1

to V

SS4

is recommended.

SS1

SS4

These are the +5 V power supply ground pins, all of which
must be connected.

February 1994

Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

Programming the SAA2022 via the Microcontroller Interface

Table 1

SAA2022 interface connections to the microcontroller.

All transfers are in units of 8-bits, registers with less than 8-bits are LSB justified, unless otherwise specified. The four
basic types of transfer are shown in Table 2.

Table 2

Types of transfer.

Microcontroller Interface Registers

The SAA2022 microcontroller interface has 7 write and 4 read registers, as shown in Table 3.

Table 3

SAA2022 Microcontroller Interface Registers.

PIN

INPUT/OUTPUT

DESCRIPTION

LTEN

enable active HIGH

LTCLK

clock signal

LTCNT0

control LSB

LTCNT1

control MSB

LTDATA

I/O

bi-directional data

LTREF

timing reference 5

s at start of every segment active LOW

LTCNT1

LTCNT0

TRANSFER

EXPLANATION

WDAT

write DATA to SAA2022

RDAT

read DATA from SAA2022

WCMD

write Command to SAA2022

RSTAT

read Status from SAA2022

REGISTER

READ/WRITE

NO. OF BITS

COMMENTS

SET0

WRITE

primary settings

SET1

WRITE

secondary settings

CMD

WRITE

microcontroller command

BYTCNT

WRITE

byte counter

RACCNT

WRITE

random access counter

SPDDTY

WRITE

duty cycle for SPEED

AFLEV

WRITE

AUXILIARY flag level

STATUS0

READ

primary status

STATUS1

READ

secondary status

STATUS2

READ

SYSINFO/AUX flags

STATUS3

READ

channel status flags

February 1994

Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

Direct Access

Only one write (CMD) and four read
(STATUS0 to STATUS3) registers can be directly
accessed using the LTCNT lines, all other registers must
be accessed by first programming the command register.

The four Status registers can be read by performing
4 RSTAT transfers within the same LTEN = HIGH period.

Indirect Access

To write to or read from the indirect access registers, a
command must first be sent to the command register. The
transfer of bytes can then occur using WDAT and RDAT
type transfers. It is the responsibility of the microcontroller
to ensure that the transfer type and the last command are
compatible. The same type of transfer can continue until a
new command is sent.

Typical transfers on the microcontroller interface are
shown in Figs 16 to 19.

Fig.16 LT interface timing (1).

MEA715 - 1

LTEN

LTCNT0,1

LTCLK

LTDATA

LTEN

LTCNT0,1

LTCLK

LTDATA

t su3

t h3

t su2

t su4

t su1

th1

t LE

t Lc

t Hc

t h2

t d1

t su2

t su4

t su1

th1

t LE

t Lc

t Hc

t h2

th6

t d2

t h5

transfer of byte from microcontroller (a)

transfer of byte to microcontroller (b)

February 1994

Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

Notes to Fig.16b.

Note

is determined by the longest path from LTEN LOW to LTDATA. This path is via the reset of the internal bit counter.

This reset is only necessary when after the last LTEN = LOW, an exact multiple of 8-bits has not been transferred.
Otherwise t

can be T

= 165 ns less.

DESCRIPTION

TIMING

For the timing figures it is assumed that cycle time T

of MCLK is within the limits 160 ns < T

< 165 ns

The set-up time t

of LTEN, LTCNT, LTCLK and LTDATA to MCLK HIGH

< 40 ns

The hold time t

of LTEN, LTCNT, LTCLK and LTDATA to MCLK HIGH

= 0 ns

The delay time t

of LTDATA from MCLK HIGH is within the limits

0 ns < t

< 30 ns

The delay time t

of LTEN to the 3-state control of LTDATA

0 ns < t

< 50 ns

LTEN LOW time before start data transfer

> 535 ns; note 1

LTCLK LOW time

> 205 ns

LTCLK HIGH time

> 205 ns

LTCNT0/1 set-up time to LTEN HIGH

su1

> 205 ns

LTCNT0/1 hold time from LTEN HIGH

> 205 ns

LTEN set-up time to LTCLK LOW

su2

> 0 ns

LTEN hold time from LTCLK HIGH

> 205 ns

LTCLK set-up time to LTEN HIGH

su4

> 535 ns

LTCLK hold time from LTEN LOW

> 160 ns

LTDATA hold time from LTEN LOW

> 0 ns

LTDATA delay time from LTEN HIGH

< 235 ns

LTDATA delay time from LTCLK HIGH

< 400 ns

LTDATA delay time from LTEN (3-state control)

< 50 ns

February 1994

Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

Table 4

Microcontroller Interface Commands.

CMD

REGISTER

76543210

COMMAND

EXPLANATION

XXXX1000

RDAUX

read AUXILIARY INFO

XXXX1001

RDSYS

read SYSINFO

XXXX1010

WRAUX

write AUXILIARY INFO

XXXX1011

WRSYS

write SYSINFO

XXXX0000

LDSET0

load new settings register 0

XXXX0001

LDSET1

load new settings register 1

XXXX0010

LDAFLEV

load AUX flag threshold level

XXXX0011

LDSPDDTY

load record speed duty cycle

XXXX0101

LDBYTCNT

load byte counter

XXXX0110

LDRACCNT

load random access counter

XXYZ1100

RDDRAC

read data in random access mode from RAM quarter YZ

XXYZ1101

RDFDRAC

read flag and data in random access mode from RAM quarter YZ

XXYZ1110

WRDRAC

write data in random access mode to RAM quarter YZ

XXYZ1111

WRFDRAC

write flag and data in random access mode to RAM quarter YZ

Explanation of settings

SET0 R

EGISTER

ABLE

CSPD

An active HIGH, selects microprocessor control for the
SPEED pulse width modulated servo control signal.

DISRSY

Disable Resyncs active HIGH, is used in after recording.

RECLAB

Record labels active HIGH when in DRAR or DPAR
modes; a label being defined as the bodies of all four AUX
tape blocks in a tape frame which is being written.
This setting has immediate effect and should only be
modified in time segment 1.

ENFREG

In modes DPAP and DPAR Enable Frequency Regulation
active HIGH, allows frequency information from the data
channels to be used with the phase information to
generate the capstan SPEED signal.

ENEFREG

Enable Extended Frequency Regulation active HIGH,
allows extended frequency information from the data
channels to be used with the "normal" frequency
information and the phase information to generate the
capstan SPEED signal, if ENFREG is active.

SET1 R

EGISTER

ABLE

TEST1

This setting is for test only. For use in applications this bit
should be always programmed to logic 0.

PINO1

Pin Output 1, Port expander output for the microcontroller.

TFEMAS

This allows the SAA2022 to become master of the
SB-I

S-bus in modes DPAP and DPAR. In mode DRAR

the device always operates as a slave irrespective of the
settings bit.

Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

February 1994

PORTAB

Portable application active HIGH, allows for the data
channels clock extraction to track fast variations in tape bit
rate. For home use set to inactive.

NOCOS

No Corrected Output Symbol active HIGH, disables the
writing of the error corrected output to the DRAM. It is only
used for debugging.

TEST2

This setting is for test only. For use in applications this bit
should always be programmed to logic 0.

PINO2

Pin output 2, Port expander output for the microcontroller.

PINO3

Pin output 3, Port expander output for the microcontroller.

APE

HASE

ODE

ENFREG = logic 0, ENEFREG = logic 0 and

CSPD = logic 0

In this mode the SAA2022 performs a new calculation to
determine the pulse width for the SPEED signal
approximately once every 21.33 ms, giving a sampling
rate of approximately 46.9 Hz. This calculation is basically
a phase comparison between the incoming main data tape
frame and an internally generated reference. The pulse
duty cycle increases linearly from approximately 9% when
the incoming main data tape frame is 1.65 tape blocks
(8.8 ms) too early up to 91% when the incoming main data
tape frame is 1.65 tape blocks (8.8 ms) too late, in 256
steps (see Fig.20). Outside

2 tape blocks range the pulse

width characteristic overflows and repeats itself forming a
saw-tooth pattern. The SAA2022 has an internal buffer of

8.8 ms inside which the phase information is valid.

APE

REQUENCY

ODE

ENFREG = logic 1, ENEFREG = logic 0 and

CSPD = logic 0

The above description is overridden with frequency
information. That is if the incoming main data bit rate
deviates by more than approximately

6% from the

nominal bit rate of 96000 bits per second, frequency
information is mixed with the phase information. In
between the limits

6% the pulse width is determined as

above.

XTENDED

APE

REQUENCY

ODE

ENFREG = logic 1, ENEFREG = logic 1 and

CSPD = logic 0

In this mode there are 3 regions. This provides a more
gentle transition from frequency plus phase control to
phase only control. Firstly from 0% to

4.5% deviation,

where the operation is as for the tape phase mode.
Secondly from

4.5% to

6% deviation where the

contribution of the frequency information to the servo
information is half of that in the region beyond

deviation. Thirdly when the deviation is greater than

6%,

which is the same as for the tape frequency mode.

ICROCONTROLLER

ODE

CSPD = logic 1

In this mode the pulse width is determined by the
microcontroller programming of the SPDDTY interface
register.

NMODE0, NMODE1

These two bits control the mode change operation in the
SAA2022.

Table 5

NMODE1, NMODE0.

NMODE1

NMODE0

OPERATING MODE

DPAP

DPAR

DRAR

invalid state

February 1994

Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

ETTINGS

EGISTERS

Table 6

SET0.

Table 7

SET1.

SETTING

BIT

DEFAULT

ENEFREG

ENFREG

RECLAB

DISRSY

CSPD

NMODE1

NMODE0

SETTING

BIT

DEFAULT

PINO3

PINO2

TEST2

NOCOS

PORTAB

TFEMAS

PINO1

TEST1

Table 8

SPEED Source.

Notes

"Tape" means that the duty cycle has been calculated
from the playback tape signal.

C" means that the microcontroller programs the

duty cycle via the SPDDTY register in the
microcontroller interface.

"50%" defines that the duty cycle is fixed at 50%.

MODE

CSPD

SPEED

DPAP

tape

(1)

DPAP

(2)

DPAR

tape

(1)

DPAR

(2)

DRAR

50%

(3)

DRAR

(2)

Table 9

Typical Settings.

SETTING BYTE

WHEN

play home machine

play portable machine

record NO LABEL

record LABEL

after record NO LABEL

after record LABEL

Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

February 1994

SNUM0, SNUM1

Time segment number.

URDA

Unreliable Data active HIGH, means that regardless of the
other flag information you cannot use the Data,
SYSINFO or AUX, because they are unreliable, this can
occur as result of a RESYNC, a mode change from mode
DRAR to mode DPAP, or a reset of the SAA2022. When a
resync occurs it resynchronizes with the incoming main
data tape channel information, with a result that for a
period of time, the time that URDA is HIGH all output data
is unusable.

FLAGI

Instantaneous flag active HIGH, indicates that the
AUXILIARY byte that is about to be transferred to the
microcontroller has a flag that is

AFLEV, or that the

SYSINFO byte that is about to be transferred is in error.

AUXFLO

Old Aux Flag active HIGH, indicates that AUXILIARY data
due to be transferred to the microcontroller in the current
segment should not be used.

AUXFLC

AUX Flag active HIGH, indicates that at least one of the
AUXILIARY data bytes due to be transferred to the
microcontroller in the current segment is in error. This
information is provided before the transfer occurs.

SYSFLC

SYSINFO flag active HIGH, indicates that at least one of
the SYSINFO bytes in the current segment is in error. This
information is provided before the transfer occurs.

RFBT

Ready for byte transfer of SYSINFO, AUX or Scratch pad
RAM to or from the microcontroller active HIGH.

MODE0, MODE1

Current mode of operation of the SAA2022.

PAG1, PAG2

Two most significant bits of the modulo 6 internal page
counter, the least significant bit is equal to SNUM0.

PINI

Pin input, Port expander input for the microcontroller.

TEST4

This is for test purposes only.

SLOWTFR

Indicates that LT data transfers of SYSINFO, AUX or
Scratch Pad RAM can only occur at low speed rate. This
occurs only during the second half of time segment 0,
therefore the status bit RFBT must be polled to see if a
transfer is possible. This bit will be HIGH only during the
second half of time segment 0.

FLG 0 to 3

Error flag from the next AUXILIARY/SYSINFO byte which
is to be transferred to the microcontroller.

The flags for SYSINFO bytes have only 2 values, logic 0
which implies that the error corrector finds the bytes are
good and logic 1 which implies that the bytes are in error.

The flags for AUXINFO bytes can have any one of 16
values, 0 to 15, depending on the type of correction. All of
the AUX bytes in the same AUX code word will have the
same flag value. The less reliable the data, the higher the
flag value. It is recommended that any byte with a flag
value of 10 or higher is deemed unreliable.

NFLG 0 to 3

Error flag from the byte after the next AUXILIARY/
SYSINFO byte which will be transferred to the
microcontroller.

CHANS 0 to 7

Error Correction Channel status, which indicates if the
even C1 code words in the 5th block of the segment for
each data tape channel were non correctable. Therefore 1
in every 16 C1 code words from each channel is monitored
to see if the C1 error correcting decoding was successful.

February 1994

Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

Loadable registers

Table 14 AFLev.

AUX Flag threshold level. FLAGI goes HIGH for the AUX bytes whose flags are

AFLev. AUXFLC will go HIGH if the

flags from either code word in the current segment are

AFLev. The default value is 10.

Table 15 SPDDTY.

SPEED duty cycle register. If

CSPD is active, this register determines the duty cycle of the speed signal.

The duty cycle is given by:

0 for 0% duty cycle

128 for 50% duty cycle

255 for 99.6% duty cycle.

The default value is 128.

Table 16 BYTCNT.

Byte counter for SYSINFO, AUX and Scratch Pad RAM
transfers. For SYSINFO:

values 0 to 31 access SYSINFO from the current segment.

values 32 to 63 access SYSINFO from the current +1 segment.

values 64 to 95 access SYSINFO from the current +2 segments.

values 96 to 127 access SYSINFO from the current +3 segments.

In Random access mode the SYSTEM ADDRESS is mapped on to BYTCNT as follows:

Table 17 SYSTEM ADDRES in Random access mode.

Table 18 RAACNT.

BIT

default value

BIT

default value

BIT

default value

BYTCNT

ROW

BIT

default value

Duty cycle

SPDDTY

100

256

------------------------------------------

February 1994

Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

Random Access counter is used for generating addresses in the Random access mode, the SYSTEM ADDRESS is
mapped on to RACCNT as shown in Table 19.

Table 19 SYSTEM address.

RACCNT

ROW

COL

PAG

SYSINFO

AND

AUX

DATA OFFSETS

AUX data consists of 4 blocks of 36 bytes, one block being
transferred in each time segment.

Each tape frame contains 128 bytes of SYSINFO, the
SYSINFO bytes can for convenience, be considered as
being grouped into 4 SYSINFO blocks, with:

SYSBlk0 ==> SI0 to SI31,

SYSBlk1 ==> SI32 to SI63, etc.

In modes DPAP and DPAR SYSINFO transfers may occur
in two ways:

4 blocks of 32 bytes, one block being transferred from
the SAA2022 in each time segment.

1 block of 128 bytes being transferred in time
segment 1.

In mode DRAR SYSINFO must be transferred to the
SAA2022 as 4 blocks of 32 bytes, one block in each
segment.

Figures 26 to 29 show the offsets between the SYSINFO
and AUX and the time segment counter, for the various
modes of operation of the SAA2022.

February 1994

Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

LOCK OFFSETS WITH RESPECT TO TIME SEGMENT

Mode DPAP

SYSBlk = (SNUM + 3) MOD 4;
or read all 4 SYSINFO blocks when SNUM = 1.

If AUX and MAIN were recorded simultaneously then
AUXBlk = (SNUM + 1) MOD 4; else read and interpret
1 AUX block in each time segment.

Mode DRAR

SYSBlk = SNUM;
AUXBlk = (SNUM + 1) MOD 4.

Mode DPAR

SYSBlk = (SNUM + 3) MOD 4;
or read all 4 SYSINFO blocks when SNUM = 1;
AUXBlk = (SNUM + 1) MOD 4.

CRATCH

RAM

The SAA2022 provides the microcontroller with a scratch
pad RAM, which it can use for any purpose. The size of the
scratch pad depends upon the size of the DRAM used and
the locations may be written and read in 8-bit or 12-bit
units.

For a 64 k

4-bit DRAM, the scratch pad is arranged as

6 pages, where each page consists of
7 columns

64 rows. The pages are numbered 0 to 5,

columns 1 to 7 and rows 0 to 63. This gives a total of
(6

64) = 2688 locations.

For a 256 k

4-bit DRAM, the scratch pad is the same as

for the 64 k

4 bit DRAM, plus an additional 3 RAM

quarters, each of 6 pages where each page consists of
8 columns

448 rows. The pages are numbered 0 to 5,

columns 0 to 7 and rows 0 to 431. This gives then a total
of (2688 + (3

448)) = 67200 locations. The RAM

quarter is chosen by the YZ bits of the microcontroller
interface commands.

Use of the scratch pad RAM outside the above ranges will
upset the operation of the device.

As with SYSINFO, AUX transfers can occur at high-speed
at all times except the second half of time segment 0, that
is when the status bit SLOWTFR is HIGH. During this
period the microcontroller must poll the status bit RFBT to
determine when a transfer can occur.

There are two possible methods for addressing the scratch
pad RAM. For random access of the scratch pad the
address of each location is sent by the microcontroller to
the SAA2022 before each location transfer. Alternatively,
the address of the first location can be sent by the
microcontroller before the first location transfer. This will
automatically increment the row for all subsequent
transfers until the end of the column. The RACCNT and
BYTCNT registers are used for addressing the scratch
pad. For the 64 k

4-bit DRAM, and first quarter of

256 k

4 DRAM the mapping of the scratch pad RAM

address onto the RACCNT and BYTCNT registers is
shown in Tables 20 and 21. For the other three-quarters of
the 256 k

4 DRAM the mapping of the scratch pad RAM

address onto the RACCNT and BYTCNT registers is
shown in Tables 22 and 23.

Table 20 RACCNT bit.

Table 21 BYTCNT bit.

RACCNT BIT

BYTCNT BIT

Table 22 RACCNT bit.

Table 23 BYTCNT bit.

RACCNT BIT

BYTCNT BIT

February 1994

Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

Mode changes

Table 24 Possible mode changes for the SAA2022.

CURRENT MODE

NEW MODE

DPAP

DRAR

DPAR

DPAP

YES

DRAR

YES

DPAR

YES

IMING FOR

ODE

HANGES

Mode change DPAP to DRAR

This mode change occurs at the end of the time segment
in which the SAA2022 receives the new settings. Writing
of the first MAIN and AUX data commences at the start of
the time segment 1 which follows two subsequent end of
time segment 3 intervals. The delay to writing to tape is
approximately 222 ms, as shown in Fig.22. If "seamless
appending" is required the new settings should be sent to
the SAA2022 during time segment 2.

Mode change DPAP to DPAR

This mode change occurs at the first end of time segment
2 after the SAA2022 receives the new settings. Output of
AUX to tape begins at the start of the following time
segment 1, (i.e.

85.3 ms after the mode change), as

shown in Fig.23.

Mode change DRAR to DPAP

This mode change occurs at the first end of time
segment 0 after the SAA2022 receives the new setting.
Writing of MAIN and AUX data stops immediately after the
mode change. The time segment jumps back to 0, URDA
goes HIGH and stays HIGH for 5 time segments
(

213.3 ms) after which it goes LOW, as shown in Fig.24.

Mode change DPAR to DPAP

This mode change occurs at the first end of time
segment 0 after the SAA2022 receives the new setting.
The writing of AUX data to tape stops immediately after the
mode change. The first AUX read from tape can be
expected during the following time segment 0 or 1 (i.e.
128 to 170.67 ms after the mode change), as shown in
Fig.25.

February 1994

Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

Input voltage should not exceed 6.5 V unless otherwise specified.

Equivalent to discharging a 100 pF capacitor through a 1.5 k

series resistor.

Equivalent to discharging a 200 pF capacitor through a 0

series resistor.

DC CHARACTERISTICS

= 3.8 to 5.5 V; T

amb

40 to +85

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

supply voltage

0.5

+6.5

input voltage

note 1

0.5

+ 0.5 V

supply current in V

100

supply current in V

100

input current

+10

output current

+20

tot

total power dissipation

500

stg

storage temperature

+150

amb

operating ambient temperature

+85

es1

electrostatic handling

note 2

1500

+1500

es2

electrostatic handling

note 3

+70

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

supply voltage

note 1

3.8

5.0

5.5

supply current

= 5 V

= 3.8 V

Inputs CLK24, TCH0 to TCH7, TAUX, PWRDWN, LTCLK, LTCNT0, LTCNT1, LTEN, PINI and SBMCLK

LOW level input voltage

0.3V

HIGH level input voltage

0.7V

input current

= 0 V; T

amb

= 25

= 5.5 V; T

amb

= 25

February 1994

Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

Note

For applications requiring minimum power dissipation the device may be operated from a nominal +4 V supply.

Input RESET

tLH

threshold voltage
LOW-HIGH

0.8V

tHL

threshold voltage
HIGH-LOW

0.2V

hys

hysteresis

tLH

tHL

1.5

input current

= V

400

Outputs RASN, CASN, WCLOCK and WDATA

LOW level output voltage

3 mA

0.4

HIGH level output voltage

= 3 mA

0.5

Outputs LTREF, WEN, OEN, A0 to A8, SPEED, SPDF, PINO1, PINO3, AZCHK, TEST2, TEST3, MCLK, SBEF,
SBDIR and URDA

LOW level output voltage

2 mA

0.4

HIGH level output voltage

= 2 mA

0.5

Inputs/outputs D0 to D3; with outputs in 3-state

LOW level input voltage

TTL-level

0.8

HIGH level input voltage

TTL-level

input leakage current

= 0 V; T

amb

= 25

= 5.5 V; T

amb

= 25

Inputs/outputs D0 to D3

LOW level output voltage

3 mA

0.4

HIGH level output voltage

= 3 mA

0.5

Inputs/outputs LTDATA, SBCL, SBDA and SBWS; with outputs in 3-state

LOW level input voltage

TTL-level

0.3V

HIGH level input voltage

TTL-level

0.7V

input leakage current

= 0 V; T

amb

= 25

= 5.5 V; T

amb

= 25

Inputs/outputs LTDATA, SBCL, SBDA and SBWS

LOW level output voltage

3mA

0.4

HIGH level output voltage

= 3 mA

0.5

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

February 1994

Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

AC CHARACTERISTICS

= 3.8 to 5.5 V; T

amb

40 to +85

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Clock inputs

input capacitance

CLK24

pulse frequency

24.576

MHz

L-i

pulse width LOW

H-i

pulse width HIGH

SBMCLK

pulse frequency

6.144

12.5

MHz

L-i

pulse width LOW

H-i

pulse width HIGH

Clock outputs

load capacitance

MCLK

pulse frequency

6.144

MHz

L-i

pulse width LOW

H-i

pulse width HIGH

dMFR

delay time from CLK24

note 1

delay time from PWRDWN

Clock inputs

input capacitance

Inputs LTCLK, LTCNT0, LTCNT1, LTEN, RESET, TCH0 to TCH7 and TAUX

suMR

set-up time to MCLK

note 2

hMR

hold time from MCLK

note 2

Input PINI

suMR

set-up time to MCLK

note 1

hMR

hold time from MCLK

note 1

Outputs

load capacitance

February 1994

Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

Outputs A0 to A8, AZCHK, TEST2, LTREF, SBDIR, SBEF, SPDF, SPEED, PINO1 to PINO3, URDA, WCLOCK,
WDATA, OEN and WEN

dMR

delay time from MCLK

note 2

Outputs OEN and WEN

delay time from PWRDWN

Output RASN

dFR

delay time from CLK24

note 1

delay time from PWRDWN

Output CASN

dFR

delay time from CLK24

note 1

delay time from PWRDWN

Inputs/outputs

input capacitance

load capacitance

Inputs/outputs D0 to D3

suCR

set-up time to CASN

note 3

hCR

hold time from CASN

note 3

dMR

delay time from MCLK

note 2

delay time from PWRDWN

Input/output LTDATA

suMR

set-up time to MCLK

note 2

hMR

hold time from MCLK

note 2

dMR

delay time from MCLK

note 2

delay time from PWRDWN

delay time from LTEN

Inputs/outputs SBCL and SBWS

suMR

set-up time to MCLK

note 2

hMR

hold time from MCLK

note 2

dSR

delay time from SBMCLK

note 3

dMR

delay time from MCLK

notes 2 and 5

delay time from PWRDWN

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

February 1994

SOLDERING

Quad flat-packs

Y WAVE

During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150

C within 6 s.

Typical dwell time is 4 s at 250

A modified wave soldering technique is recommended
using two waves (dual-wave), in which, in a turbulent wave
with high upward pressure is followed by a smooth laminar
wave. Using a mildly-activated flux eliminates the need for
removal of corrosive residues in most applications.

Y SOLDER PASTE REFLOW

Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45

EPAIRING SOLDERED JOINTS

(

BY HAND-HELD SOLDERING

IRON OR PULSE-HEATED SOLDER TOOL

)

Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300

C. When using proper tools, all other pins can be

soldered in one operation within 2 to 5 s at between 270
and 320

C. (Pulse-heated soldering is not recommended

for SO packages.)

For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.

February 1994

Philips Semiconductors

Product specification

Tape formatting and error
correction for the DCC system

SAA2022

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress rating only and operation of
the device at these or at any other conditions above those given in the Characteristics sections of the specification is
not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

The Digital Compact Cassette logo is a registered trade mark of Philips Electronics N.V.

Philips Semiconductors

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Telex 35000 phtcnl, Fax. +31-40-724825

SCD28

All rights are reserved. Reproduction in whole or in part is prohibited without the
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use. Publication thereof does not convey nor imply any license under patent- or
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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SAA2022

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SAA2022

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SAA2022