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Электронный компонент: SA5522

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DATA SHEET
Product specification
Supersedes data of 1995 Mar 22
File under Integrated Circuits, IC02
1996 Jan 23
INTEGRATED CIRCUITS
TSA5522
1.4 GHz I
2
C-bus controlled
synthesizer
1996 Jan 23
2
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
TSA5522
FEATURES
Complete 1.4 GHz single chip system
Three PNP band switch buffers (20 mA)
Four bus-controlled bidirectional ports (NPN
open-collector outputs); only one port in 16-pin version
33 V tuning voltage output
In-lock detector
5-step ADC
Mixer-Oscillator (M/O) band switch output
15-bit programmable divider
Programmable reference divider ratio (512, 640
or 1024)
Programmable charge-pump current (50 or 250
A)
Varicap drive disable
I
2
C-bus format
address plus 4 data bytes transmission (write mode)
address plus 1 status byte transmission (read mode)
three independent addresses
Low power and low radiation.
APPLICATIONS
TV tuners and front-ends
VCR tuners.
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
TSA5522M
SSOP20
plastic shrink small outline package; 20 leads; body width 4.4 mm
SOT266-1
TSA5522T
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
1996 Jan 23
3
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
TSA5522
QUICK REFERENCE DATA
Note
1. One band switch buffer ON; I
o
= 20 mA.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
CC1
supply voltage (+5 V)
4.5
-
5.5
V
V
CC2
band switch supply voltage (+12 V)
V
CC1
12
13.5
V
I
CC1
supply current
-
22
30
mA
I
CC2
band switch supply current
note 1
-
27
32
mA
f
RF
RF input frequency
64
-
1400
MHz
V
i(RF)
RF input voltage
f
i
= 80 to 150 MHz
-
25
-
3
dBm
f
i
= 150 to 1000 MHz
-
28
-
3
dBm
f
i
= 1000 to 1400 MHz
-
26
-
3
dBm
f
xtal
crystal oscillator input frequency
-
4
-
MHz
I
o(PNP)
PNP band switch buffers output current
-
20
25
mA
I
o(NPN)
NPN open-collector output current
-
20
25
mA
T
amb
operating ambient temperature
-
20
-
+85
C
T
stg
storage temperature (IC)
-
40
-
+150
C
GENERAL DESCRIPTION (see Fig.1)
The device is a single chip PLL frequency synthesizer
designed for TV and VCR tuning systems. The circuit
consists of a divide-by-eight prescaler with its own
preamplifier, a 15-bit programmable divider, a crystal
oscillator and its programmable reference divider and a
phase/frequency detector combined with a charge-pump
which drives the tuning amplifier, including 33 V output.
Three high-current PNP band switch buffers are provided
for band switching together with four open-collector NPN
outputs (only one open-collector output on 16-pin
devices). These ports can also be used as input ports [one
Analog-to Digital Converter (ADC) and three general
purpose I/O ports (not available on 16-pin devices)]. An
output is provided to control a Philips mixer/oscillator IC in
combination with the PNP buffers state.
Depending on the reference divider ratio (512, 640
or 1024), the phase comparator operates at 3.90625 kHz,
6.25 kHz or 7.8125 kHz with a 4 MHz crystal. The LOCK
detector bit FL is set to logic 1 when the loop is locked and
is read on the SDA line (status byte) during a read
operation.
The ADC is available for digital AFC control. The ADC
code is read during a read operation on the I
2
C-bus. The
ADC input is combined with the port P6. In the TEST
mode, this port is also used as a TEST output for f
ref
and
1
/
2
f
div
(see Table 4).
I
2
C-bus format
Five serial bytes (including address byte) are required to
address the device, select the VCO frequency, program
the ports, set the charge-pump current and the reference
divider ratio. The device has three independent I
2
C-bus
addresses selected by applying a specific voltage on AS
input (see Table 3). The general address C2 is always
valid.
1996 Jan 23
4
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
TSA5522
BLOCK DIAGRAM
Fig.1 Block diagram (SSOP20).
handbook, full pagewidth
PRESCALER
DIVIDE-BY-8
DIVIDER
512/640/1024
XTAL
OSCILLATOR
POWER-ON
RESET
15-BIT
PROGRAMMABLE
DIVIDER
15-BIT
FREQUENCY
REGISTER
7-BIT PORTS
REGISTER
7-BIT CONTROL
REGISTER
DIGITAL
PHASE
COMPARATOR
IN-LOCK
DETECTOR
CHARGE
PUMP
I C -BUS
TRANSCEIVER
2
ADC
COMPARATORS
PNP
BUFFERS
BAND
SWITCH
P0
n.c.
V
P1
P2
P6
P4
P5
P7
LOGIC
OS
CP
BS
CC1
V
GATE
RSA
RSB
RSA,RSB
6
7
1
0
9
8
1
3
1
61
51
4
2
3
28
17
SCL
SDA
AS
18
19
XTAL
RF2
RF1
ref
div
11
CP
12
1
5
4
T2,T1,T0
T2,T1,T0
EE
LOCK
TSA5522
MLD226
CC2
V
f
f
AMP
V
tune
1996 Jan 23
5
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
TSA5522
PINNING
SYMBOL
SO16
SSOP20
DESCRIPTION
V
CC1
1
1
voltage supply (+5 V)
RF1
2
2
RF signal input 1
RF2
3
3
RF signal input 2
BS
4
4
band switch output to mixer/oscillator drive
V
EE
5
5
ground
V
CC2
6
6
voltage supply (+12 V)
n.c.
-
7
not connected
P2
7
8
PNP band switch buffer output 2
P1
8
9
PNP band switch buffer output 1
P0
9
10
PNP band switch buffer output 0
CP
10
11
charge-pump output
V
tune
11
12
tuning voltage output
P6
12
13
NPN open-collector output/ADC input
P7
-
14
NPN open-collector output/comparator input
P5
-
15
NPN open-collector output/comparator input
P4
-
16
NPN open-collector output/comparator input
SCL
13
17
serial clock input
SDA
14
18
serial data input/output
AS
15
19
address selection input
XTAL
16
20
crystal oscillator input
Fig.2 Pin configuration (SO16).
handbook, halfpage
MLD225
TSA5522T
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
RF1
RF2
BS
V
P2
P1
EE
XTAL
AS
SDA
SCL
V
CP
PO
P6
CC1
VCC2
tune
Fig.3 Pin configuration (SSOP20).
handbook, halfpage
TSA5522M
MLD230
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
XTAL
AS
SDA
SCL
P4
P5
P7
P6
CP
RF1
RF2
BS
CC2
V
CC1
V
EE
V
n.c.
P2
P1
P0
Vtune
1996 Jan 23
6
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
TSA5522
FUNCTIONAL DESCRIPTION
The device is controlled via the two-wire I
2
C-bus. For
programming, there is one module address (7 bits) and the
R/W bit for selecting the READ or the WRITE mode.
I
2
C-bus mode
W
RITE MODE
(R/W = 0); see Table 1
Data bytes can be sent to the device after the address
transmission (first byte). Four data bytes are required to
fully program the device. The bus transceiver has an
auto-increment facility which permits the programming of
the device within one single transmission
(address + 4 data bytes).
The device can also be partially programmed providing
that the first data byte following the address is divider
byte 1 (DB1) or control byte (CB). The bits in the data
bytes are defined in Table 1. The first bit of the first data
byte transmitted indicates whether frequency data
(first bit = 0) or control and ports data (first bit = 1) will
follow. Until an I
2
C-bus STOP command is sent by the
controller, additional data bytes can be entered without the
need to re-address the device. The frequency register is
loaded after the 8th clock pulse of the second divider
byte (DB2), the control register is loaded after the 8th clock
pulse of the control byte (CB) and the ports register is
loaded after the 8th clock pulse of the ports byte (PB).
I
2
C-
BUS ADDRESS SELECTION
The module address contains programmable address bits
(MA1 and MA0) which offer the possibility of having
several synthesizers (up to 3) in one system by applying a
specific voltage on the AS input.
The relationship between MA1 and MA0 and the input
voltage on the AS input is given in Table 3.
Table 1
I
2
C-bus data format
Note
1. Not available on 16-pin devices.
Table 2
Description of Table 1
BYTE
MSB
DATA BYTE
LSB
COMMAND
Address byte (ADB)
1
1
0
0
0
MA1
MA0
0
A
Divider byte 1 (DB1)
0
N14
N13
N12
N11
N10
N9
N8
A
Divider byte 2 (DB2)
N7
N6
N5
N4
N3
N2
N1
N0
A
Control byte (CB)
1
CP
T2
T1
T0
RSA
RSB
OS
A
Ports byte (PB)
P7
(1)
P6
P5
(1)
P4
(1)
X
P2
P1
P0
A
SYMBOL
DESCRIPTION
MA1, MA0
programmable address bits (see Table 3)
N14 to N0
programmable divider bits N = N14
2
14
+ N13
2
13
+ ... + N1
2 + N0
CP
charge-pump current; CP = 0 = 50
A; CP = 1 = 250
A
T2 to T0
test bits (see Table 4). For normal operation T2 = 0; T1 = 0; T0 = 1
RSA, RSB
reference divider ratio select bits (see Table 5)
OS
tuning amplifier control bit; for normal operation OS = 0 and tuning voltage is ON; when
OS = 1 tuning voltage is OFF (high impedance)
P2 to P0
PNP band switch buffers control bits
P7 to P4
NPN open collector control bits when P
n
= 0 output n is OFF; when P
n
= 1 output n is ON
X
don't care
1996 Jan 23
7
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
TSA5522
Table 3
Address selection
Table 4
Test bits
Table 5
Ratio select bits
Table 6
Band switch output levels
VOLTAGE APPLIED ON AS
INPUT
MA1
MA2
0 to 0.1V
CC1
0
0
Always valid
0
1
0.4V
CC1
to 0.6V
CC1
1
0
0.9V
CC1
to V
CC1
1
1
T2
T1
T0
DEVICE OPERATION
0
0
1
normal mode
0
1
X
charge-pump is OFF
1
1
0
charge-pump is sinking current
1
1
1
charge-pump is sourcing current
1
0
0
f
ref
is available at LOCK output
1
0
1
1
/
2
f
div
is available at LOCK output
RSA
RSB
REFERENCE DIVIDER
X
0
640
0
1
1024
1
1
512
P2
P1
P0
VOLTAGE
ON BS
OUTPUT
PHILIPS M/O
BAND
0
1
0
0.25 V
band A
1
0
0
0.4V
CC1
band B
0
0
1
0.8V
CC1
band C
R
EAD MODE
; R/W = 1 (see Table 7)
Data can be read from the device by setting the R/W bit to
logic 1. After the slave address has been recognized, the
device generates an acknowledge pulse and the first data
byte (status byte) is transferred on the SDA line (MSB
first). Data is valid on the SDA line during a HIGH level of
the SCL clock signal. A second data byte can be read from
the device if the microcontroller generates an
acknowledge on the SDA line (master acknowledge). End
of transmission will occur if no master acknowledge
occurs. The device will then release the data line to allow
the microcontroller to generate a STOP condition. When
ports P4 to P7 are used as inputs, the corresponding bits
must be logic 0 (high impedance state). The POR flag is
set to logic 1 at power-on. The flag is reset when an
end-of-data is detected by the device (end of a read
sequence). Control of the loop is made possible with the
in-lock flag (FL) which indicates when the loop is locked
(FL = 1).
The bits I2, to I0 represent the status of the I/O ports
P7, P5 and P4 respectively. A logic 0 indicates a LOW
level and a logic 1 indicates a HIGH level
(see "Characteristics").
A built-in ADC is available at pin P6. This converter can be
used to apply AFC information to the microcontroller from
the IF section of the television. The relationship between
the bits A2 to A0 is given in Table 8.
Table 7
READ data format
Notes
1. A = acknowledge.
2. POR = power-on-reset (POR = 1 at power-on).
3. FL = in-lock flag (FL = 1 when loop is locked).
4. I2 to I0 = digital levels for I/O ports P7, P5 and P4 respectively.
5. A2 to A0 = digital outputs of the 5-level ADC.
BYTE
MSB
DATA BYTE
LSB
COMMAND
Address byte (ADB)
1
1
0
0
0
MA1
MA0
1
A
(1)
Status byte (SB)
POR
(2)
FL
(3)
I2
(4)
I1
(4)
I0
(4)
A2
(5)
A1
(5)
A0
(5)
-
1996 Jan 23
8
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
TSA5522
Table 8
ADC levels
Note
1. Accuracy is 0.02V
CC1
.
LIMITING VALUES
In accordance with the Absolute Maximum System (IEC 134)
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling bipolar devices. Every pin withstands the ESD test in
accordance with
MIL-STD-883C category B (2000 V). Every pin withstands the ESD test in accordance with Philips
Semiconductors Machine Model 0
, 200 pF (200 V).
VOLTAGE APPLIED ON
PORT P6
(1)
A2
A1
A0
0.6V
CC1
to 13.5V
1
0
0
0.45V
CC1
to 0.6V
CC1
0
1
1
0.3V
CC1
to 0.45V
CC1
0
1
0
0.15V
CC1
to 0.3V
CC1
0
0
1
0 to 0.15V
CC1
0
0
0
SYMBOL
PARAMETER
MIN.
MAX
UNIT
V
CC1
supply voltage +5 V
-
0.3
6.0
V
V
CC2
supply voltage + 12 V
-
0.3
16
V
V
i(RF)
prescaler input voltage
-
0.3
V
CC1
V
V
o(BS)
band switch output voltage
-
0.3
V
CC1
V
V
o(PNP)
PNP band switch buffer output voltage
-
0.3
V
CC2
V
I
o(PNP)
PNP band switch buffers output current
-
1
25
mA
V
NPN
NPN open-collector output voltage
-
0.3
16
V
I
NPN
NPN open-collector output current
-
1
25
mA
V
o(CP)
charge-pump output voltage
-
0.3
V
CC1
V
V
o(tune)
output tuning voltage
-
0.3
35
V
V
i(SCL)
serial clock input voltage
-
0.3
6.0
V
V
i/o(SDA)
serial data input/output voltage
-
0.3
6.0
V
I
o(SDA)
serial data output current
-
1
5
mA
V
i(AS)
address selection input voltage
-
0.3
V
CC1
V
V
i(xtal)
crystal oscillator input voltage
-
0.3
V
CC1
V
T
stg
storage temperature range (IC)
-
40
+150
C
T
j
maximum junction temperature
-
+150
C
t
sc
short circuit time; every pin to V
CC1
or GND
-
10
s
1996 Jan 23
9
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
TSA5522
THERMAL CHARACTERISTICS
CHARACTERISTICS
V
CC1
= 4.5 to 5.5 V; V
CC2
= V
CC1
to 13.2 V; T
amb
=
-
20 to 85
C; unless otherwise specified; see note 1
SYMBOL
PARAMETER
MAX
UNIT
R
th j-a
thermal resistance from junction to ambient in free air
SO16
110
K/W
SSOP20
120
K/W
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX
UNIT
V
CC1
supply voltage (+5 V)
4.5
-
5.5
V
V
CC2
supply voltage (+12 V)
V
CC1
-
13.5
V
I
CC1
supply current
-
22
30
mA
I
CC2
supply current
One band switch buffer is ON;
I
source
= 20 mA
-
27
32
mA
f
RF
RF input frequency
64
-
1400
MHz
DR
divider ratio
15-bit frequency word
256
-
32767
MHz
Crystal oscillator
f
xtal
crystal oscillator input
frequency
R
xtal
= 25 to 300
3.2
4
4.48
MHz
Z
xtal
crystal oscillator input
impedance (absolute value)
f
i
= 4 MHz
600
1200
-
Prescaler
V
i(RF)
RF input level
V
CC1
= 4.5 to 5.5 V; see Fig.4;
f
i
= 80 to 150 MHz
-
25
-
3
dB
V
CC1
= 4.5 to 5.5 V; see Fig.4;
f
i
= 150 to 1000 MHz
-
28
-
3
dB
V
CC1
= 4.5 to 5.5 V; see Fig.4;
f
i
= 1000 to 1400 MHz
-
26
-
3
dB
PNP band switch buffers outputs
|
I
LO
|
output leakage current
V
CC2
= 13.5 V; V
o
= 0 V
-
10
-
-
A
V
o(sat)
output saturation voltage
I
source
= 20 mA; note 1
-
0.2
0.5
V
NPN open-collector outputs P4, P5, P6 and P7; see note 2
|
I
LO
|
output leakage current
V
CC1
= 5.5 V; V
o
= 13.5 V
-
-
10
A
V
o(sat)
output saturation voltage
I
sink
= 20 mA; note 3
-
0.2
0.5
V
C
OL
allowed capacitive loading
on output pins
V
OL
= 13.5 V
10
nF
Input ports P7, P5 and P4; see note 2
V
IL
LOW level input voltage
-
-
1.5
V
V
IH
HIGH level input voltage
3
-
-
V
AS input (Address Selection)
I
IH(AS)
HIGH level input current
V
AS
= V
CC1
-
-
50
A
1996 Jan 23
10
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
TSA5522
Notes
1. A single PNP band switch buffer is ON.
2. P4, P5 and P7 I/O ports are not available in 16-pin package. In 20-pin package, when a port is active, the collector
voltage must not exceed 6 V.
3. A single NPN open-collector output is ON.
I
IL(AS)
LOW level input current
V
AS
= 0 V
-
50
-
-
A
SCL and SDA inputs
V
IL
LOW level input voltage
-
-
1.5
V
V
IH
HIGH level input voltage
3.0
-
5.5
V
I
IH
HIGH level input current
V
IH
= 5.5 V; V
CC1
= 0 V
-
-
10
A
V
IH
= 5.5 V; V
CC1
= 5.5 V
-
-
10
A
I
IL
LOW level input current
V
IL
= 0 V; V
CC1
= 5.5 V
-
10
-
-
A
f
clk
input clock frequency
-
100
400
kHz
SDA output (I
2
C bus mode)
I
ILO
output leakage current
V
O
= 5.5 V
-
-
10
A
V
o
output voltage
I
sink
= 3 mA
-
-
0.4
A
BS output (M/O band selection)
V
o(BS)
output voltage
band A; I
source
= 20
A
-
0.25
0.5
V
band B; I
source
= 20
A
0.36V
CC1
0.4V
CC1
0.43V
CC1
V
band C; I
source
= 20
A
0.7V
CC1
0.8V
CC1
0.9V
CC1
V
band C; I
source
= 50
A
3.1
-
-
V
Charge-pump output CP
I
ICPH
HIGH charge pump current
(absolute value)
CP = 1
-
250
-
A
I
ICPL
LOW charge pump current
(absolute value)
CP = 0
-
50
-
A
V
o(CP)
output voltage
in-lock; T
amb
= +25
C
-
1.95
-
V
I
LI(off)
off-state leakage current
T2 = 0; T1 = 1
-
5
1
15
nA
Tuning voltage output V
tune
I
LO(off)
leakage current when
switched-off
OS = 1; V
tune
= 33 V
-
-
10
A
V
o
output voltage when the
loop is closed
OS = 0; T2 = 0; T1 = 0; T0 = 1;
R
L
= 27 k
;
V
tune
= 33 V
0.4
-
32.6
V
V
ripple(p-p)
acceptable ripple voltage
on V
CC1
(peak-to-peak
value)
f
ripple
= 300 Hz to 300 kHz
-
-
30
mV
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX
UNIT
1996 Jan 23
11
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
TSA5522
Fig.4 Prescaler typical input sensitivity curve.
handbook, full pagewidth
600
12
48
0
200
400
1400
1600
800
1000
1200
MLD227
36
24
12
0
power
(dBm)
f (MHz)
i
1996 Jan 23
12
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
TSA5522
INTERNAL PIN CONFIGURATION
handbook, full pagewidth
P2
P1
V
P0
down
up
CC1
n.c.
EE
V
BS
RF2
RF1
to presscaler
divider
Vref
V
XTAL
3 k
1 k
1 k
1 k
300
F
AS
AS
SDA
SCL
P7
control
CP
V
MLD228
V
CC1
V
CC1
P6
Vtune
V
CC1
V
CC1
P4
V
CC1
V
CC1
V
CC1
V
CC1
V
CC1
V
CC1
V
CC1
V
CC1
V
CC1
V
CC1
P5
V
CC1
V
X4
CC1
CC1
CC2
V
CC2
V
CC2
V
CC2
TSA5522
Fig.5 Internal pin configuration.
1996 Jan 23
13
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
TSA5522
APPLICATION INFORMATION
Tuning amplifier
The tuning amplifier is capable of driving the varicap
voltage without an external transistor. The tuning voltage
output must be connected to an external load of 27 k
which is connected to the tuning voltage supply rail.
Figure 6 shows a possible loop filter. The component
values depend on the oscillator characteristics and the
selected reference frequency.
Crystal oscillator
The crystal oscillator uses a 4 MHz crystal connected in
series with an 18 pF capacitor thereby operating in the
series resonance mode. Connecting the oscillator to the
supply voltage is preferred, but it can, however, also be
connected to ground.
Fig.6 Typical application (SO16).
handbook, full pagewidth
P0
CP
P6
SCL
SDA
AS
XTAL
V
33 V
UHF
VHF1
VHF3
12 V
BS
RF
RF
5 V
10 nF
1 nF
1 nF
P1
P2
V
V
BS
RF2
RF1
V
CC2
CC1
EE
P6
SCL
39 nF
180 nF
SDA
AS
TSA5522T
tune
22 k
27 k
4 MHz
18 pF
MLD229
Vtune
1996 Jan 23
14
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
TSA5522
Flock flag (FL) definition
When the LOCK output is LOW the maximum frequency
deviation
(
f) from stable frequency can be expressed as
follows:
where:
K
vco
= oscillator slope Hz/V
I
CP
= charge-pump current (A)
K
O
= 4
10E6
C1, C2 = loop filter capacitors.
In the application:
K
VCO
= 16 MHz/V (UHF band)
I
CP
= 250
A
C1 = 180 nF, C2 = 39 nF
f =
31.2 kHz.
f
K
VCO
K
O
--------------
I
CP
C1
C2
+
(
)
C1
C2
(
)
-----------------------------
=
Fig.7 Loop filter.
handbook, halfpage
MBE331
C1
R
C2
Table 9
LOCK output / FL flag setting
DESCRIPTION
CONDITION
MIN.
MAX.
UNIT
Time span between actual phase lock and LOCK bit is LOW
(or FL flag = 1)
RSA = 1; RSB = 1
1024
1152
s
RSA = 1; RSB = 1
2048
2304
s
RSB = 0
1280
1440
s
Time span between the loop losing lock and LOCK bit is
HIGH or (FL flag = 0)
0
300
s
1996 Jan 23
15
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
TSA5522
PACKAGE OUTLINES
X
w
M
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v
M
A
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT
A
max.
A
1
A
2
A
3
b
p
c
D
(1)
E
(1)
(1)
e
H
E
L
L
p
Q
Z
y
w
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
0.7
0.6
0.7
0.3
8
0
o
o
0.25
0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
1.0
0.4
SOT109-1
91-08-13
95-01-23
076E07S
MS-012AC
0.069
0.0098
0.0039
0.057
0.049
0.01
0.019
0.014
0.0098
0.0075
0.39
0.38
0.16
0.15
0.050
1.05
0.041
0.24
0.23
0.028
0.020
0.028
0.012
0.01
0.25
0.01
0.004
0.039
0.016
0
2.5
5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
1996 Jan 23
16
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
TSA5522
UNIT
A
1
A
2
A
3
b
p
c
D
(1)
E
(1)
(1)
e
H
E
L
L
p
Q
Z
y
w
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
0.15
0
1.4
1.2
0.32
0.20
0.20
0.13
6.6
6.4
4.5
4.3
0.65
1.0
0.2
6.6
6.2
0.65
0.45
0.48
0.18
10
0
o
o
0.13
0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
0.75
0.45
SOT266-1
90-04-05
95-02-25
w
M
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v
M
A
X
(A )
3
A
y
0.25
1
10
20
11
pin 1 index
0
2.5
5 mm
scale
SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm
SOT266-1
A
max.
1.5
1996 Jan 23
17
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
TSA5522
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
"IC Package Databook" (order code 9398 652 90011).
Reflow soldering
Reflow soldering techniques are suitable for all SO and
SSOP packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250
C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45
C.
Wave soldering
SO
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
The longitudinal axis of the package footprint must be
parallel to the solder flow.
The package footprint must incorporate solder thieves at
the downstream end.
SSOP
Wave soldering is not recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
If wave soldering cannot be avoided, the following
conditions must be observed:
A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
The longitudinal axis of the package footprint must
be parallel to the solder flow and must incorporate
solder thieves at the downstream end.
Even with these conditions, only consider wave
soldering SSOP packages that have a body width of
4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1)
.
M
ETHOD
(SO
AND
SSOP)
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260
C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150
C within
6 seconds. Typical dwell time is 4 seconds at 250
C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300
C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320
C.
1996 Jan 23
18
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
TSA5522
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I
2
C COMPONENTS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Purchase of Philips I
2
C components conveys a license under the Philips' I
2
C patent to use the
components in the I
2
C system provided the system conforms to the I
2
C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1996 Jan 23
19
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
TSA5522
NOTES
Philips Semiconductors a worldwide company
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SCDS47
Philips Electronics N.V. 1996
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