Philips Semiconductors

Product data

PCA9531

8-bit I

C LED dimmer

2003 Nov 10

FEATURES

Eight LED drivers (on, off, flashing at a programmable rate)

Two selectable, fully programmable blink rates (frequency and
duty cycle) between 0.625 and 160 Hz (1.6 and 6.25 milliseconds)

256 brightness steps

Input/outputs not used as LED drivers can be used as regular
GPIOs

Internal oscillator requires no external components

C interface logic compatible with SMBus

Internal power-on reset

Noise filter on SCL/SDA inputs

Active low reset input

Eight open drain outputs directly drive LEDs to 25 mA

Edge rate control on outputs

No glitch on power-up

Supports hot insertion

Low stand-by current

Operating power supply voltage range of 2.3 V to 5.5 V

0 to 400 kHz clock frequency

ESD protection exceeds 2000 V HBM per JESD22-A114,
150 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101

Latch-up testing is done to JEDEC Standard JESD78 which
exceeds 100 mA

Package offer: SO16, TSSOP16, HVQFN16

DESCRIPTION

The PCA9531 is an 8-bit I

C & SMBus I/O expander optimized for

dimming LEDs in 256 discrete steps for Red/Green/Blue (RGB)
color mixing and back light applications.

The PCA9531 contains an internal oscillator with two user
programmable blink rates and duty cycles coupled to the output
PWM. The LED brightness is controlled by setting the blink rate high
enough (> 100 Hz) that the blinking can not be seen and then using
the duty cycle to vary the amount of time the LED is on and thus the
average current through the LED.

The initial setup sequence programs the two blink rates/duty cycles
for each individual PWM. From then on, only one command from the
bus master is required to turn individual LEDs ON, OFF, BLINK
RATE 1 or BLINK RATE 2. Based on the programmed frequency
and duty cycle, BLINK RATE 1 and BLINK RATE 2 will cause the
LEDs to appear at a different brightness or blink at periods up to 1.6
second. The open drain outputs directly drive the LEDs with
maximum output sink current of 25 mA per bit and 100 mA per
package.

To blink LEDs at periods greater than 1.6 second the bus master
(MCU, MPU, DSP, chipset, etc.) must send repeated commands to
turn the LED on and off as is currently done when using normal I/O
Expanders like the Philips PCF8574 or PCA9554. Any bits not used
for controlling the LEDs can be used for General Purpose Parallel
Input/Output (GPIO) expansion which provides a simple solution
when additional I/O is needed for ACPI power switches, sensors,
push-buttons, alarm monitoring, fans, etc.

The active low hardware reset pin (RESET) and Power On Reset
(POR) initializes the registers to their default state causing the bits
to be set high (LED off).

Three hardware address pins on the PCA9531 allow eight devices
to operate on the same bus.

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

TOPSIDE MARK

DRAWING NUMBER

16-pin plastic SO

-40 to +85

PCA9531D

SOT109-1

16-pin plastic TSSOP

-40 to +85

PCA9531PW

PCA9531

SOT403-1

16-pin plastic HVQFN

-40 to +85

PCA9531BS

9531

SOT629-1

Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
I

C is a trademark of Philips Semiconductors Corporation.

Philips Semiconductors

Product data

PCA9531

8-bit I

C LED dimmer

2003 Nov 10

PIN CONFIGURATION -- SO, TSSOP

SW02039

LED0

LED1

LED2

LED3

SDA

SCL

RESET

LED7

LED6

LED5

LED4

Figure 1. Pin configuration -- SO, TSSOP

PIN CONFIGURATION -- HVQFN

su01667

TOP VIEW

LED0

LED1

LED2

LED3

LED4

LED5

RESET

LED6

LED7

SDA

SCL

Figure 2. Pin configuration -- HVQFN

PIN DESCRIPTION

SO, TSSOP

PIN

NUMBER

HVQFN

PIN

NUMBER

SYMBOL

FUNCTION

Address input 0

Address input 1

Address input 2

4, 5, 6, 7

2, 3, 4, 5

LED0-3

LED drivers 0-3

Supply ground

9, 10, 11, 12

7, 8, 9, 10

LED4-7

LED drivers 4-7

RESET

Active low reset input

SCL

Serial clock line

SDA

Serial data line

Supply voltage

Philips Semiconductors

Product data

PCA9531

8-bit I

C LED dimmer

2003 Nov 10

DEVICE ADDRESSING

Following a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9531 is
shown in Figure 4. To conserve power, no internal pullup resistors
are incorporated on the hardware selectable address pins and they
must be pulled HIGH or LOW.

SLAVE ADDRESS

su01420

FIXED

HARDWARE SELECTABLE

R/W

Figure 4. Slave address

The last bit of the address byte defines the operation to be
performed. When set to logic 1 a read is selected while a logic 0
selects a write operation.

CONTROL REGISTER

Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9531 which will be stored
in the Control Register.

B2 B1 B0

SW01034

AUTO-INCREMENT FLAG

RESET STATE: 00h

Figure 5. Control register

CONTROL

REGISTER DEFINITION

REGISTER

NAME

TYPE

INPUT

READ

INPUT

PSC0

READ/

WRITE

FREQUENCY

PRESCALER 0

PWM0

READ/

WRITE

PWM

PSC1

READ/

WRITE

FREQUENCY

PRESCALER 1

PWM1

READ/

WRITE

PWM

LS0

READ/

WRITE

LED0-LED3

SELECTOR

LS1

READ/

WRITE

LED4-LED7

SELECTOR

REGISTER DESCRIPTION

The lowest 3 bits are used as a pointer to determine which register
will be accessed.

If the auto-increment flag is set, the three low order bits of the
Control Register are automatically incremented after a read or write.
This allows the user to program the registers sequentially. The
contents of these bits will rollover to `000' after the last register is
accessed.

When auto-increment flag is set (AI = 1) and a read sequence is
initiated, the sequence must start by reading a register different from
the input register (B2 B1 B0

0 0 0).

Only the 3 least significant bits are affected by the AI flag.

Unused bits must be programmed with zeroes.

INPUT -- INPUT REGISTER

bit

Default

The INPUT register reflects the state of the device pins. Writes to
this register will be acknowledged but will have no effect.

PSC0 -- FREQUENCY PRESCALER 0

bit

default

PSC0 is used to program the period of the PWM output.

The period of BLINK0

(PSC0

)

152

PWM0 -- PWM REGISTER 0

bit

default

The PWM0 register determines the duty cycle of BLINK0. The
outputs are LOW (LED on) when the count is less than the value in
PWM0 and HIGH (LED off) when it is greater. If PWM0 is
programmed with 00h, then the PWM0 output is always HIGH (LED
off).

The duty cycle of BLINK0 is:

PWM0

256

PSC1 -- FREQUENCY PRESCALER 1

bit

default

PSC1 is used to program the period of PWM output.

The period of BLINK1

(PSC1

)

152

PWM1 -- PWM REGISTER 1

bit

default

The PWM1 register determines the duty cycle of BLINK1. The
outputs are LOW (LED on) when the count is less than the value in
PWM1 and HIGH (LED off) when it is greater. If PWM1 is
programmed with 00h, then the PWM1 output is always HIGH (LED
off) .

The duty cycle of BLINK1 is:

PWM1

256

LS0 -- LED0-3 SELECTOR

LED 3

LED 2

LED 1

LED 0

bit

default

LS1 -- LED4-7 SELECTOR

LED 7

LED 6

LED 5

LED 4

bit

default

The LSx LED select registers determine the source of the LED data.

00 = Output is set Hi-Z (LED off - default)
01 = Output is set low (LED on)
10 = Output blinks at PWM0 rate
11 = Output blinks at PWM1 rate

Philips Semiconductors

Product data

PCA9531

8-bit I

C LED dimmer

2003 Nov 10

POWER-ON RESET

When power is applied to V

, an internal Power On Reset holds

the PCA9531 in a reset state until V

has reached V

POR

. At this

point, the reset condition is released and the PCA9531 registers are
initialized to their default states, all the outputs in the off state.

EXTERNAL RESET

A reset can be accomplished by holding the RESET pin low for a
minimum of t

. The PCA9531 registers and I

C state machine will

be held in their default state until the RESET input is once again
high.

This input requires a pull-up resistor to V

CHARACTERISTICS OF THE I

C-BUS

The I

C-bus is for 2-way, 2-line communication between different ICs

or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.

Bit transfer

One data bit is transferred during each clock pulse. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (see Figure 6).

SDA

SCL

SW00363

data line

stable;

data valid

change

of data

allowed

Figure 6. Bit transfer

Start and stop conditions

Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 7).

System configuration

A device generating a message is a transmitter: a device receiving
is the receiver. The device that controls the message is the master
and the devices which are controlled by the master are the slaves
(see Figure 8).

SDA

SCL

SW00365

SDA

SCL

START condition

STOP condition

Figure 7. Definition of start and stop conditions

MASTER
TRANSMITTER/
RECEIVER

SLAVE
RECEIVER

SLAVE
TRANSMITTER/
RECEIVER

MASTER
TRANSMITTER

MASTER
TRANSMITTER/
RECEIVER

SDA

SCL

SW00366

MULTIPLEXER

SLAVE

Figure 8. System configuration

Philips Semiconductors

Product data

PCA9531

8-bit I

C LED dimmer

2003 Nov 10

Acknowledge

The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.

DATA OUTPUT

BY TRANSMITTER

SCL FROM

MASTER

SW00368

DATA OUTPUT

BY RECEIVER

START condition

clock pulse for
acknowledgement

acknowledge

not acknowledge

Figure 9. Acknowledgement on the I

C-bus

Philips Semiconductors

Product data

PCA9531

8-bit I

C LED dimmer

2003 Nov 10

Bus transactions

SCL

WRITE TO

REGISTER

DATA OUT

FROM PORT

SDA

DATA 1

slave address

data to register

start condition

R/W

acknowledge
from slave

DATA 1 VALID

SW01081

command byte

Figure 10. WRITE to register

acknowledge
from slave

R/W

acknowledge
from slave

acknowledge
from master

DATA

R/W

first byte

at this moment master-transmitter
becomes master-receiver and
slave-receiver becomes
slave-transmitter

last byte

SW01082

no acknowledge
from master

slave address

data from register

slave address

auto-increment
register address
if AI = 1

B2 B1

Figure 11. READ from register

READ FROM

PORT

DATA INTO

PORT

SDA

DATA 1

DATA 4

slave address

data from port

start condition

R/W

acknowledge
from slave

acknowledge
from master

stop
condition

DATA 4

DATA 2

DATA 3

SW01084

no acknowledge
from master

DATA 1

NOTES:
1. This figure assumes the command byte has previously been programmed with 00h.

Figure 12. READ input port register

Philips Semiconductors

Product data

PCA9531

8-bit I

C LED dimmer

2003 Nov 10

APPLICATION DATA

PCA9531

SDA

SCL

RESET

C/SMBus MASTER

SW02041

SDA

SCL

LED0

LED1

LED2

LED3

LED4

LED5

LED6

LED7

5 V

Note: LED0 to LED5 are used as LED drivers

LED6 and LED7 are used as regular GPIOs.

GPIO

Figure 13. Typical application

Minimizing I

when the I/O is used to control LEDs

When the I/Os are used to control LEDs, they are normally connected to V

through a resistor as shown in Figure 13. Since the LED acts as a

diode, when the LED is off the I/O V

is about 1.2 V less than V

. The supply current , I

, increases as V

becomes lower than V

and is

specified as

in the DC characteristics table.

Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or
equal to V

when the LED is off. Figure 14 shows a high value resistor in parallel with the LED. Figure 15 shows V

less than the LED supply

voltage by at least 1.2 V. Both of these methods maintain the I/O V

at or above V

and prevents additional supply current consumption when

the LED is off.

LEDx

LED

100 k

SW02086

Figure 14. High value resistor in parallel with the LED

3.3 V

LEDx

LED

SW02087

5 V

Figure 15. Device supplied by a lower voltage

Philips Semiconductors

Product data

PCA9531

8-bit I

C LED dimmer

2003 Nov 10

ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134)

SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

UNIT

Supply voltage

-0.5

6.0

I/O

DC voltage on an I/O

- 0.5

5.5

I/O

DC output current on an I/O

+25

Supply current

200

tot

Total power dissipation

400

stg

Storage temperature range

-65

+150

amb

Operating ambient temperature

-40

+85

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take
precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under "Handling MOS devices".

DC CHARACTERISTICS

= 2.3 to 5.5 V; V

= 0 V; T

amb

= -40 to +85

C; unless otherwise specified. TYP at 3.3 V and 25

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Supplies

Supply voltage

2.3

5.5

Supply current

Operating mode; V

= 5.5 V;

= V

or V

; f

SCL

= 100 kHz

350

500

stb

Standby current

Standby mode; V

= 5.5 V;

= V

or V

; f

SCL

= 0 kHz

1.9

3.0

Additional standby current

Standby mode; V

= 5.5 V; Every

LED I/O at V

= 4.3 V; f

SCL

= 0 kHz

800

POR

Power-on reset voltage

No load; V

= V

or V

1.7

2.2

Input SCL; input/output SDA

LOW level input voltage

-0.5

0.3 V

HIGH level input voltage

0.7 V

5.5

LOW level output current

= 0.4V

6.5

Leakage current

= V

-1

Input capacitance

= V

3.7

I/Os

LOW level input voltage

-0.5

0.8

HIGH level input voltage

2.0

5.5

= 0.4 V; V

= 2.3 V; Note 1

= 0.4 V; V

= 3.0 V; Note 1

= 0.4 V; V

= 5.0 V; Note 1

LOW level output current

= 0.7 V; V

= 2.3 V; Note 1

= 0.7 V; V

= 3.0 V; Note 1

= 0.7 V; V

= 5.0 V; Note 1

Input leakage current

= 3.6 V; V

= 0 or V

-1

Input/output capacitance

2.5

Select Inputs A0, A1, A2 / RESET

LOW level input voltage

-0.5

0.8

HIGH level input voltage; A0 / RESET

2.0

5.5

HIGH level input voltage; A1 / A2

2.0

+ 0.5

Input leakage current

-1

Input capacitance

= V

2.3

NOTE:
1. Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.

Philips Semiconductors

Product data

PCA9531

8-bit I

C LED dimmer

2003 Nov 10

AC SPECIFICATIONS

SYMBOL

PARAMETER

STANDARD MODE I

BUS

FAST MODE

C BUS

UNITS

SYMBOL

PARAMETER

MIN

MAX

MIN

MAX

UNITS

SCL

Operating frequency

100

400

kHz

BUF

Bus free time between STOP and START conditions

4.7

1.3

HD;STA

Hold time after (repeated) START condition

4.0

0.6

SU;STA

Repeated START condition setup time

4.7

0.6

SU;STO

Setup time for STOP condition

4.0

0.6

HD;DAT

Data in hold time

VD;ACK

Valid time for ACK condition

600

VD;DAT

(L)

Data out valid time

600

VD;DAT

(H)

Data out valid time

1500

600

SU;DAT

Data setup time

250

100

LOW

Clock LOW period

4.7

1.3

HIGH

Clock HIGH period

4.0

0.6

Clock/Data fall time

300

20 + 0.1 C

300

Clock/Data rise time

1000

20 + 0.1 C

300

Pulse width of spikes that must be suppressed by the
input filters

Port Timing

Output data valid

200

Input data setup time

100

Input data hold time

Reset

Reset pulse width

REC

Reset recovery time

RESET

4,5

Time to reset

400

NOTES:
1. C

= total capacitance of one bus line in pF.

2. t

VD;ACK

= time for Acknowledgement signal from SCL low to SDA (out) low.

3. t

VD;DAT

= minimum time for SDA data out to be valid following SCL low.

4. Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions.
5. Upon reset, the full delay will be the sum of t

RESET

and the RC time constant of the SDA bus.

Philips Semiconductors

Product data

PCA9531

8-bit I

C LED dimmer

2003 Nov 10

Purchase of Philips I

C components conveys a license under the Philips' I

C patent

to use the components in the I

C system provided the system conforms to the

C specifications defined by Philips. This specification can be ordered using the

code 9398 393 40011.

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described
or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.

Contact information

For additional information please visit
http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.

Koninklijke Philips Electronics N.V. 2002

Date of release: 11-03

Document order number:

9397 750 12292

Philips
Semiconductors

Data sheet status

[1]

Objective data

Preliminary data

Product data

Product
status

[2] [3]

Development

Qualification

Production

Definitions

This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.

This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

Data sheet status

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Level

III

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