DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT191
Presettable synchronous 4-bit
binary up/down counter
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990
2
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT191
FEATURES
Synchronous reversible counting
Asynchronous parallel load
Count enable control for synchronous expansion
Single up/down control input
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT191 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT191 are asynchronously presettable 4-bit
binary up/down counters. They contain four master/slave
flip-flops with internal gating and steering logic to provide
asynchronous preset and synchronous count-up and
count-down operation.
Asynchronous parallel load capability permits the counter
to be preset to any desired number. Information present on
the parallel data inputs (D
0
to D
3
) is loaded into the counter
and appears on the outputs when the parallel load (PL)
input is LOW. As indicated in the function table, this
operation overrides the counting function.
Counting is inhibited by a HIGH level on the count enable
(CE) input. When CE is LOW internal state changes are
initiated synchronously by the LOW-to-HIGH transition of
the clock input. The up/down (U/D) input signal determines
the direction of counting as indicated in the function table.
The CE input may go LOW when the clock is in either
state, however, the LOW-to-HIGH CE transition must
occur only when the clock is HIGH. Also, the U/D input
should be changed only when either CE or CP is HIGH.
Overflow/underflow indications are provided by two types
of outputs, the terminal count (TC) and ripple clock (RC).
The TC output is normally LOW and goes HIGH when a
circuit reaches zero in the count-down mode or reaches
"15" in the count-up-mode. The TC output will remain
HIGH until a state change occurs, either by counting or
presetting, or until U/D is changed. Do not use the TC
output as a clock signal because it is subject to decoding
spikes. The TC signal is used internally to enable the
RC output. When TC is HIGH and CE is LOW, the RC
output follows the clock pulse (CP). This feature simplifies
the design of multistage counters as shown in Figs 5
and 6.
In Fig.5, each RC output is used as the clock input to the
next higher stage. It is only necessary to inhibit the first
stage to prevent counting in all stages, since a HIGH on
CE inhibits the RC output pulse as indicated in the function
table. The timing skew between state changes in the first
and last stages is represented by the cumulative delay of
the clock as it ripples through the preceding stages. This
can be a disadvantage of this configuration in some
applications.
Fig.6 shows a method of causing state changes to occur
simultaneously in all stages. The RC outputs propagate
the carry/borrow signals in ripple fashion and all clock
inputs are driven in parallel. In this configuration the
duration of the clock LOW state must be long enough to
allow the negative-going edge of the carry/borrow signal to
ripple through to the last stage before the clock goes
HIGH. Since the RC output of any package goes HIGH
shortly after its CP input goes HIGH there is no such
restriction on the HIGH-state duration of the clock.
In Fig.7, the configuration shown avoids ripple delays and
their associated restrictions. Combining the TC signals
from all the preceding stages forms the CE input for a
given stage. An enable must be included in each carry
gate in order to inhibit counting. The TC output of a given
stage it not affected by its own CE signal therefore the
simple inhibit scheme of Figs 5 and 6 does not apply.
December 1990
3
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT191
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
V
CC
2
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V
ORDERING INFORMATION
See
"74HC/HCT/HCU/HCMOS Logic Package Information"
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay CP to Q
n
C
L
= 15 pF; V
CC
= 5 V
22
22
ns
f
max
maximum clock frequency
36
36
MHz
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per package
notes 1 and 2
31
33
pF
December 1990
4
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT191
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
3, 2, 6, 7
Q
0
to Q
3
flip-flop outputs
4
CE
count enable input (active LOW)
5
U/D
up/down input
8
GND
ground (0 V)
11
PL
parallel load input (active LOW)
12
TC
terminal count output
13
RC
ripple clock output (active LOW)
14
CP
clock input (LOW-to-HIGH, edge triggered)
15, 1, 10, 9
D
0
to D
3
data inputs
16
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
5
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT191
FUNCTION TABLE
TC AND RC FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
I
= LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
X = don't care
= LOW-to-HIGH CP transition
= one LOW level pulse
= TC goes LOW on a LOW-to-HIGH CP transition
OPERATING MODE
INPUTS
OUTPUTS
PL
U/D
CE
CP
D
n
Q
n
parallel load
L
L
X
X
X
X
X
X
L
H
L
H
count up
H
L
I
X
count up
count down
H
H
I
X
count down
hold (do nothing)
H
X
H
X
X
no change
INPUTS
TERMINAL COUNT STATE
OUTPUTS
U/D
CE
CP
Q
0
Q
1
Q
2
Q
3
TC
RC
H
L
L
L
H
H
H
H
L
H
H
L
X
X
X
X
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
L
H
L
H
H
H
H
H
Fig.4 Functional diagram.
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