Document Outline
- FEATURES
- GENERAL DESCRIPTION
- QUICK REFERENCE DATA
- ORDERING INFORMATION
- PIN DESCRIPTION
- FUNCTION TABLE
- DC CHARACTERISTICS
- AC CHARACTERISTICS
- AC WAVEFORMS
- PACKAGE OUTLINES
DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT107
Dual JK flip-flop with reset;
negative-edge trigger
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990
2
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74HC/HCT107
FEATURES
Output capability: standard
I
CC
category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT107 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT107 are dual negative-edge triggered
JK-type flip-flops featuring individual J, K, clock (nCP) and
reset (nR) inputs; also complementary Q and Q outputs.
The J and K inputs must be stable one set-up time prior to
the HIGH-to-LOW clock transition for predictable
operation.
The reset (nR) is an asynchronous active LOW input.
When LOW, it overrides the clock and data inputs, forcing
the Q output LOW and the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
V
CC
2
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V.
ORDERING INFORMATION
See
"74HC/HCT/HCU/HCMOS Logic Package Information"
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
C
L
= 15 pF;
V
CC
= 5 V
nCP to nQ
16
16
ns
nCP to nQ
16
18
ns
nR to nQ, nQ
16
17
ns
f
max
maximum clock frequency
78
73
MHz
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation
capacitance per flip-flop
notes 1 and 2
30
30
pF
December 1990
3
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74HC/HCT107
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1, 8, 4, 11
1J, 2J, 1K, 2K
synchronous inputs; flip-flops 1 and 2
2, 6
1Q, 2Q
complement flip-flop outputs
3, 5
1Q, 2Q
true flip-flop outputs
7
GND
ground (0 V)
12, 9
1CP, 2CP
clock input (HIGH-to-LOW, edge-triggered)
13, 10
1R, 2R
asynchronous reset inputs (active LOW)
14
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
4
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74HC/HCT107
Fig.4 Functional diagram.
Fig.5 Logic diagram (one flip-flop).
FUNCTION TABLE
Note
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW CP
transition
X = don't care
= HIGH-to-LOW CP transition
OPERATING MODE
INPUTS
OUTPUTS
nR
nCP
J
K
Q
Q
asynchronous reset
L
X
X
X
L
H
toggle
H
h
h
q
q
load "0" (reset)
H
I
h
L
H
load "1" (set)
H
h
I
H
L
hold "no change"
H
I
I
q
q
December 1990
5
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74HC/HCT107
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Output capability: standard
I
CC
category: flip-flops
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
C)
TEST CONDITIONS
74HC
UNIT
V
CC
(V)
WAVEFORMS
+
25
-
40 to
+
85
-
40 to
+
125
min.
typ.
max. min.
max.
min.
max.
t
PHL
/ t
PLH
propagation delay
nCP to nQ
52
19
15
160
32
27
200
40
34
240
48
41
ns
2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
nCP to nQ
52
19
15
160
32
27
200
40
34
240
48
41
ns
2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
nR to nQ, nQ
52
19
15
155
31
26
195
39
33
235
47
40
ns
2.0
4.5
6.0
Fig.7
t
THL
/ t
TLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.6
t
W
clock pulse width
HIGH or LOW
80
16
14
22
8
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.6
t
W
reset pulse width
LOW
80
16
14
22
8
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.7
t
rem
removal time
nR to nCP
60
12
10
19
7
6
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.7
t
su
set-up time
nJ, nK to nCP
100
20
17
22
8
6
125
25
21
150
30
26
ns
2.0
4.5
6.0
Fig.6
t
h
hold time
nJ, nK to nCP
3
3
3
-
6
-
2
-
2
3
3
3
3
3
3
ns
2.0
4.5
6.0
Fig.6
f
max
maximum clock pulse
frequency
6.0
30
35
23
70
85
4.8
24
28
4.0
20
24
MHz
2.0
4.5
6.0
Fig.6
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