Philips
Semiconductors
74F273A
Octal D flip-flop
Product specification
IC15 Data Handbook
1996 Mar 12
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74F273A
Octal D flipflop
2
1996 Mar 12
8530066 16555
FEATURES
High impedance inputs for reduced loading
(20
A in Low and High states)
Ideal buffer for MOS microprocessor or memory
Eight edgetriggered Dtype flipflops
Buffered common clock
Buffered asynchronous Master Reset
See 74F377A for clock enable version
See 74F373 for transparent latch version
See 74F374 for 3State version
DESCRIPTION
The 74F273 has eight edgetriggered Dtype flipflops with
individual D inputs and Q outputs. The common buffered Clock (CP)
and Master Reset (MR) inputs load and reset (clear) all flipflops
simultaneously.
The register is fully edgetriggered. The state of each D input, one
setup time before the LowtoHigh clock transition, is transferred to
the corresponding flipflop's Q output.
All outputs will be forced Low independently of Clock or Data inputs
by a Low voltage level on the MR input. The device is useful for
applications where the true output only is required and the CP and
MR are common to all elements.
TYPE
TYPICAL
f
MAX
TYPICAL SUPPLY CURRENT
(TOTAL)
74F273A
170MHz
25mA
ORDERING INFORMATION
PACKAGES
COMMERCIAL RANGE
V
CC
= 5V
10%;
T
amb
= 0
C to +70
C
PKG. DWG. #
20pin plastic DIP
74F273AN
SOT146-1
20pin plastic SOL
74F273AD
SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D0 D7
Data inputs
1.0/0.033
20
A/20
A
MR
Master Reset input (activeLow)
1.0/0.033
20
A/20
A
CP
Clock pulse input (active rising edge)
1.0/0.033
20
A/20
A
Q0 Q7
Data outputs
50/33
1.0mA/20mA
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MR
Q0
D0
D1
Q1
Q2
D2
D3
Q3
Q4
GND
D4
D5
Q5
Q6
D6
D7
Q7
V
CC
CP
SF00346
LOGIC SYMBOL
3
4
7
8
13
14
18
17
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
1
11
MR
CP
V
CC
= Pin 20
GND = Pin 10
SF00347
Philips Semiconductors
Product specification
74F273A
Octal D flipflop
1996 Mar 12
3
LOGIC SYMBOL (IEEE/IEC)
SF00348
1
3
2
4
5
7
6
8
9
R
11
C1
13
12
14
15
17
16
18
19
1D
LOGIC DIAGRAM
CP
Q
RD
D
3
D0
Q0
CP
Q
RD
D
4
D1
CP
Q
RD
D
7
D2
CP
Q
RD
D
8
D3
CP
Q
RD
D
13
D4
CP
Q
RD
D
14
D5
CP
Q
RD
D
17
D6
CP
Q
RD
D
18
D7
2
Q1
5
Q2
6
Q3
9
Q4
12
Q5
15
Q6
16
Q7
19
11
1
CP
MR
VCC = Pin 20
GND = Pin 10
SF00349
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING
MR
CP
Dn
Q0 Q7
MODE
L
X
X
L
Reset (clear)
H
h
H
Load "1"
H
l
L
Load "0"
H = High voltage level
h
= High voltage level one setup time prior to the LowtoHigh clock transition
L
= Low voltage level
l
= Low voltage level one setup time prior to the LowtoHigh clock transition
X = Don't care
= LowtoHigh clock transition
Philips Semiconductors
Product specification
74F273A
Octal D flipflop
1996 Mar 12
4
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
CC
Supply voltage
0.5 to +7.0
V
V
IN
Input voltage
0.5 to +7.0
V
I
IN
Input current
30 to +5
mA
V
OUT
Voltage applied to output in High output state
0.5 to V
CC
V
I
OUT
Current applied to output in Low output state
40
mA
T
amb
Operating free air temperature range
0 to +70
C
T
stg
Storage temperature range
65 to +150
C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
MIN
TYP
MAX
V
CC
Supply voltage
4.5
5.0
5.5
V
V
IH
Highlevel input voltage
2.0
V
V
IL
Lowlevel input voltage
0.8
V
I
Ik
Input clamp current
18
mA
I
OH
Highlevel output current
1
mA
I
OL
Lowlevel output current
20
mA
T
amb
Operating free air temperature range
0
+70
C
Philips Semiconductors
Product specification
74F273A
Octal D flipflop
1996 Mar 12
5
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
CONDITIONS
1
MIN
TYP
2
MAX
MR & CP
V
CC
= MIN, V
IL
= 0.0V
3
,
10%V
CC
2.5
V
V
OH
High-level output voltage
inputs
V
IH
= 4.5V
3
, I
OH
= MAX
5%V
CC
2.7
3.4
V
other
V
CC
= MIN, V
IL
= MAX,
10%V
CC
2.5
V
inputs
V
IH
= MIN, I
OH
= MAX
5%V
CC
2.7
3.4
V
V
OL
Low-level output voltage
V
CC
= MIN, V
IL
= MAX,
10%V
CC
0.30
0.50
V
V
IH
= MIN, I
OH
= MAX
5%V
CC
0.30
0.50
V
V
IK
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
0.73
-1.2
V
I
I
Input current at maximum input voltage
V
CC
= 0.0V, V
I
= 7.0V
100
A
I
IH
Highlevel input current
V
CC
= MAX, V
I
= 2.7V
20
A
I
IL
Lowlevel input current
V
CC
= MAX, V
I
= 0.5V
20
A
I
OS
Shortcircuit output current
4
V
CC
= MAX
-60
-150
mA
I
CC
Supply current (total)
I
CCH
V
CC
= MAX
24
38
mA
I
CCL
27
43
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
C.
3. To reduce the effect of external noise during test.
4. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
AC CHARACTERISTICS FOR 'F273A
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
C
V
CC
= +5.0V
C
L
= 50pF
R
L
= 500
T
amb
= 0
C to +70
C
V
CC
= +5.0V
10%
C
L
= 50pF
R
L
= 500
UNIT
Min
Typ
Max
Min
Max
f
MAX
Maximum clock frequency
1
150
170
125
MHz
t
PLH
t
PHL
Propagation delay
CP to Qn
1
3.5
5.0
5.0
7.0
8.0
9.5
3.0
4.5
9.0
10.0
ns
t
PHL
Propagation delay
MR to Qn
2
5.0
7.0
9.0
5.0
9.5
ns
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