Page 1 of 15
Document No. 70-0140-01
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
Peregrine's PE9763 is a high performance fractional-N PLL
capable of frequency synthesis up to 3.2 GHz. The device is
designed for superior phase noise performance while providing
an order of magnitude reduction in current consumption, when
compared with the existing commercial space PLLs.
The PE9763 features a 10/11 dual modulus prescaler,
counters, a delta sigma modulator, a phase comparator and a
charge pump as shown in Figure 1. Counter values are
programmable through either a serial interface or directly hard-
wired.
PE9763 is optimized for commercial space applications. Single
Event Latch up (SEL) is physically impossible and Single Event
Upset (SEU) is better than 10-9 errors per bit / day. Fabricated
in Peregrine's patented UTSi (Ultra Thin Silicon) CMOS
technology, the PE9763 offers excellent RF performance and
intrinsic radiation tolerance.
Product Specification
3.2 GHz Delta-Sigma modulated
Fractional-N Frequency Synthesizer
for Low Phase Noise Applications
Product Description
Figure 1. Block Diagram
PE9763
Features
3.2 GHz operation
10/11 dual modulus prescaler
Selectable phase detector or charge
pump output
Serial or Direct mode access
Frequency selectivity: Comparison
frequency / 2
18
Low power --- 25 - 30 mA at 3V (phase
detector / charge pump)
Rad-Hard
Ultra-low phase noise
68-lead CQFJ or Die
Auxilia-
ry
20-bit
Latch
F
in
F
in
Prescaler
10/11
Main
Counter
20
Secon-
dary
20-bit
Latch
Primary
21-bit
Latch
R Counter
f
r
Phase
Detector
6
6
13
Sdata
PD_U
PD_D
DSM
4
Charge
Pump
CP
2
18
13
+
19
20
18
K
17:0
M
8:0
A
3:0
R
5:0
Pre_en
Direct
Product Specification
PE9763
Page 2 of 15
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0140-01
UltraCMOSTM RFIC Solutions
Figure 2. Pin Configuration
V
DD
51
GND
52
PD_U
53
V
DD
54
V
DD
55
56
57
58
GND
59
60
21
FIN
49
CP
50
20
24
26
25
23
22
4
3
7
9
8
6
5
14
13
17
19
18
16
15
10
12
11
65
64
68
2
1
67
66
62
61
63
46
47
48
44
45
32
33
29
27
28
30
31
39
40
36
34
35
37
38
42
43
41
K
2
K
3
K
4
K
5
K
6
K
7
K
8
K
9
K
10
K
11
K
12
K
13
K
14
K
15
K
16
K
17
R
5
K
1
GN
D
K
0
R
4
R
0
R
2
R
3
R
1
RA
ND
_E
N
MS2
_
SE
L
V
DD
EN
H
C
P
SEL
V
DD
F
R
GN
D
A
2
DIR
E
CT
PR
E_
E
N
A
3
A
1
M
6
M
8
A
0
M
7
M
5
M
4
M
0
M
2
M
3
M
1
GN
D
V
DD
GND
PD_D
V
DD
LD
D
OUT
C
EXT
V
DD
FIN
V
DD
GND
Table 1. Pin Descriptions
Pin No.
Pin
Name
Valid
Mode
Type Description
1
R
0
Direct
Input
R Counter bit0 (LSB).
2
R
1
Direct
Input
R Counter bit1.
3
R
2
Direct
Input
R Counter bit2.
4
R
3
Direct
Input
R Counter bit3.
5
R
4
Direct
Input
R Counter bit4.
6
R
5
Direct
Input
R Counter bit5 (MSB).
7
K
0
Direct
Input
K Counter bit0 (LSB).
8
K
1
Direct
Input
K Counter bit1.
9
GND
Downbond
Digital core ground.
GND
Downbond
ESD ground.
10
V
DD
(Note 1)
ESD V
DD
.
V
DD
(Note 1)
Digital core V
DD
.
11
K
2
Direct
Input
K Counter bit2.
12
K
3
Direct
Input
K Counter bit3.
13
K
4
Direct
Input
K Counter bit4.
14
K
5
Direct
Input
K Counter bit5.
15
K
6
Direct
Input
K Counter bit6.
Product Specification
PE9763
Page 3 of 15
Document No. 70-0140-01
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
Pin No.
Pin
Name
Valid
Mode
Type Description
16
K
7
Direct
Input
K Counter bit7.
17
K
8
Direct
Input
K Counter bit8.
18
K
9
Direct
Input
K Counter bit9.
19
K
10
Direct
Input
K Counter bit10.
20
K
11
Direct
Input
K Counter bit11.
21
K
12
Direct
Input
K Counter bit12.
22
K
13
Direct
Input
K Counter bit13.
23
K
14
Direct
Input
K Counter bit14.
24
K
15
Direct
Input
K Counter bit15.
25
K
16
Direct
Input
K Counter bit16.
26
K
17
Direct
Input
K Counter bit17 (MSB).
27
V
DD
(Note 1)
Digital core V
DD
.
V
DD
(Note 1)
ESD V
DD
.
28
GND
Downbond
Digital core ground.
GND
Downbond
ESD ground.
29
M
0
Direct
Input
M Counter bit0 (LSB).
30
M
1
Direct
Input
M Counter bit1.
31
M
2
Direct
Input
M Counter bit2
32
M
3
Direct
Input
M Counter bit3.
33
M
4
Direct
Input
M Counter bit4.
S_WR
Serial
Input
Serial load enable input. While S_WR is "low", Sdata can be serially clocked. Primary register
data are transferred to the secondary register on S_WR or Hop_WR rising edge.
34
M
5
Direct
Input
M Counter bit5.
SDATA
Serial
Input
Binary serial data input. Input data entered MSB first.
35
M
6
Direct
Input
M Counter bit6.
SCLK
Serial
Input
Serial clock input. SDATA is clocked serially into the 20-bit primary register (E_WR "low") or
the 8-bit enhancement register (E_WR "high") on the rising edge of Sclk.
36
M
7
Direct
Input
M Counter bit7.
37
M
8
Direct
Input
M Counter bit8 (MSB).
38
A
0
Direct
Input
A Counter bit0 (LSB).
39
A
1
Direct
Input
A Counter bit1.
E_WR
Serial
Input
Enhancement register write enable. While E_WR is "high", Sdata can be serially clocked into
the enhancement register on the rising edge of Sclk.
40
A
2
Direct
Input
A Counter bit2.
41
A
3
Direct
Input
A Counter bit3 (MSB).
42
DIRECT
Both
Input
Direct mode select. "High" enables direct mode. "Low" enables serial mode.
43
Pre_en
Direct
Input
Prescaler enable, active "low". When "high", Fin bypasses the prescaler.
44
V
DD
(Note 1)
Digital core V
DD
.
45
GND
Downbond
Digital core ground.
GND
Downbond
ESD ground.
Product Specification
PE9763
Page 4 of 15
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0140-01
UltraCMOSTM RFIC Solutions
Pin No.
Pin
Name
Valid
Mode
Type Description
47
F
in
Both
Input
Prescaler input from the VCO. 3.2 GHz max frequency.
48
F
in
Both
Input
Prescaler complementary input. A bypass capacitor should be placed as close as possible to
this pin and be connected in series with a 50 W resistor directly to the ground plane.
49
GND
Downbond
Prescaler ground.
GND
Downbond
Prescaler ground.
GND
Downbond
Output driver/charge pump ground.
50
CEXT
Both
Output
Logical "NAND" of PD_
U
and PD_
D
terminated through an on chip, 2 kW series resistor.
Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier
used for driving LD.
51
LD
Both
Output
Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high
impedance, otherwise LD is a logic low ("0").
52
D
OUT
Both
Output
Data out function, enabled in enhancement mode.
53
V
DD
(Note 1)
Output driver/charge pump V
DD
.
54
GND
Downbond
Output driver/charge pump ground.
55
PD_
D
Both
Output
PD_
D
pulses down when f
p
leads f
c
. PD_
U
is driven to GND when CPSEL = "High".
56
CP
Both
Output
Charge pump output. Selected when CPSEL = "1". Tristate when CPSEL = "Low".
57
PD_
U
Both
Output
PD_
U
pulses down when f
c
leads f
p
. PD_
D
is driven to GND when CPSEL = "High".
58
GND
Downbond
Output driver/charge pump ground.
59
V
DD
(Note 1)
Output driver/charge pump V
DD
.
GND
Downbond
Phase detector GND.
60
V
DD
(Note 1)
Phase detector V
DD
.
V
DD
(Note 1)
ESD V
DD
.
61
GND
Downbond
ESD ground.
GND
Downbond
Reference ground.
62
f
r
Both
Input
Reference frequency input.
63
V
DD
(Note 1)
Reference V
DD
.
64
V
DD
(Note 1)
Digital core V
DD
.
GND
Downbond
Digital core ground.
65
ENH
Both
Input
Enhancement mode. When asserted low ("0"), enhancement register bits are functional.
66
CPSEL
Both
Input
Charge pump select. "High" enables the charge pump and disables pins PD_
U
and PD_
D
by
forcing them "low". A "low" Tri-states the CP and enables PD_
U
and PD_
D
.
67
MS2_SEL
Both
Input
MASH 1-1 select. "High" selects MASH 1-1 mode. "Low" selects the MASH 1-1-1 mode.
68
RND_SEL
Both
Input
K register LSB toggle enable. "1" enables the toggling of LSB. This is equivalent to having
an additional bit for the LSB of K register. The frequency offset as a result of enabling this bit
is the phase detector comparison frequency / 2
19
.
Note 1: All V
DD
pins are connected by diodes and must be supplied with the same positive voltage level.
Note 2:
All digital input pins have 70 k
pull-down resistors to ground.
46
V
DD
(Note 1)
ESD V
DD
.
V
DD
(Note 1)
Prescaler V
DD
.
Product Specification
PE9763
Page 5 of 15
Document No. 70-0140-01
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
Table 2. Absolute Maximum Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOSTM device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOSTM
devices are immune to latch-up.
Note 1: Periodically sampled, not 100% tested. Tested per MIL-
STD-883,
M3015
C2
Table 3. Operating Ratings
Symbol Parameter/Conditions Min Max Units
V
DD
Supply
voltage
-0.3
4.0 V
V
I
Voltage on any input
-0.3
V
DD
+
0.3
V
I
I
DC into any input
-10
+10
mA
I
O
DC into any output
-10
+10
mA
T
stg
Storage temperature range
-65
150
C
Symbol Parameter/Conditions Min Max Units
V
DD
Supply
voltage
2.85
3.15 V
T
A
Operating
ambient
temperature range
-40 85 C
Symbol Parameter/Conditions Level
Units
V
ESD
ESD voltage human body model
(Note 1)
1000 V
Table 4. ESD Rating
s
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