¡ Semiconductor

ML9211

1/19

GENERAL DESCRIPTION

The ML9211 is a full CMOS controller/driver for Duplex or Triplex (1/2 duty or 1/3 duty)
vacuum fluorescent display tube. It consists of a 56-segment driver multiplexed to drive up to
168 segments, and 10-bit digital dimming circuit.
ML9211 features a selection of a master mode and a slave mode, and therefore it can be used to
expand segments for the VFD driver with keyscan and A/D converter function.
ML9211 provides an interface with a microcontroller only by three signal lines: DATA IN,
CLOCK and CS.

FEATURES

· Logic supply voltage (V

)

: 4.5 to 5.5V

· Driver supply voltage (V

DISP

)

: 8 to 18V

· Duplex/Triplex (1/2 duty / 1/3 duty) selectable

DUP/TRI=1/2 duty selectable at "H" level
DUP/TRI=1/3 duty selectable at "L" level

· Number of display segments

Max. 112-segment display (during 1/2 duty mode)
Max. 168-segment display (during 1/3 duty mode)

· Master/Slave selectable

M/S=Master mode selectable at "H" level
M/S=Slave mode selectable at "L" level

· Interface with a microcontroller

Three lines: CS, CLOCK, and DATA IN

· 56-segment driver outputs

: I

=5mA at V

DISP

0.8V (SEG1 to 37)

(can be directly connected to VFD tube

: I

=10mA at V

DISP

0.8V (SEG38 to 56)

and require no external resistors)

: I

=500mA at V

=2V (SEG1 to 56)

· 3-grid pre-driver outputs

: I

=5.0mA at V

DISP

0.8V

(require external drivers)

=10mA at V

=2V

· Logic outputs

: I

=200mA at V

0.8V

=200mA at V

=0.8V

· Built-in digital dimming circuit (10-bit resolution)
· Built-in oscillation circuit (external R and C)
· Built-in Power-On-Reset circuit
· Package options:

80-pin plastic QFP (QFP80-P-1420-0.80-BK)

Product name: ML9211GA

80-pin plastic QFP (QFP80-P-1414-0.65-K)

Product name: ML9211GP

Preliminary

¡ Semiconductor
ML9211

56-Bit Duplex/Triplex (1/2 duty / 1/3 duty) VF Controller/Driver with Digital Dimming

E2C0045-19-83

This version: Aug. 1999

¡ Semiconductor

ML9211

2/19

BLOCK DIAGRAM

Timing Generator

DIM OUT

SYNC OUT1

SYNC OUT2

DIM IN

SYNC IN1

SYNC IN2

M/S

DUP/TRI

OSC

Control

Out1-56

56bit Shift Register

in1-10

Dimming Latch

Out1-10

10bit Digital

Dimming

POR

OSC0

CLOCK

DATA IN

Out1-3

3bit Shift Register

POR

Out1-56

Segment Latch

in1-56

POR

Out1-56

Segment Latch

in1-56

POR

Out1-56

Segment Latch

in1-56

POR

Mode Select

in1-3

POR

Power

Reset

L-GND

POR

Out1-56

168 to 56 Segment Control

in1-56

56 Segment Driver

DISP

D-GND

3 Grid pre Driver

GRID2 GRID3

GRID1

SEG56

SEG1

¡ Semiconductor

ML9211

4/19

PIN CONFIGURATION (TOP VIEW)

NC: No connection

80-pin Plastic QFP

(QFP80-P-1420-0.80-BK)

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

D-GND

DIM OUT

SYNC OUT 1

SYNC OUT 2

DUP/

TRI

OSC0

L-GND

DATA IN

CLOCK

SYNC IN 2

SYNC IN 1

DIM IN

D-GND

GRID3

GRID2

GRID1

SEG56

SEG55

SEG54

SEG53

SEG52

SEG51

SEG50

SEG49

SEG48

SEG47

SEG46

SEG45

SEG44

SEG43

SEG42

SEG41

SEG40

SEG39

SEG38

DISP

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

DISP

¡ Semiconductor

ML9211

5/19

NC: No connection

80-pin Plastic QFP

(QFP80-P-1414-0.65-K)

SEG39

SEG38

DISP

SEG37

SEG36

SEG35

SEG34

SEG33

SEG32

SEG31

SEG30

SEG29

SEG28

SEG27

SEG26

SEG25

SEG24

DISP

SEG23

SEG22

D-GND

DIM IN

SYNC IN 1

SYNC IN 2

CLOCK

DATA IN

L-GND

OSC0

DUP/

TRI

SYNC OUT 2

SYNC OUT 1

DIM OUT

D-GND

SEG1

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20

SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56

GRID1
GRID2
GRID3

¡ Semiconductor

ML9211

6/19

PIN DESCRIPTIONS

Symbol

QFP-1

Type

Description

DISP

65, 80

Power supply pins for VFD driver circuit.
These should be connected externally.

Power supply pin for logic drive.

D-GND

24, 40

L-GND

SEG1 to 37

42 to 64,

66 to 79

D-GND is ground pin for the VFD driver circuit. L-GND is ground pin for the
logic circuit. These should be connected externally.

Segment (anode) signal output pins for a VFD tube. These pins can be directly
connected to the VFD tube. External circuit is not required.
I

5 mA

SEG38 to 56 1 to 19

Segment (anode) signal output pins for a VFD tube.These pins can be directly
connected to the VFD tube. External circuit is not required.
I

10 mA

GRID2

Inverted Grid signal output pins. For pre-driver, the external circuit is required.
I

10 mA

Chip select input pin.
Data is not transferred when CS is set to a Low level.

CLOCK

Shift clock input pin.
Serial data shifts at the rising edge of the CLOCK.

DATA IN

Serial data input pin (positive logic).
Data is input to the shift register at the rising edge of the CLOCK signal.

DUP/TRI

Duplex/Triplex operation select input pin.
Duplex (1/2 duty) operation is selected when this pin is set to V

Triplex (1/3 duty) operation is selected when this pin is set to L-GND.

M/S

Master/Slave mode select input pin.
Master mode is selected when this pin is set to V

Slave mode is selected when this pin is set to L-GND.

Dimming pulse input.
When the slave mode is selected, connect this pin to the master side DIM
OUT pin at the slave mode. The pulse width of the all segment output are
controlled by a input pulse width of DIM IN.
When the master mode is selected, the input level of this pin is ignored.
Connect this pin to V

or L-GND at the master mode. The pulse width of the

all grids and segment outputs are controlled by a built-in 10-bit dimming circuit.

DIM IN

SYNC IN 2

Synchronous signal input.
When the slave mode is selected, connect these pins to the master side SYNC
OUT 1 and 2 pins.
When the master mode is selected, the input level of these pins are ignored.
Connect these pins to V

or L-GND at the master mode.

DIM OUT

Dimming pulse output.
Connect this pin to the slave side DIM IN pin.

QFP-2

63 78

22, 38

40 to 62,

64 to 77

79, 80,
1 to 17

GRID1

GRID3

SYNC IN 1

Pin

¡ Semiconductor

ML9211

7/19

Symbol

QFP-1

Type

Description

SYNC OUT 1

Synchronous signal output.
Connect these pins to the slave side SYNC IN 1 and 2 pins.

OSC0

I/O

RC oscillator connecting pins.
Oscillation frequency depends on display tubes
to be used. For details, refer to ELECTRICAL
CHARACTERISTICS.

QFP-2

SYNC OUT 2

Pin

OSC0

ABSOLUTE MAXIMUM RATING

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

DISP

Driver Supply Voltage

Logic Supply Voltage

High Level Input Voltage

Low Level Input Voltage

Clock Frequency

Operating Temperature

Condition

Min.

Typ.

Max.

Unit

8.0

13.0

18.0

4.5

5.0

5.5

All inputs except OSC0

0.8V

All inputs except OSC0

0.2V

2.0

MHz

+85

°C

OSC

Oscillation Frequency

R=10KW±5%, C=27pF±5%

2.6

3.3

4.0

MHz

Frame Frequency

R=10KW±5%,

C=27pF±5%

211

269

325

1/3 Duty

1/2 Duty

317

403

488

Parameter

Symbol

Condition

Ratings

Unit

DISP

0.3 to +20

Driver Supply Voltage

Logic Supply Voltage

Input Voltage

QFP80-P-1420-0.80-BK

Power Dissipation

STG

°C

Storage Temperature

SEG1 to 37

SEG38 to 56

Output Current

GRID1 to 3

DIM OUT, SYNC OUT1, SYNC OUT2

0.3 to +6.5

0.3 to V

+0.3

760

55 to +150

10.0 to +2.0

20.0 to +2.0

10.0 to +20.0

2.0 to +2.0

QFP80-P-1414-0.65-K

630

Ta25°C

QFP-1: QFP80-P-1420-0.80-BK
QFP-2: QFP80-P-1414-0.65-K

¡ Semiconductor

ML9211

8/19

ELECTRICAL CHARACTERISTICS

DC Characteristics

Parameter

Symbol

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

OH1

OH2

OH3

High Level Output Voltage

Condition

Min.

Max.

Unit

0.8V

0.2V

1.0

+1.0

=GND

1.0

+1.0

DISP

0.8

DISP

0.8

DISP

0.8

DISP

=9.5V

Applied pin

*1)

SEG1-37

SEG38-56

GRID1-3

OH4

*2)

=4.5V

OH1

=5mA

OH2

=10mA

OH3

=5mA

OH4

=200mA

OL1

OL2

OL3

Low Level Output Voltage

2.0

0.8

DISP

=9.5V

SEG1-37

SEG38-56

GRID1-3

OL4

*2)

=4.5V

OL1

=500mA

OL2

=500mA

OL3

=10mA

OL4

=200mA

5.0

Supply Current

100

DISP

R=10KW±5%, C=27pF±5%,

no load

Ta=40 to +85°C,V

DISP

=8.0 to 18.0V, V

=4.5 to 5.5V

*1) CS, CLOCK, DATA IN, DIM IN, SYNC IN 1, SYNC IN 2, M/S, DUP/TRI
*2) DIM OUT, SYNC OUT 1, SYNC OUT 2

¡ Semiconductor

ML9211

9/19

AC Characteristics

TIMING DIAGRAM

Data Input Timing

0.8V

0.2V

0.8V

0.2V

0.8V

0.2V

CLOCK

DATA IN

CSS

1/f

CSH

CSL

VALID

Reset Timing

POF

PRZ

RSOFF

0.8V

0.0V

0.8V

0.0V

Driver Output Timing

0.8V

DISP

0.2V

DISP

SEG1-56, GRID1-3

Parameter

Symbol

Clock Frequency

Clock Pulse Width

Data Setup Time

Data Hold Time

CSL

CS Off Time

CSS

PRZ

CS Setup Time
(CS-Clock)

Output Slew Rate Time

Rise Time

Condition

Min.

Max.

Unit

2.0

MHz

200

=20% to 80%

2.0

=80% to 20%

2.0

Mounted in a unit

100

=100pF

CSH

CS Hold Time
(Clock-CS)

200

POF

Off Time

Mounted in a unit, V

=0.0V

5.0

RSOFF

CS Wait Time

400

Ta=40 to +85°C,V

DISP

=8.0 to 18.0V, V

=4.5 to 5.5V

¡ Semiconductor

ML9211

10/19

Output Timing (Duplex Operation)

*1bit time=4/f

OSC

(The dimming data is 1016/1024 in the master mode)

GRID1

DISP

D-GND

GRID2

DISP

D-GND

GRID3

SEG1-56

DISP

D-GND

DIM OUT

L-GND

SYNC OUT1

L-GND

SYNC OUT2

L-GND

DISP

D-GND

2048bit times (1 display cycle)

1016bit times

1019bit times

1029bit times

1019bit times

1029bit times

5bit times

3bit times

8bit times

5bit times

Output Timing (Triplex Operation)

*1bit time=4/f

OSC

(The dimming data is 1016/1024 in the master mode)

GRID1

DISP

D-GND

GRID2

DISP

D-GND

GRID3

SEG1-56

DISP

D-GND

DIM OUT

L-GND

SYNC OUT1

L-GND

SYNC OUT2

L-GND

DISP

D-GND

3072bit times (1 display cycle)

1016bit times

1019bit times

1029bit times

1019bit times

1029bit times

5bit times

3bit times

8bit times

5bit times

1019bit times

1016bit times

8bit times

¡ Semiconductor

ML9211

11/19

Output Timing (Duplex Operation)

*1bit time=4/f

OSC

(The dimming data is 64/1024 in the master mode)

Output Timing (Triplex Operation)

*1bit time=4/f

OSC

(The dimming data is 64/1024 in the master mode)

GRID1

DISP

D-GND

GRID2

DISP

D-GND

GRID3

SEG1-56

DISP

D-GND

DIM OUT

L-GND

SYNC OUT1

L-GND

SYNC OUT2

L-GND

DISP

D-GND

2048bit times (1 display cycle)

64bit times

67bit times

1981bit times

957bit times

3bit times

960bit times

67bit times

1981bit times

67bit times

960bit times

957bit times

GRID1

DISP

D-GND

GRID2

DISP

D-GND

GRID3

SEG1-56

DISP

D-GND

DIM OUT

L-GND

SYNC OUT1

L-GND

SYNC OUT2

L-GND

DISP

D-GND

3072bit times (1 display cycle)

64bit times

67bit times

1981bit times

957bit times

3bit times

960bit times

67bit times

1981bit times

67bit times

960bit times

957bit times

67bit times

64bit times

960bit times

¡ Semiconductor

ML9211

12/19

Segment Data Input [Function Mode: 0 to 3]
· ML9211 receives the segment data when function mode 0 to 3 are selected.
· The same segment data is transferred to the 3 segment data latches corresponding to GRID 1

to 3 at the same time when the function mode 0 is selected.

· The segment data is transferred to only one segment data latch corresponding to the specified

GRID when the function mode is 1, 2 or 3 is selected.

· Segment output (SEG1 to 56) becomes High level (lighting) when the segment data (S1 to S56)

is set to "1".

[Data Format]

Input Data

: 59 bits

Segment Data : 56 bits
Mode Data

: 3 bits

FUNCTIONAL DESCRIPTION

Power-on Reset
When power is turned on, the ML9211 is initialized by the internal power-on reset circuit.
The status of the internal circuit after initialization is as follows:
· The contents of the shift registers and latches are set to "0".
· The digital dimming duty cycle is set to "0".
· All segment outputs are set to Low level.
· All grid outputs are set to High level.

Data Transfer Method
Data can be transferred between the rising edge and the next falling edge of chip select input.
The mode data, segment data and dimming data are written by a serial transfer method. The
serial data is input to the shift register at the rising edge of a shift clock pulse.
The mode data (M0 to M2) must be transferred after the segment data and dimming data
succeedingly.
When the chip select input falls, an internal LOAD signal is automatically generated and data is
loaded to the latches.

Function Mode
Function mode is selected by the mode data (M0 to M2). The relation between function mode and
mode data is as follows:

FUNCTION MODE

OPERATING MODE

FUNCTION DATA

Segment Data for GRID1-3 Input

Segment Data for GRID1 Input

Segment Data for GRID2 Input

Segment Data for GRID3 Input

Digital Dimming Data Input

S53

S54

S55

S56

Bit

Input Data

Segment Data (56bits)

Mode Data

(3bits)

¡ Semiconductor

ML9211

13/19

[Bit correspondence between segment output and segment data]

S21

S22

S23

S24

S25

S26

S27

S28

S29

S10

S30

S11

S31

S12

S32

S13

S33

S14

S34

S15

S35

S16

S36

SEG n

Segment data

SEG n

Segment data

S17

S37

S18

S38

S19

S39

S20

S40

S41

S42

S43

S44

S45

S46

S47

S48

S49

S50

S51

S52

S53

S54

S55

S56

SEG n

Segment data

Digital Dimming Data Input [Function Mode: 4]
· ML9211 receives the digital dimming data when function mode 4 is selected.
· The output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid.
· The 10-bit digital dimming data is input from LSB.

[Data Format]

Input Data

: 13 bits

Digital Dimming Data: 10 bits
Mode Data

: 3 bits

D10

Bit

Input Data

Digital Dimming Data (10bits)

Mode Data

(3bits)

D10

Dimming Data

(MSB)

(LSB)

Duty Cycle

0/1024

1/1024

1015/1024

1016/1024

LSB

MSB

Master Mode
Master Mode is selected when M/S pin is set at High level. The master mode operation is as
follows:
· The input levels of DIM IN, SYNC IN1 and SYNC IN2 are ignored, and these pins should be

connected to L-GND or V

· Brightness is adjusted by the internal digital dimming circuit.
· The segment Latch1 to 3 corresponding to GRID1 to 3 are selected by the internal timing

generator.

¡ Semiconductor

ML9211

14/19

SYNC IN 1

SYNC IN 2

Segment Latch

GRID

Latch1

GRID1

Latch2

GRID2

Latch3

GRID3

DIM IN

SEG1 to 56

Low

High

Slave Mode
Slave Mode is selected when M/S pin is set at Low level. The slave mode operation is as follows:
· The internal dimming circuit is ignored.
· The pulse width of SEG1 to 56 are controlled by the pulse width of DIM IN signal.
· The segment Latch1 to 3 corresponding to GRID1 to 3 are selected by SYNC IN1 and SYNC IN2

signals.

· The output levels of GRID1 to 3 are set at High level. The output levels of DIM OUT, SYNC

OUT1 and SYNC OUT2 are set at Low level.

[Correspondence between SYNC IN1, 2 and Segment Latch1 to 3] [Correspondence between DIM IN and SEG1 to 56]

Note: Low: Lights OFF

High: Lights ON

¡ Semiconductor

ML9211

15/19

APPLICATION CIRCUITS

1. Circuit for the duplex VFD tube with 128 segments (2 Grid

112 Anode)

ML9211

(MASTER)

DISP

D-GND

L-GND

OSC 0

CLOCK

DATA IN

DIM IN

SYNC IN 1

SYNC IN 2

M/S

DUP/TRI

DIM OUT

SYNC OUT 1

SYNC OUT 2

GRID2

GRID1

GRID3

SEG1

SEG56

ML9211
(SLAVE)

DISP

D-GND

L-GND

OSC 0

CLOCK

DATA IN

DIM IN

SYNC IN 1

SYNC IN 2

DIM OUT

SYNC OUT 1

SYNC OUT 2

GRID2

GRID1

GRID3

SEG1

SEG56

Duplex VFD Tube

S110 S111 S112

S1 S2 S3

Microcontroller

DISP

M/S

GND

DUP/TRI

GND

¡ Semiconductor

ML9211

16/19

2. Circuit for the triplex VFD tube with 192 segments (3 Grid

112 Anode)

ML9211

(MASTER)

DISP

D-GND

L-GND

OSC 0

CLOCK

DATA IN

DIM IN

SYNC IN 1

SYNC IN 2

DUP/TRI

M/S

DIM OUT

SYNC OUT 1

SYNC OUT 2

GRID2

GRID1

GRID3

SEG1

SEG56

ML9211
(SLAVE)

DISP

D-GND

L-GND

CLOCK

DATA IN

DIM IN

SYNC IN 1

SYNC IN 2

DUP/TRI

M/S

DIM OUT

SYNC OUT 1

SYNC OUT 2

GRID2

GRID1

GRID3

SEG1

SEG56

Triplex VFD Tube

S110 S111 S112

S1 S2 S3

G1
G2

Microcontroller

DISP

GND

OSC 0

GND

¡ Semiconductor

ML9211

18/19

(Unit : mm)

PACKAGE DIMENSIONS

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

QFP80-P-1420-0.80-BK

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more
1.27 TYP.

Mirror finish

¡ Semiconductor

ML9211

19/19

(Unit : mm)

Notes for Mounting the Surface Mount Type Package

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more
0.85 TYP.

QFP80-P-1414-0.65-K

Mirror finish

NOTICE

The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.

The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.

When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.

Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.

Neither indemnity against nor license of a third party's industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party's right which may result from the use thereof.

The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.

Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.

No part of the contents contained herein may be reprinted or reproduced without our prior
permission.

MS-DOS is a registered trademark of Microsoft Corporation.

Printed in Japan

E2Y0002-29-62

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ML9211

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ML9211