OKI Semiconductor
FEDL9042-01
Issue Date: Nov. 19, 2003
ML9042-xx
DOT MATRIX LCD CONTROLLER DRIVER
1/58
GENERAL DESCRIPTION
The ML9042 used in combination with an 8-bit or 4-bit microcontroller controls the operation of a character type
dot matrix LCD.
FEATURES
Easy interfacing with an 8-bit or 4-bit microcontroller
Switchable between serial and parallel interfaces
Dot-matrix LCD controller driver for a 5 8 dot font
Built-in circuit allowing automatic resetting at power-on
Built-in 17 common signal drivers and 100 segment signal drivers
Two built-in character generator ROMs each capable of generating 240 characters (5 8 dots)
The character generator ROM can be selected by bank switching (ROM1S) pin.
Creation of character patterns by programming: up to 8 character patterns (5 8 dots)
Built-in RC oscillation circuit using external or internal resistors
Program-selectable
duties
When ABE bit is "L": 1/8 duty (1 line: 5
8 dots), or 1/16 duty (2 lines: 5 8 dots)
When ABE bit is "H": 1/9 duty (1 line: 5
8 dots + arbitrator), or 1/17 duty (2 lines: 5 8 dots + arbitrator)
Cursor
display
Built-in bias dividing resistors to drive the LCD
Bi-directional transfer of segment outputs
Bi-directional transfer of common outputs
100-dot arbitrator display
Line display shifting
Built-in voltage multiplier circuit
Gold Bump Chip
ML9042-xx CVWA/DVWA
*xx indicates a character generator ROM code number.
*01, 11 and 21 indicate general character generator ROM code numbers.
CVWA indicates a bump chip with high hardness, and DVWA indicates a bump chip with low
hardness.
FEDL9042-01
OKI Semiconductor
ML9042-xx
2/58
BLOCK DIAGRAM
V
DD
GND
OS
C
1
OS
C
R3
OS
C
2
RS
1
RS
0
/CS
B
RW/SI
E/
SHT
B
SP
DB
0
(
S
O
)
to
DB
3
4
DB
4
to
DB
7
4
T
1
T
2
T
3
V
4
V
3B
V
2
V
3A
V
1
V
0
V
OU
T
Tim
i
ng
g
ener
ator
8
I/
O
B
u
ffer
8
In
str
u
ction
de
c
o
de
r
(ID
)
Parallel-
serial converter
7
8
8
8
Data
r
egist
er
(
DR)
5
COM
1
SE
G
1
COM
17
Te
s
t
cir
c
u
i
t
LCD bias
vo
l
t
age
d
i
viding
cir
c
u
i
t
8
B
u
sy flag
(B
F
)
E
x
pa
nsion
instr
u
ction
r
egiste
r
(E
R)
Vol
t
age
m
u
lt
ipli
er
ci
rcui
t
A
d
d
r
ess
cou
n
ter
(
A
DC)
E
x
pansio
n
instr
u
ctio
n
regist
er (E
D)
C
harac
t
e
r
ge
nerato
r
RAM
(C
G R
A
M
)
8
8
Display
data
RAM
(
DD RAM
)
A
r
bitr
ator
RA
M
(
AB RAM
)
Cur
s
or
blin
k
contr
o
ller
5
5
17
-
b
it
b
i
-d
irect
i
on
al
shi
f
t
regi
st
er
Com
m
o
n
sign
al
dri
v
e
r
100-bit bi-directional shift register
100-bit latch
Segment Signal driver
SE
G
100
BE
V
CC
V
C
V
IN
C
harac
te
r
gen
erator
RO
M
(C
G
R
O
M)
I
n
str
u
ction
regi
ster
(IR)
OS
C
R5
ROM
1
S
FEDL9042-01
OKI Semiconductor
ML9042-xx
3/58
I/O CIRCUITS
V
DD
P
N
Applied to pins T
1
, T
2
, and T
3
V
DD
P
N
V
DD
Applied to pins RW/SI, RS
1
, and
RS
0
/CSB
Applied to pins E/SHTB, SP, ROM1S, and BE
V
DD
P
V
DD
P
N
V
DD
P
N
Applied to pins DB
0
(SO) to DB
7
Output Enable signal
FEDL9042-01
OKI Semiconductor
ML9042-xx
4/58
PIN DESCRIPTIONS
Symbol Description
RW/SI
The input pin with a pull-up resistor to select Read ("H") or Write ("L") in the Parallel I/F
Mode.
The pin to input data in the Serial l/F Mode. Each instruction code and each data are
read in by the rising edge of the E/SHTB signal.
RS
0
/CSB, RS
1
The input pins with a pull-up resistor to select a register in the Parallel l/F Mode.
The RSo/CSB pin is configured as a chip enable input in the Serial I/F Mode. Setting
the RSo/CSB pin to "L" allows the I/F to be provided.
E/SHTB
The input pin for data input/output between the CPU and the ML9042 and for
activating instructions in the Parallel l/F Mode.
This pin is configured as a shift clock input in the Serial I/F Mode. The data input to the
PW/SI pin is synchronized to the rising edge of the clock, and the data output from the
DB0(SO) pin is synchronized to the falling edge of the shift clock.
DB
0
(SO) to DB
3
The input/output pins to transfer data of lower-order 4 bits between the CPU and the
ML9042 in the Parallel l/F Mode. The pins are not used for the 4-bit interface.
Only the DB0(SO) pin is configured as a data output in the Serial I/F Mode. Busy flag
& address and data are output synchronized to the falling edge of the E/SHTB signal.
These pins remain pulled up when data is not output.
Each pin is equipped with a pull-up resistor, so this pin should be open when not used.
DB
4
to DB
7
The input/output pins to transfer data of upper 4 bits between the CPU and the
ML9042 in the Parallel l/F Mode. The pins are not used for the serial interface.
Each pin is equipped with a pull-up resistor, so this pin should be open in the Serial I/F
Mode when not used.
OSC
1
OSC
2
OSC
R3
OSC
R5
The clock oscillation pins required for LCD drive signals and the operation of the
ML9042 by instructions sent from the CPU.
To input external clock, the OSC
1
pin should be used. The OSC
R3
, OSC
R5,
and
OSC
2
pins should be open.
To start oscillation with an external resistor, the resistor should be connected between
the OSC
1
and OSC
2
pins. The OSC
R3
and OSC
R5
pins should be open.
To start oscillation at 5 V using an internal resistor, the OSC
2
and OSC
R5
pins should
be short-circuited outside the ML9042. The OSC
1
and OSC
R3
pins should be open.
To start oscillation at 3 V using an internal resistor, the OSC
2
and OSC
R3
pins should
be short-circuited outside the ML9042. The OSC
1
and OSC
R5
pins should be open.
(The OSC
2
, OSC
R3,
and OSC
R5
pins can also be short-circuited outside the ML9042,
and the OSC
1
pin can be open.)
COM
1
to COM
17
The LCD common signal output pins.
For 1/8 duty, non-selectable voltage waveforms are output via COM
9
to COM
17
. For
1/9 duty, non-selectable voltage waveforms are output via COM
10
to COM
17
. For 1/16
duty, a non-selectable voltage waveform is output via COM
17.
SEG
1
to SEG
100
The LCD segment signal output pins.
RS
1
RS
0
/CSB
Name of register
H
H
Data register
H
L
Instruction register
L
L
Expansion Instruction register
FEDL9042-01
OKI Semiconductor
ML9042-xx
5/58
Symbol Description
ROM1S
The input pin to switch the ROM bank. "H" selects ROM1 and "L" selects ROM0.
Switching after power-on is prohibited.
V
1
, V
2
, V
3A
, V
3B
, V
4
The pins to output bias voltages to the LCD.
For 1/4 bias : The V
2
and V
3B
pins are shorted.
For 1/5 bias : The V
3A
and V
3B
pins are shorted.
BE
The input pin to enable or disable the voltage multiplier circuit.
"L" disables the voltage multiplier circuit. "H" enables the voltage multiplier circuit.
The voltage multiplier circuit doubles the input voltage between the V
IN
pin and the
GND pin, and the multiplied voltage referenced to the GND is output to the V
OUT
pin.
The voltage multiplier circuit can be used only when generating a level higher than the
V
DD
.
TEST
IN
The input pin for test circuits. Normally connect this pin to V
DD
.
TEST
OUT
The output pin for the test circuits. Normally leave this pin open.
V
IN
The pin to input voltage to the voltage multiplier.
V
0
, V
OUT
The pins to supply the LCD drive voltage.
The same potential as the V
DD
potential is supplied to the V
OUT
and V
0
pins when the
voltage multiplier is not used (BE = "0" or BE = "1", and the capacitor is not connected
to the V
C
and V
CC
pins)
When the voltage multiplier is used (BE = "1"), the multiplied voltage is output to the
V
OUT
pin, so that the V
OUT
pin and V
0
pin should be connected.
Capacitors for the voltage multiplier should be connected between the GND and the
V
OUT
pin.
V
C
The pin to connect the negative pin of the capacitor for the voltage multiplier. Leave the
pin open when the voltage multiplier circuit is not used.
V
CC
The pin to connect the positive pin of the capacitor used for the voltage multiplier.
Leave the pin open when the voltage multiplier circuit is not used.
T
1
, T
2
, T
3
The input pins for test circuits (normally open). Each of these pins is equipped with a
pull-down resistor, so this pin should be left open.
V
DD
The power supply pin.
GND
The ground level input pin.
SP
The input pin to select the serial or parallel interface.
"L" selects the parallel interface.
"H" selects the serial interface.
DUMMYV
DD
The output pin to fix the adjacent input pin to the V
DD
level. Use this pin only for this
purpose.
DUMMYGND
The output pin to fix the adjacent input pin to the GND level. Use this pin only for this
purpose.
DUMMY
NC (No Connection) pin.
FEDL9042-01
OKI Semiconductor
ML9042-xx
6/58
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V)
Parameter Symbol
Condition
Rating Unit Applicable
pins
Supply Voltage
V
DD
Ta = 25
C
0.3 to +6.5
V
V
DD
LCD Driving Voltage
V
0,
V
1
, V
2
,
V
3
, V
4
,
Ta = 25
C
0.3 to +6.5
V
V
OUT
, V
0
, V
1
, V
2
, V
3A
, V
3B,
V
4
,
GND
Input Voltage
V
I
Ta = 25
C
0.3 to V
DD
+0.3 V
RW/SI, E/SHTB, SP,
RS
0
/CSB, RS
1
, BE,
ROM1S, T
1
to T
3
, DB
0
(SO)
to DB
7
, V
IN
Storage Temperature
T
STG
--
55 to +150
C --
RECOMMENDED OPERATING CONDITIONS
(GND = 0 V)
Parameter Symbol
Condition
Range Unit Applicable
pins
Supply Voltage
V
DD
--
2.7 to 5.5
V
V
DD
LCD Driving Voltage
V
0
(See Note)
--
2.7 to 5.5
V
V
OUT,
V
0
Voltage Multipler
Input Voltage
V
MUL
BE = "1"
1.8 to 2.75
V
V
IN
Operating Temperature
T
op
--
40 to +85
C --
Note: This voltage should be applied across V
0
and GND. The following voltages are output to the V
1
,
V
2
, V
3A
(V
3B
) and V
4
pins:
1/4 bias (V
2
and V
3B
are short-circuited)
V
1
=3 V
0
/4
0.15 V
V
2
= V
3B
= V
0
/2
0.15 V
V
4
= V
0
/4
0.15 V
1/5 bias (V
3A
and V
3B
are short-circuited)
V
1
= 4 V
0
/5
0.15 V
V
2
= 3 V
0
/5
0.15 V
V
3A
= V
3B
= 2 V
0
/5
0.15 V
V
4
= V
0
/5
0.15 V
The voltages at the V
0
, V
1
, V
2
, V
3A
(V
3B
), V
4
and GND pins should satisfy
V
0
> V
1
> V
2
> V
3A
(V
3B
) > V
4
> GND
(Higher
Lower)
* If the chip is attached on a substrate using COG technology, the chip tends to be susceptible
to electrical characteristics of the chip due to trace resistance on the glass substrate. It is
recommended to use the chip by confirming that it operates on the glass substrate properly.
Trace resistance, especially, V
DD
and V
SS
trace resistance, between the chip on the LCD
panel and the flexible cable should be designed as low as possible. Trace resistance that
cannot be very well decreased, larger size of the LCD panel, or greater trace capacitance
between the microcontroller and the ML9042 device can cause device malfunction. In order
to avoid the device malfunction, power noise should be reduced by serial interfacing of the
microcontroller and the ML9042 device.
* Do not apply short-circuiting across output pins and across an output pin and an input/output
pin or the power supply pin in the output mode.
FEDL9042-01
OKI Semiconductor
ML9042-xx
7/58
ELECTRICAL CHARACTERISTICS
DC Characteristics
(GND
= 0 V, V
DD
= 2.7 to 5.5 V, Ta = 40 to +85
C)
Parameter Symbol
Condition
Min.
Typ.
Max.
Unit
Applicable
pin
"H" Input Voltage
V
IH
0.8V
DD
-- V
DD
"L" Input Voltage
V
IL
--
0 --
0.2V
DD
V
RW/SI,
RS
0
/CSB, RS
1
,
E/SHTB,
DB
0
(SO) to
DB
7
, SP,
OSC
1
, BE,
ROM1S
"H" Output Voltage 1
V
OH1
I
OH
= 0.1 mA
0.9V
DD
-- --
"L" Output Voltage 1
V
OL1
I
OL
= +0.1 mA
--
--
0.1V
DD
V
DB
0
(SO) to
DB
7
"H" Output Voltage 2
V
OH2
I
OH
= 13
A 0.9V
DD
-- --
"L" Output Voltage 2
V
OL2
I
OL
= +13
A --
--
0.1V
DD
V OSC
2
V
CH
l
OCH
= 4
A V
0
0.3
V
0
0.012
V
0
V
CMH
l
OCMH
=
4
A V
1
0.3
V
1
0.012
V
1
+0.3
V
CML
l
OCML
=
4
A V
4
0.3
V
4
0.012
V
4
+0.3
COM Voltage Drop
V
CL
l
OCL
= +4
A
V
0
GND = 5 V
Note 1
GND
GND+
0.012
GND+0.3
V
COM
1
to
COM
17
V
SH
l
OSH
= 4
A V
0
0.3
V
0
0.012
V
0
V
SMH
l
OSMH
=
4
A V
2
0.3
V
2
0.012
V
2
+0.3
V
SML
l
OSML
=
4
A V
3
0.3
V
3
0.012
V
3
+0.3
SEG Voltage Drop
V
SL
l
OSL
= +4
A
V
0
GND = 5 V
Note 1
GND
GND+
0.012
GND+0.3
V
SEG
1
to
SEG
100
Input Leakage Current
| IIL | V
DD
= 5 V, V
I
= 5 V or 0 V
--
--
1.0
A
E/SHTB, BE,
SP, V
IN
V
DD
= 5 V, V
I
= GND
10
25
61
Input Current 1
| II1 |
V
DD
= 5 V, V
I
= V
DD
,
Excluding current flowing
through the pull-up resistor
and the output driving MOS
-- -- 2.0
A
RW/SI,
RS
0
/CSB, RS
1
,
DB
0
(SO) to
DB
7
V
DD
= 5 V, V
I
= V
DD
15
45
105
Input Current 2
| II2 | V
DD
= 5 V, V
I
= GND
Excluding current flowing
through the pull-down resistor
-- -- 2.0
A T
1
, T
2
, T
3
Supply Current
l
DD
V
DD
= 5 V
Note 2
--
--
1.2
mA V
DD
GND
Oscillation Frequency
of External Resistor Rf
f
osc1
Rf = 85 k
2% Note
3
175
270
400
kHz
OSC
1
, OSC
2
FEDL9042-01
OKI Semiconductor
ML9042-xx
8/58
V
DD
= 4.0 to 5.5 V
Ta = -20 to 75
C
OSC
1
and OSC
R3
: Open
OSC
2
and OSC
R5
:
Short-circuited
Note 4
200 270 351 kHz
OSC
1
, OSC
2
,
OSC
R5
Oscillation Frequency of
Internal Resistor Rf
f
osc2
V
DD
= 2.7 to 3.6 V
Ta = -20 to 75
C
OSC
1
and OSC
R5
: Open
OSC
2
and OSC
R3
:
Short-circuited
Note 4
200 280 364 kHz
OSC
1
, OSC
2
,
OSC
R3
Clock Input
Frequency
f
in
OSC
2
, OSC
R
: Open
Input from OSC
1
175 -- 400
kHz
Input Clock Duty
f
duty
Note
5
45
50
55
%
Input Clock Rise
Time
f
rf
Note
6
-- -- 0.2
s
External Clock
Input Clock Fall Time
f
ff
Note
6
-- -- 0.2
s
OSC
1
-0x code
1.4
2.0
2.6
k
V
0
, V
1
, V
2
, V
3A
,
V
3B
, V
4
, GND
-1x code
2.8
4.0
5.2
k
V
0
, V
1
, V
2
, V
3A
,
V
3B
, V
4
, GND
LCD Bias Resistor
R
LB
-2x code
7.0
10.0
13.0
k
V
0
, V
1
, V
2
, V
3A
,
V
3B
, V
4
, GND
FEDL9042-01
OKI Semiconductor
ML9042-xx
9/58
(GND
= 0 V, V
DD
= 2.7 to 5.5 V, Ta = 40 to +85
C)
Parameter Symbol
Condition
Min.
Typ.
Max.
Unit
Applicable
pins
Voltage Multiplier
Input Voltage
V
MUL
Note
7
1.8 -- 2.75 V
V
IN
1/5
bias
4.3 --
(V
DD
V
IN
)
2
Voltage Multiplier
Output Voltage
V
OUT
V
DD
= 2.7 V, V
IN
= 2.25 V
f = 175 kHz
A capacitor for the voltage
multiplier = 1 to 4.7
F
V
OUT
load current = 54
A
BE = "H"
Applied to LCD bias
resistance of 10 k
(TYP)
only
1/4
bias
4.3 --
(V
DD
V
IN
)
2
V V
OUT
V
LCD1
1/5
bias
2.7 -- 5.5
Bias Voltage for
Driving LCD
V
LCD2
V
0
GND Note 8
1/4
bias
2.7 -- 5.5
V V
0
Note 1: Applied to the voltage drop occurring between any of the V
0
, V
1
, V
4
and GND pins and any of
the common pins (COM
1
to COM
17
) when the current of 4
A flows in or flows out at one
common pin.
Also applied to the voltage drop occurring between any of the V
0
, V
2
, V
3A
(V
3B
) and GND pins
and any of the segment pins (SEG
1
to SEG
100
) when the current of 4
A flows in or flows out at
one segment pin.
The current of 4
A flows out when the output level is V
DD
or flows in when the output level is
V
5
.
Note 2: Applied to the current flowing into the V
DD
pin when the external clock (f
OSC2
= f
in
= 270 kHz) is
fed to the internal R
f
oscillation or OSC
1
under the following conditions:
V
DD
= V
0
= 5 V
GND = 0 V,
V
1
, V
2
, V
3A
(V
3B
) and V
4
: Open
E/SHTB and BE: "L" (fixed)
Other input pins: "L" or "H" (fixed)
Other output pins: No load
FEDL9042-01
OKI Semiconductor
ML9042-xx
10/58
Note 3:
Note 4:
The wire between OSC
R3
and
OSC
2,
or between OSC
R5
and OSC
2
should be as short as possible. Keep open
between OSC
1
and OSC
R3,
or between OSC
1
and OSC
R5.
The wire between OSC
1
and R
f
and the wire between
OSC
2
and R
f
should be as short as possible.
Keep OSC
R3
and OSC
R5
open.
OSC
1
OSC
R3
OSC
2
OSC
1
OSC
R5
OSC
2
OSC
R3
OSC
R5
OSC
1
OSC
R5
OSC
2
R
f
= 85 k
2%
OSC
R3
Note 5:
t
HW
t
LW
V
DD
2
f
IN
waveform
V
DD
2
V
DD
2
Applied to the pulses entering from the OSC
1
pin
f
duty
= t
HW
/(t
HW
+ t
LW
) 100 (%)
Note 6:
0.8V
DD
Applied to the pulses entering from the OSC
1
pin
0.8V
DD
0.2V
DD
0.2V
DD
t
rf
t
ff
Note 7: The maximum value of the voltage multiplier input voltage should be set at 2.75 V, and the
minimum value of the voltage multiplier input voltage should be set by monitoring the voltage
of V
0
in actual use so that the voltage multiplier output voltage meets the specification for the
bias voltage for driving LCD after contrast adjustment.
Note 8: For 1/4 bias, V
2
and V
3B
pins are short-circuited. V
3A
pin is open.
For 1/5 bias, V
3A
and V
3B
pins are short-circuited. V
2
pin is open.
FEDL9042-01
OKI Semiconductor
ML9042-xx
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I/O Characteristics
Parallel Interface Mode
The timing for the input from the CPU and the timing for the output to the CPU are as shown below:
1) WRITE MODE (Timing for input from the CPU)
(V
DD
= 2.7 to 4.5 V, Ta = 40 to +85
C)
Parameter Symbol
Min.
Typ.
Max.
Unit
RW/SI, RS
0
/CSB, RS
1
Setup Time
t
B
40
--
--
ns
E/SHTB Pulse Width
t
W
450 -- -- ns
RW/SI, RS
0
/CSB, RS
1
Hold Time
t
A
10
--
--
ns
E/SHTB Rise Time
t
r
--
--
125
ns
E/SHTB Fall Time
t
f
--
--
125
ns
E/SHTB Pulse Width
t
L
430
-- -- ns
E/SHTB Cycle Time
t
C
1000
-- -- ns
DB
0
(SO) to DB
7
Input Data Setup Time
t
I
195
--
-- ns
DB
0
(SO) to DB
7
Input Data Hold Time
t
H
10
--
--
ns
(V
DD
= 4.5 to 5.5 V, Ta = 40 to +85
C)
Parameter Symbol
Min.
Typ.
Max.
Unit
RW/SI, RS
0
/CSB, RS
1
Setup Time
t
B
40
--
--
ns
E/SHTB Pulse Width
t
W
220 -- -- ns
RW/SI, RS
0
/CSB, RS
1
Hold Time
t
A
10
--
--
ns
E/SHTB Rise Time
t
r
--
--
125
ns
E/SHTB Fall Time
t
f
--
--
125
ns
E/SHTB Pulse Width
t
L
220
-- -- ns
E/SHTB Cycle Time
t
C
500
-- -- ns
DB
0
(SO) to DB
7
Input Data Setup Time
t
I
60
--
--
ns
DB
0
(SO) to DB
7
Input Data Hold Time
t
H
10
--
--
ns
RS
1
, RS
0
/CSB
V
IH
V
IL
V
IH
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
V
IL
V
IH
V
IL
RW/SI
E/SHTB
DB
0
(SO) to DB
7
t
L
t
B
t
W
t
r
t
f
t
A
t
H
t
I
Input
Data
t
C
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2) READ MODE (Timing for output to the CPU)
(V
DD
= 2.7 to 4.5 V, Ta = 40 to +85
C)
Parameter Symbol
Min.
Typ.
Max.
Unit
RW/SI, RS
1
, RS
0
/CSB Setup Time
t
B
40
--
--
ns
E/SHTB Pulse Width
t
W
450 -- -- ns
RW/SI, RS
1
, RS
0
/CSB Hold Time
t
A
10
--
--
ns
E/SHTB Rise Time
t
r
--
--
125
ns
E/SHTB Fall Time
t
f
--
--
125
ns
E/SHTB Pulse Width
t
L
430
-- -- ns
E/SHTB Cycle Time
t
C
1000
-- -- ns
DB
0
(SO) to DB
7
Output Data Delay Time
t
D
--
--
350
ns
DB
0
(SO) to DB
7
Output Data Hold Time
t
O
20
--
--
ns
Note: A load capacitance of each of DB
0
(SO) to DB
7
must be 50 pF or less.
(V
DD
= 4.5 to 5.5 V, Ta = 40 to +85
C)
Parameter Symbol
Min.
Typ.
Max.
Unit
RW/SI, RS
1
, RS
0
/CSB Setup Time
t
B
40
--
--
ns
E/SHTB Pulse Width
t
W
220 -- -- ns
RW/SI, RS
1
, RS
0
/CSB Hold Time
t
A
10
--
--
ns
E/SHTB Rise Time
t
r
--
--
125
ns
E/SHTB Fall Time
t
f
--
--
125
ns
E/SHTB Pulse Width
t
L
220
-- -- ns
E/SHTB Cycle Time
t
C
500
-- -- ns
DB
0
(SO) to DB
7
Output Data Delay Time
t
D
--
--
250
ns
DB
0
(SO) to DB
7
Output Data Hold Time
t
O
20
--
--
ns
Note: A load capacitance of each of DB
0
(SO) to DB
7
must be 50 pF or less.
RS
1
, RS
0
/CSB
V
IH
V
IL
V
IH
V
IL
V
IH
V
IH
V
IL
V
IL
V
IL
V
IH
V
IH
0.8V
DD
0.2V
DD
0.8V
DD
0.2V
DD
RW/SI
E/SHTB
DB
0
(SO) to DB
7
t
L
t
B
t
W
t
r
t
f
t
A
t
O
t
D
Output
Data
t
C
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Serial Interface Mode
(V
DD
= 2.7 to 5.5 V, Ta = 40 to +85
C)
Parameter Symbol
Min.
Typ.
Max.
Unit
E/SHTB Cycle Time
t
SCY
500 -- -- ns
RS
0
/CSB Setup Time
t
CSU
100 -- -- ns
RS
0
/CSB Hold Time
t
CH
100 -- -- ns
RS
0
/CSB "H" Pulse Width
t
CSWH
200 -- -- ns
E/SHTB Setup Time
t
SSU
60 -- -- ns
E/SHTB Hold Time
t
SH
200 -- -- ns
E/SHTB "H" Pulse Width
t
SWH
200 -- -- ns
E/SHTB "L" Pulse Width
t
SWL
200 -- -- ns
E/SHTB Rise Time
t
SR
-- --
125
ns
E/SHTB Fall Time
t
SF
-- --
125
ns
RW/Sl Setup Time
t
DISU
100 -- -- ns
RW/Sl Hold Time
t
DIH
100 -- -- ns
DB
0
(SO) Output Data Delay Time
t
DOD
-- -- 160 ns
DB
0
(SO) Output Data Hold Time
t
CDH
0 -- -- ns
V
IH
V
IL
V
IH
V
IL
RW/SI
V
IL
t
SCY
t
DOD
t
DOD
V
OL
V
OH
V
OH
t
CDH
RS
0
/CSB
DB
0
(SO)
E/SHTB
t
CSU
t
SSU
t
SWL
t
SR
t
SWH
t
SF
t
SH
t
CH
V
IH
V
IL
V
IH
V
IH
V
IH
V
IL
t
DISU
t
DIH
V
IH
t
CSWH
V
IH
V
IL
V
IH
V
IH
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FUNCTIONAL DESCRIPTION
Instruction Register (IR), Data Register (DR), and Expansion Instruction Register (ER)
These registers are selected by setting the level of the Register Selection input pins RS
0
/CSB and RS
1
. The DR is
selected when both RS
0
/CSB and RS
1
are "H". The IR is selected when RS
0
/CSB is "L" and RS
1
is "H". The ER
is selected when both RS
0
/CSB and RS
1
are "L". (When RS
0
/CSB is "H" and RS
1
is "L", the ML9042 is not
selected.)
The IR stores an instruction code and sets the address code of the display data RAM (DDRAM) or the character
generator RAM (CGRAM).
The microcontroller (CPU) can write but cannot read the instruction code.
The ER sets the display positions of the arbitrator and the address code of the arbitrator RAM (ABRAM).
The CPU can write but cannot read the display positions of the arbitrator.
The DR stores data to be written in the DDRAM, ABRAM and CGRAM and also stores data read from the
DDRAM, ABRAM and CGRAM.
The data written in the DR by the CPU is automatically written in the DDRAM, ABRAM or CGRAM.
When an address code is written in the IR or ER, the data of the specified address is automatically transferred from
the DDRAM, ABRAM or CGRAM to the DR. The data of the DDRAM, ABRAM and CGRAM can be checked
by allowing the CPU to read the data stored in the DR.
After the CPU writes data in the DR, the data of the next address in the DDRAM, ABRAM or CGRAM is selected
to be ready for the next writing by the CPU. Similarly, after the CPU reads the data in the DR, the data of the next
address in the DDRAM, ABRAM or CGRAM is set in the DR to be ready for the next reading by the CPU.
Writing in or reading from these 3 registers is controlled by changing the status of the RW/SI pin.
Table 1 RW/SI pin status and register operation
RW/SI RS
0
/CSB RS
1
Operation
L
L
H
Writing in the IR
H
L
H
Reading the Busy flag (BF) and the address counter (ADC)
L
H
H
Writing in the DR
H
H
H
Reading from the DR
L
L
L
Writing in the ER
H L
L
Disabled (Not in a busy state, not performing the reads.
Note that the data bus goes into a high impedance state.)
L
H
L
Disabled (Not in a busy state, not performing the writes)
H H
L
Disabled (Not in a busy state, not performing the reads.
Note that the data bus goes into a high impedance state.)
Busy Flag (BF)
The status "1" of the Busy Flag (BF) indicates that the ML9042 is carrying out internal operation.
When the BF is "1", any new instruction is ignored.
When RW/SI = "H", RS
0
/CSB = "L" and RS
1
= "H", the data in the BF is output to the DB
7
.
New instructions should be input when the BF is "0".
When the BF is "1", the output code of the address counter (ADC) is undefined.
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Address Counter (ADC)
The address counter provides a read/write address for the DDRAM, ABRAM or CGRAM and also provides a
cursor display address.
When an instruction code specifying DDRAM, ABRAM or CGRAM address setting is input to the pre-defined
register, the register selects the specified DDRAM, ABRAM or CGRAM and transfers the address code to the
ADC. The address data in the ADC is automatically incremented (or decremented) by 1 after the display data is
written in or read from the DDRAM, ABRAM or CGRAM.
The data in the ADC is output to DB
0
(SO) to DB
6
when RW/SI = "H", RS
0
/CSB = "L", RS
1
= "H" and BF = "0".
Timing Generator
The timing generator generates timing signals for the internal operation of the ML9042 activated by the instruction
sent from the CPU or for the operation of the internal circuits of the ML9042 such as DDRAM, ABRAM,
CGRAM and CGROM. Timing signals are generated so that the internal operation carried out for LCD displaying
will not be interfered by the internal operation initiated by accessing from the CPU. For example, when the CPU
writes data in the DDRAM, the display of the LCD not corresponding to the written data is not affected.
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Display Data RAM (DDRAM)
This RAM stores the 8-bit character codes (see Table 2).
The DDRAM addresses correspond to the display positions (digits) of the LCD as shown below. The DDRAM
addresses (to be set in the ADC) are represented in hexadecimal.
MSB
LSB
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
Hexadecimal
Hexadecimal
2
0
ADC
0
1
0
0
1
0
1
ADC
(Example) Representation of DDRAM address = 12
1) Relationship between DDRAM addresses and display positions (1-line display mode)
00 01 02 03 04
12 13
Digit
1 2 3 4 5
19 20
Left
end
Right
end
Display position
DD RAM address (hexadecimal)
In the 1-line display mode, the ML9042 can display up to 20 characters from digit 1 to digit 20. While the
DDRAM has addresses "00" to "4F" for up to 80 character codes, the area not used for display can be used as a
RAM area for general data. When the display is shifted by instruction, the relationship between the LCD
display position and the DDRAM address changes as shown below:
4F 00 01 02
11 12
Digit
1 2 3 4
19 20
(Display shifted to the right)
01 02 03 04
13 14
Digit
1 2 3 4
05
5
19 20
(Display shifted to the left)
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2) Relationship between DDRAM addresses and display positions (2-line display mode)
In the 2-line mode, the ML9042 can display up to 40 characters (20 characters per line) from digit 1 to digit 20.
00 01 02 03 04
Digit
1 2 3 4 5
12 13
19 20
40 41 42 43 44
52 53
Line 1
Line 2
Display position
DD RAM
address (hexadecimal)
Note: The DDRAM address at digit 20 in the first line is not consecutive to the DDRAM address at
digit 1 in the second line.
When the display is shifted by instruction, the relationship between the LCD display position and the DDRAM
address changes as shown below:
27 00 01 02
Digit
1 2 3 4
11 12
19 20
67 40 41 42
51 52
Line 1
Line 2
01 02 03 04
Digit
1 2 3 4
13 14
19 20
41 42 43 44
03
5
43
05
5
45
53 54
Line 1
Line 2
(Display shifted to the right)
(Display shifted to the left)
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Character Generator ROM (CGROM)
The CGROM generates character patterns (5
8 dots, 240 patterns) from the 8-bit character code signals in the
DDRAM. The bank switching pin (ROM1S) can switch to the other ROM that generates character patterns (5
8
dots, 240 patterns), allowing a total of 480 characters to be controlled.
When the 8-bit character code corresponding to a character pattern in the CGROM is written in the DDRAM, the
character pattern is displayed in the display position specified by the DDRAM address.
Character codes 10 to FF are contained in the ROM area in the CG ROM.
The general character generator ROM codes are 01/11/21.
The relationship between character codes and general purpose character patterns in Bank0 (ROM0) and Bank1
(ROM1) are indicated in Table 2-1 and Table 2-2, respectively.
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Character Generator RAM (CGRAM)
The CGRAM is used to generate user-specific character patterns that are not in the CGROM. CGRAM (64 bytes =
512 bits) can store up to 8 character patterns (5
8 dots) .
When displaying a character pattern stored in the CGRAM, write an 8-bit character code (00 to 07 or 08 to 0F;
hex.) to the DDRAM. This enables outputting the character pattern to the LCD display position corresponding to
the DDRAM address.
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the
cursor or blink display should be inhibited while the ADC is holding a CGRAM or ABRAM address.
The following describes how character patterns are written in and read from the CGRAM. (See Tables 2-1 and
2-2.)
(1) A method of writing character patterns to the CGRAM from the CPU
The three CGRAM address bit weights 0 to 2 select one of the lines constituting a character pattern.
First, set the mode to increment or decrement from the CPU, and then input the CGRAM address.
Write each line of the character pattern in the CGRAM through DB
0
(SO) to DB
7
.
The data lines DB
0
(SO) to DB
7
correspond to the CGRAM data bit weights 0 to 7, respectively (see Table
3-1). Input data "1" represents the ON status of an LCD dot and "0" represents the OFF status. Since the
ADC is automatically incremented or decremented by 1 after the data is written to the CGRAM, it is not
necessary to set the CGRAM address again.
The bottom line of a character pattern (the CGRAM address bit weights 0 to 2 are all "1", which means 7
in hexadecimal) is the cursor line. The ON/OFF pattern of this line is ORed with the cursor pattern for
displaying on the LCD. Therefore, the pattern data for the cursor position should be all zeros to display
the cursor.
Whereas the data given by the CGRAM data bit weights 0 to 4 is output to the LCD as display data, the
data given by the CGRAM data bit weights 5 to 7 is not. Therefore, the CGRAM data bit weights 5 to 7
can be used as a RAM area.
(2) A method of displaying CGRAM character patterns on the LCD
The CGRAM is selected when the higher-order 4 bits of a character code are all zeros. Since bit weight 3
of a character code is not used, the character pattern "0" in Table 3-1 can be selected using the character
code "00" or "08" in hexadecimal.
When the 8-bit character code corresponding to a character pattern in the CGRAM is written to the
DDRAM, the character pattern is displayed in the display position specified by the DDRAM address.
(The DDRAM data bit weights 0 to 2 correspond to the CGRAM address bit weights 3 to 5, respectively.)
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Arbitrator RAM (ABRAM)
The arbitrator RAM (ABRAM) stores arbitrator display data.
100 dots can be displayed in both 1-line and 2-line display modes. The arbitrator RAM has the addresses
(hexadecimal) from "00" to "1F" and the valid display address area is from 00 to 19 (0H to 13H). The area of 20 to
31 (14H to 1FH) not used for display can be used as a data RAM area for general data. Even if the display is shifted
by instruction, the arbitrator display is not shifted.
A capacity of 8 bits by 32 addresses (= 256 bits) is available for data write.
First set the mode to increment or decrement from the CPU, and then input the ABRAM address.
Write Display-ON data in the ABRAM through DB
0
(SO) to DB
7
.
DB
0
(SO) to DB
7
correspond to the ABRAM data bit weights 0 to 7 respectively. Input data "1" represents the ON
status of an LCD dot and "0" represents the OFF status.
Since ADC is automatically incremented or decremented by 1 after the data is written to the ABRAM, it is not
necessary to set the ABRAM address again.
Whereas ABRAM data bit weights 0 to 4 are output as display data to the LCD, the ABRAM data bit weights 5 to
7 are not. These bits can be used as a RAM area.
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the
cursor or blink display should be inhibited while the ADC is holding a CGRAM or ABRAM address.
MSB
LSB
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
Hexadecimal
Hexadecimal
ADC
The arbitrator RAM can store a maximum of 100 dots of the arbitrator Display-ON data in units of 5 dots.
The relationship with the LCD display positions is shown below.
* * E4 E3 E2 E1 E0
DB
6
*
DB
7
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
* Don't Care
Display - ON data
E4
E0
5XSn+1
5XSn+5
Configuration of input display data
Input data
Relationship between display-ON
data and segment pins
Sn = ABRAM address (0 to 19)
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Note: The same CGRAM character patterns are displayed in Bank0 and Bank1.
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Table 3-1 Relationship between CGRAM address bits, CGRAM data bits (character pattern)
and DDRAM data bits (character code) in 5
7 dot character mode. (Examples)
CG RAM data
(Character pattern)
(Character code)
DD RAM data
0 1 1 1 0
1 0 0 0 1
1 0 0 0 1
1 0 0 0 1
1 0 0 0 1
1 0 0 0 1
0 1 1 1 0
0 0 0 0 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
LSB MSB
LSB MSB
LSB
0 0 0 0
0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 0 1 0 0
1 0 0 1 0
1 0 0 0 1
0 0 0 0 0
0 0 0 0
0 0 1
0 1 1 1 0
0 0 1 0 0
0 0 1 0 0
0 0 1 0 0
0 0 1 0 0
0 0 1 0 0
0 1 1 1 0
0 0 0 0 0
0 0 0 0
1 1 1
CG RAM
address
5 4 3 2 1 0
MSB
0 0 0 0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 1 0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1 1 1 0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
: Don't Care
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Cursor/Blink Control Circuit
This circuit generates the cursor and blink of the LCD.
The operation of this circuit is controlled by the program of the CPU.
The cursor/blink display is carried out in the position corresponding to the DDRAM address set in the ADC
(Address Counter).
For example, when the ADC stores a value of "07" (hexadecimal), the cursor or blink is displayed as follows:
0
DB
6
DB
0
0 0 0 1 1 1
7
0
00 01 02 03 04
07 08
Digit
1 2 3 4 5
8 9
Cursor/blink position
12 13
19 20
6 7
05 06
00 01 02 03 04
07 08
Digit
1 2 3 4 5
8 9
Cursor/blink position
12 13
19 20
6 7
05 06
40 41 42 43 44
47 48
52 53
45 46
First line
ADC
In 1-line display mode
In 2-line display mode
Second line
Note: The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in
the ADC. Therefore, the cursor or blink display should be inhibited while the ADC is
holding a CGRAM or ABRAM address.
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LCD Display Circuit (COM1 to COM17, SEG1 to SEG100, SSR and CSR)
The ML9042 has 17 common signal outputs and 100 segment signal outputs to display 20 characters (in the 1-line
display mode) or 40 characters (in the 2-line display mode).
The character pattern is converted into serial data and transferred in series through the shift register.
The transfer direction of serial data is determined by the SSR bit. The shift direction of common signals is
determined by the CSR bit. The following tables show the transfer and shift directions:
SSR bit
Transfer direction
L SEG
1
SEG
100
H SEG
100
SEG
1
ABE bit
CSR bit
duty
AS bit
Shift Direction
Arbitrator's common pin
L L
1/8
L COM1
COM8 None
L L
1/8
H COM1
COM8 None
L L
1/16
L COM1
COM16 None
L L
1/16
H COM1
COM16 None
L H
1/8
L COM8
COM1 None
L H
1/8
H COM8
COM1 None
L H
1/16
L COM16
COM1 None
L H
1/16
H COM16
COM1 None
H L
1/9
L COM1
COM9 COM9
H L
1/9
H COM1
COM9 COM1
H L
1/17
L COM1
COM17 COM17
H L
1/17
H COM1
COM17 COM1
H H
1/9
L COM9
COM1 COM1
H H
1/9
H COM9
COM1 COM9
H H
1/17
L COM17
COM1 COM1
H H
1/17
H COM17
COM1 COM17
* Refer to the Expansion Instruction Codes section about the ABE bit, SSR bit, CSR bit, and AS bit.
Signals to be input to the SSR bit, CSR bit, ABE bit, and AS bit should be initially determined at power-on and be
kept unchanged.
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Built-in Reset Circuit
The ML9042 is automatically initialized when the power is turned on.
During initialization, the Busy Flag (BF) is "1" and the ML9042 does not accept any instruction from the CPU
(other than the Read BF instruction).
The Busy Flag is "1" for about 15 ms after the V
DD
becomes 2.7 V or higher.
During this initialization, the ML9042 performs the following instructions:
1) Display
clearing
2) CPU interface data length = 8 bits
(DL = "1")
3) 1-line LCD display
(N = "0")
4) ADC counting = Increment
(I/D = "1")
5) Display shifting = None
(S = "0")
6) Display = Off
(D = "0")
7) Cursor = Off
(C = "0")
8) Blinking = Off
(B = "0")
9) Arbitrator = Displayed in the lower line
(AS = "0")
10) Arbitrator = Not displayed
(ABE = "0")
11) Segment shift direction = SEG
1
SEG
100
(SSR = "0")
12) Common shift direction = COM
1
COM
17
(CSR = "0")
To use the built-in reset circuit, the power supply conditions shown below should be satisfied. Otherwise, the
built-in reset circuit may not work properly. In such a case, initialize the ML9042 with the instructions from the
CPU. The use of a battery always requires such initialization from the CPU. (See "Initial Setting of Instructions")
t
ON
2.7 V
0.2 V
0.2 V
0.2 V
t
OFF
0.1 ms
t
ON
100 ms
1 ms
t
OFF
Figure 1 Power-on and Power-off Waveform
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I/F with CPU
Parallel interface mode
The ML9042 can transfer either 8 bits once or 4 bits twice on the data bus for interfacing with any 8-bit or 4-bit
microcontroller (CPU).
1) 8-bit interface data length
The ML9042 uses all of the 8 data bus lines DB
0
(SO) to DB
7
at a time to transfer data to and from the CPU.
2) 4-bit interface data length
The ML9042 uses only the higher-order 4 data bus lines DB
4
to DB
7
twice to transfer 8-bit data to and from the
CPU.
The ML9042 first transfers the higher-order 4 bits of 8-bit data (DB
4
to DB
7
in the case of 8-bit interface data
length) and then the lower-order 4 bits of the data (DB
0
(SO) to DB
3
in the case of 8-bit interface data length).
The lower-order 4 bits of data should always be transferred even when only the transfer of the higher-order 4
bits of data is required. (Example: Reading the Busy Flag)
Two transfers of 4 bits of data complete the transfer of a set of 8-bit data. Therefore, when only one access is
made, the following data transfer cannot be completed properly.
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RS
0
/CSB
RWB/SI
E/SHTB
Busy
(Internal operation)
IR
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
/(SO)
DB
7
Busy
No
Busy
DR
7
IR
6
DR
6
ADC
6
IR
5
DR
5
ADC
5
IR
4
DR
4
ADC
4
IR
3
DR
3
ADC
3
IR
2
DR
2
ADC
2
IR
1
DR
1
ADC
1
IR
0
DR
0
ADC
0
RS
1
Writing In IR
(Instruction
Register)
Reading BF (Busy Flag)
and ADC (Address Counter)
Writing In DR
(Data Register)
Figure 2 8-Bit Data Transfer
RS
0
/CSB
RWB/SI
E/SHTB
Busy
(Internal operation)
DB
7
DB
6
DB
5
DB
4
IR
7
Busy
No
Busy
DR
7
DR
3
ADC
3
ADC
5
DR
6
DR
2
ADC
2
DR
5
DR
1
ADC
1
ADC
4
DR
4
DR
0
ADC
0
ADC
6
IR
3
IR
6
IR
2
IR
5
IR
1
IR
4
IR
0
RS
1
Writing In IR
(Instruction
Register)
Reading BF (Busy Flag)
and ADC (Address Counter)
Writing In DR
(Data Register)
Figure 3 4-Bit Data Transfer
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Serial Interface Mode
In the Serial I/F Mode, the ML9042 interfaces with the CPU via the RS
0
/CSB, E/SHTB, RW/SI, and DB
0
(SO)
pins.
Writing and reading operations are executed in units of 16 bits after the RS
0
/CSB signal falls down. If the RS
0
/CSB
signal rises up before the completion of 16-bit unit access, this access is ignored.
When the BF bit is "1", the ML9042 cannot accept any other instructions. Before inputting a new instruction,
check that the BF bit is "0". Any access when the BF bit is "1" is ignored.
Data format is LSB-first.
Examples of Access in the Serial I/F Mode
Note 1: Higher 5 bits of each instruction must be input at a "H" level.
Note 2: Lower 8 bits are "don't care" when the instructions in the READ MODE are set.
Note 3: After one instruction is input, the next instruction must be input after the RS
0
/CSB pin is pulled at a "H"
level.
1) WRITE MODE
RS
0
/CSB
E/SHTB
BUSY
RWB/SI
DB(SO)
2) READ MODE
RS
0
/CSB
E/SHTB
BUSY
RWB/SI
DB(SO)
(Internal operation)
(Internal operation)
1
2
1
2
3
4
5
6
7
8
1
13
14
15
16
9
10
11
12
1
1
1
1
1
R/
W
RS0 RS1
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
1
1
1
1
1
R/
W
RS0 RS1
1
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
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Instruction Codes
Table of Instruction Codes
Code
Instruction
RS
1
RS
0
/
CSB
RW/
SI
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
(SO)
Function
Execution
Time
f = 270 kHz
Display Clear
1
0
0
0
0
0
0
0
0
0
1
Clears all the displayed digits of the
LCD and sets the DDRAM address 00
in the address counter. The arbitrator
data is cleared.
1.52 ms
Cursor Home
1
0
0
0
0
0
0
0
0
1
X
Sets the DDRAM address 00 in the
address counter and shifts the display
back to the original. The content of the
DDRAM remains unchanged.
1.52 ms
Entry Mode
Setting
1 0 0 0 0 0 0 0 1 I/D S
Determines the direction of movement
of the cursor and whether or not to shift
the display. This instruction is
executed when data is written or read.
37
s
Display
ON/OFF Control
1 0 0 0 0 0 0 1 D C B
Sets LCD display ON/OFF (D), cursor
ON/OFF (C) or cursor-position
character blinking ON/OFF (B).
37
s
Cursor/Display
Shift
1 0 0 0 0 0 1 S/C R/L
X X
Moves the cursor or shifts the display
without changing the content of the
DDRAM.
37
s
Function Setting 1
0
0
0
0
1
DL
N ABE SSR CSR
Sets the interface data length (DL), the
number of display lines (N), the
arbitrator display (ABE), the segment
data shift direction (SSR), or the
common data shift direction (CSR).
37
s
CGRAM
Address Setting
1 0 0 0 1
ACG
Sets on CGRAM address. After that,
CGRAM data is transferred to and from
the CPU.
37
s
DDRAM
Address Setting 1 0 0 1
ADD
Sets a DDRAM address. After that,
DDRAM data is transferred to and from
the CPU.
37
s
Busy Flag/
Address Read
1 0 1 BF
ADC
Reads the Busy Flag (indicating that
the ML9042 is operating) and the
content of the address counter.
0
s
RAM Data Write 1
1
0
WRITE DATA
Writes data in DDRAM, ABRAM or
CGRAM.
37
s
RAM Data Read 1
1
1
READ DATA
Reads data from DDRAM, ABRAM or
CGRAM.
37
s
Arbitrator
Display Line Set
0
0
0
0
0
0
0
0
0
1
AS Sets the arbitrator display line.
37
s
ABRAM
Address Setting
0 0 0 0 1 1
AAB
Sets an ABRAM address. After that,
ABRAM data is transferred to and from
the CPU.
37
s
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--
I/D = "1" (Increment)
I/D = "0" (Decrement)
S = "1" (Shifts the display.)
S/C = "1" (Shifts display.)
S/C = "0" (Moves the cursor.)
R/L = "1" (Right shift)
R/L = "0" (Left shift)
D/L = "1" (8-bit data)
DL = "0" (4-bit data)
N = "1" (2 lines)
N = "0" (1 line)
ABE = "1" (Arbitrator displayed)
ABE = "0" (Arbitrator not displayed)
SSR = "1" (Transfer direction: SEG
100
SEG
1
)
SSR = "0" (Transfer direction: SEG
1
SEG
100
)
CSR = "1" (Transfer direction: COMn
COM1)
CSR = "0" (Transfer direction: COM1
COMn)
BF = "1" (Busy)
BF = "0" (Ready to accept
an
instruction)
B = "1" (Enables blinking)
C = "1" (Displays the cursor.)
D = "1" (Displays a character pattern.)
AS = "1" (Arbitrator Displays AS = "0" (Arbitrator Displays
arbitrator on the
arbitrator on the
upper line)
lower line)
DD RAM: Display data RAM
CG RAM: Character generator RAM
ABRAM: Arbitrator data RAM
ACG:
CGRAM address
ADD: DDRAM
address
(Corresponds to the cursor
address)
AAB:
ABRAM address
ADC:
Address counter (Used by
DDRAM, ABRAM and
CGRAM)
The
execution
time is
dependent
upon
frequen-
cies.
: Don't Care
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Instruction Codes
An instruction code is a signal sent from the CPU to access the ML9042. The ML9042 starts operation as
instructed by the code received. The busy status of the ML9042 is rather longer than the cycle time of the CPU,
since the internal processing of the ML9042 starts at a timing which does not affect the display on the LCD. In the
busy status (Busy Flag is "1"), the ML9042 cannot input the Busy Flag Read instruction only. Therefore, the CPU
should ensure that the Busy Flag is "0" before sending an instruction code to the ML9042.
1) Display Clear
RS
1
1
RS
0
0
R/
W
0
DB
7
0
DB
6
0
DB
5
0
DB
4
0
DB
3
0
DB
2
0
DB
1
0
DB
0
1
Instruction Code:
When this instruction is executed, the LCD display including arbitrator display is cleared and the I/D entry
mode is set to "Increment". The value of "S" (Display shifting) remains unchanged. The position of the cursor
or blink being displayed moves to the left end of the LCD (or the left end of the line 1 in the 2-line display
mode).
Note: All DDRAM and ABRAM data turn to "20" and "00" in hexadecimal, respectively. The value of the
address counter (ADC) turns to the one corresponding to the address "00" (hexadecimal) of the
DDRAM.
The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency of 270 kHz.
2) Cursor Home
RS
1
1
RS
0
0
R/
W
0
DB
7
0
DB
6
0
DB
5
0
DB
4
0
DB
3
0
DB
2
0
DB
1
1
DB
0
Instruction code:
: Don't Care
When this instruction is executed, the cursor or blink position moves to the left end of the LCD (or the left end
of line 1 in the 2-line display mode). If the display has been shifted, the display returns to the original display
position before shifting.
Note: The value of the address counter (ADC) goes to the one corresponding to the address "00"
(hexadecimal) of the DDRAM).
The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency of 270 kHz.
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3) Entry Mode Setting
RS
1
1
RS
0
0
R/
W
0
DB
7
0
DB
6
0
DB
5
0
DB
4
0
DB
3
0
DB
2
1
DB
1
I/D
DB
0
S
Instruction code:
(1) When the I/D is set, the cursor or blink shifts to the right by 1 character position (ID= "1"; increment) or to
the left by 1 character position (I/D= "0"; decrement) after an 8-bit character code is written to or read
from the DDRAM. At the same time, the address counter (ADC) is also incremented by 1 (when I/D =
"1"; increment) or decremented by 1 (when I/D = "0"; decrement). After a character pattern is written to
or read from the CGRAM, the address counter (ADC) is incremented by 1 (when I/D = "1"; increment) or
decremented by 1 (when I/D = "0"; decrement).
Also after data is written to or read from the ABRAM, the address counter (ADC) is incremented by 1
(when I/D = "1"; increment) or decremented by 1 (when I/D = "0"; decrement).
(2) When S = "1", the cursor or blink stops and the entire display shifts to the left (I/D = "1") or to the right
(I/D = "0") by 1 character position after a character code is written to the DDRAM.
In the case of S = "1", when a character code is read from the DDRAM, when a character pattern is
written to or read from the CGRAM or when data is written to or read from the ABRAM, normal
read/write is carried out without shifting of the entire display. (The entire display does not shift, but the
cursor or blink shifts to the right (I/D = "1") or to the left (I/D = "0") by 1 character position.)
When S = "0", the display does not shift, but normal write/read is performed.
Note: The execution time of this instruction is 37
s (maximum) at an oscillation frequency of
270 kHz.
4) Display ON/OFF Control
RS
1
1
RS
0
0
R/
W
0
DB
7
0
DB
6
0
DB
5
0
DB
4
0
DB
3
1
DB
2
D
DB
1
C
DB
0
B
Instruction code:
(1) The "D" bit (DB2) of this instruction determines whether or not to display character patterns on the LCD.
When the "D" bit is "1", character patterns are displayed on the LCD.
When the "D" bit is "0", character patterns are not displayed on the LCD and the cursor/blinking also
disappear.
Note: Unlike the Display Clear instruction, this instruction does not change the character code in the
DDRAM .
(2) When the "C" bit (DB1) is "0", the cursor turns off. When both the "C" and "D" bits are "1", the cursor
turns on.
(3) When the "B" bit (DB0) is "0", blinking is canceled. When both the "B" and "D" bits are "1", blinking is
performed.
In the Blinking mode, all dots including those of the cursor, the character pattern and the cursor are
alternately displayed.
Note: The execution time of this instruction is 37
s (maximum) at an oscillation frequency of
270 kHz.
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5) Cursor/Display Shift
RS
1
1
RS
0
0
R/
W
0
DB
7
0
DB
6
0
DB
5
0
DB
4
1
DB
3
S/C
DB
2
R/L
DB
1
DB
0
Instruction code:
: Don't Care
S/C = "0", R/L = "0"
This instruction shifts left the cursor and blink positions by 1 (decrements the
content of the ADC by 1).
S/C = "0", R/L = "1"
This instruction shifts right the cursor and blink positions by 1 (increments the
content of the ADC by 1).
S/C = "1", R/L = "0"
This instruction shifts left the entire display by 1 character position. The cursor
and blink positions move to the left together with the entire display.
The Arbitrator display is not shifted.
(The content of the ADC remains unchanged.)
S/C = "1", R/L = "1"
This instruction shifts right the entire display by 1 character position. The cursor
and blink positions move to the right together with the entire display.
The Arbitrator display is not shifted.
(The content of the ADC remains unchanged.)
In the 2-line mode, the cursor or blink moves from the first line to the second line when the cursor at digit 40
(27; hex) of the first line is shifted right.
When the entire display is shifted, the character pattern, cursor or blink will not move between the lines (from
line 1 to line 2 or vice versa).
Note: The execution time of this instruction is 37
s at an oscillation frequency (OSC) of 270 kHz.
6) Function Setting
RS
1
1
RS
0
0
R/
W
0
DB
7
0
DB
6
0
DB
5
1
DB
4
DL
DB
3
N
DB
2
ABE
DB
1
SSR
DB
0
CSR
: Don't Care
Instruction code:
(1) When the "DL" bit (DB
4
) of this instruction is "1", the data transfer to and from the CPU is performed
once by the use of 8 bits DB
7
to DB
0
.
When the "DL" bit (DB
4
) of this instruction is "0", the data transfer to and from the CPU is performed
twice by the use of 4 bits DB
7
to DB
4
.
(2) The 2-line display mode is selected when the "N" bit (DB
3
) of this instruction is "1". The 1-line display
mode is selected when the "N" bit is "0".
The arbitrator is displayed when the "ABE" bit (DB
2
) of this instruction is "1".
The arbitrator is not displayed when the "ABE" bit (DB
2
) of this instruction is "0".
(3) The transfer direction of the segment signal output data is controlled.
When the "SSR" bit (DB
1
) of this instruction is "1", the data is transferred from
SEG
100
to SEG
1
.
When the "SSR" bit (DB
1
) of this instruction is "0", the data is transferred from
SEG
1
to SEG
100
.
The transfer direction of the common signal output data is controlled.
At 1/n duty,
When the "CSR" bit (DB
0
) of this instruction is "1", the data is transferred from
COMn to COM1
.
When the "CSR" bit (DB
0
) of this instruction is "0", the data is transferred from
COM1 to COMn
.
After the ML9042 is powered on, this function setting should be carried out before execution of any
instruction except the Busy Flag Read. After this function setting, no instructions other than the DL Set
instruction can be executed. In the Serial I/F Mode, DL setting is ignored.
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N ABE
Number of
display lines
Font size
Duty
Number of
biases
Number of
common signals
0 0
1
5
8
1/8
4
8
0 1
1
5
8
1/9
4
9
1 0
2
5
8
1/16
5
16
1 1
2
5
8
1/17
5
17
Note: The execution time of this instruction is 37
s at an oscillation frequency (OSC) of 270
kHz.
7) CGRAM Address Setting
RS
1
1
RS
0
0
R/
W
0
DB
7
0
DB
6
1
DB
5
C
5
DB
4
C
4
DB
3
C
3
DB
2
C
2
DB
1
C
1
DB
0
C
0
Instruction code:
This instruction sets the CGRAM address to the data represented by the bits C
5
to C
0
(binary).
The CGRAM addresses are valid until DDRAM or ABRAM addresses are set.
The CPU writes or reads character patterns starting from the one represented by the CGRAM address bits C
5
to
C
0
set in the instruction code at that time.
Note: The execution time of this instruction is 37
s at an oscillation frequency (OSC) of 270 kHz.
8) DDRAM Address Setting
RS
1
1
RS
0
0
R/
W
0
DB
7
1
DB
6
D
6
DB
5
D
5
DB
4
D
4
DB
3
D
3
DB
2
D
2
DB
1
D
1
DB
0
D
0
Instruction code:
This instruction sets the DDRAM address to the data represented by the bits D
6
to D
0
(binary).
The DDRAM addresses are valid until CGRAM or ABRAM addresses are set.
The CPU writes or reads character codes starting from the one represented by the DDRAM address bits D
6
to
D
0
set in the instruction code at that time.
In the 1-line mode (the "N" bit is "0"), the DDRAM address represented by bits D
6
to D
0
(binary) should be in
the range "00" to "4F" in hexadecimal.
In the 2-line mode (the "N" bit is "1"), the DDRAM address represented by bits D
6
to D
0
(binary) should be in
the range "00" to "27" or "40" to "67" in hexadecimal.
If an address other than above is input, the ML9042 cannot properly write a character code in or read it from the
DDRAM.
Note: The execution time of this instruction is 37
s at an oscillation frequency (OSC) of 270 kHz.
9) DDRAM/ABRAM/CGRAM Data Write
RS
1
1
RS
0
1
R/
W
0
DB
7
E
7
DB
6
E
6
DB
5
E
5
DB
4
E
4
DB
3
E
3
DB
2
E
2
DB
1
E
1
DB
0
E
0
Instruction code:
A character code (E
7
to E
0
) is written to the DDRAM, Display-ON data (E
7
to E
0
) to the ABRAM or a character
pattern (E
7
to E
0
) to the CGRAM.
The DDRAM, ABRAM or CGRAM is selected at the preceding address setting.
After data is written, the address counter (ADC) is incremented or decremented as set by the Entry Mode
Setting instruction (see 3).
Note: The execution time of this instruction is 37
s at an oscillation frequency (OSC) of 270 kHz.
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10) Busy Flag/Address Counter Read (Execution time: 0
s)
RS
1
1
RS
0
0
R/
W
1
DB
7
BF
DB
6
O
6
DB
5
O
5
DB
4
O
4
DB
3
O
3
DB
2
O
2
DB
1
O
1
DB
0
O
0
Instruction code:
The "BF" bit (DB7) of this instruction tells whether the ML9042 is busy in internal operation (BF = "1") or not
(BF = "0").
When the "BF" bit is "1", the ML9042 cannot accept any other instructions. Before inputting a new instruction,
check that the "BF" bit is "0".
When the "BF" bit is "0", the ML9042 outputs the correct value of the address counter. The value of the
address counter is equal to the DDRAM, ABRAM or CGRAM address. Which of the DDRAM, ABRAM and
CGRAM addresses is set in the counter is determined by the preceding address setting.
When the "BF" bit is "1", the value of the address counter is not always correct because it may have been
incremented or decremented by 1 during internal operation.
11) DDRAM/ABRAM/CGRAM Data Read
RS
1
1
RS
0
1
R/
W
1
DB
7
P
7
DB
6
P
6
DB
5
P
5
DB
4
P
4
DB
3
P
3
DB
2
P
2
DB
1
P
1
DB
0
P
0
Instruction code:
A character code (P
7
to P
0
) is read from the DDRAM, Display-ON data (P
7
to P
0
) from the ABRAM or a
character pattern (P
7
to P
0
) from the CGRAM.
The DDRAM, ABRAM or CGRAM is selected at the preceding address setting.
After data is read, the address counter (ADC) is incremented or decremented as set by the Entry Mode Setting
instruction (see 3).
Note: Conditions for reading correct data
(1) The DDRAM, ABRAM or CGRAM Setting instruction is input before this data read instruction is input.
(2) When reading a character code from the DDRAM, the Cursor/Display Shift instruction (see 5) is input
before this Data Read instruction is input.
(3) When two or more consecutive RAM Data Read instructions are executed, the following read data is
correct.
Correct data is not output under conditions other than the cases (1), (2) and (3) above.
Note: The execution time of this instruction is 37
s at an oscillation frequency (OSC) of 270 kHz.
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Expansion Instruction Codes
The busy status of the ML9042 is rather longer than the cycle time of the CPU, since the internal processing of the
ML9042 starts at a timing which does not affect the display on the LCD. In the busy status (Busy Flag is "1"), the
ML9042 executes the Busy Flag Read instruction only. Therefore, the CPU should ensure that the Busy Flag is
"0" before sending an expansion instruction code to the ML9042.
1) Arbitrator Display Line Set
RS
1
0
RS
0
0
R/
W
0
DB
7
0
DB
6
0
DB
5
0
DB
4
0
DB
3
0
DB
2
0
DB
1
1
DB
0
AS
Expansion instruction code:
This expansion instruction code sets the Arbitrator display line. The relationship between the status of this bit
and the common outputs is as follows:
For display examples, refer to LCD Drive Waveforms section.
ABE bit
CSR bit
duty
AS bit
Shift direction
Arbitrator's common pin
L L 1/8 L
COM1
COM8 None
L L 1/8 H COM1
COM8 None
L L
1/16 L COM1
COM16 None
L L
1/16
H COM1
COM16 None
L H 1/8 L
COM8
COM1 None
L H 1/8 H
COM8
COM1 None
L H
1/16 L COM16
COM1 None
L H
1/16 H COM16
COM1 None
H L 1/9 L
COM1
COM9 COM9
H L 1/9 H
COM1
COM9 COM1
H L
1/17 L COM1
COM17 COM17
H L
1/17 H COM1
COM17 COM1
H H 1/9 L
COM9
COM1 COM1
H H 1/9 H
COM9
COM1 COM9
H H
1/17 L COM17
COM1 COM1
H H
1/17 H COM17
COM1 COM17
Note:
The execution time of this instruction is 37
s at an oscillation frequency (OSC) of
270
kHz.
2) ABRAM Address Setting
RS
1
0
RS
0
0
R/
W
1
DB
7
0
DB
6
1
DB
5
1
DB
4
H
4
DB
3
H
3
DB
2
H
2
DB
1
H
1
DB
0
H
0
Expansion instruction code:
This instruction sets the ABRAM address to the data represented by the bits H
4
to H
0
(binary).
The ABRAM addresses are valid until CGRAM or DDRAM addresses are set.
The CPU writes or reads the Display-ON data starting from the one represented by the ABRAM address bits H
4
to H
0
set in the instruction code at that time.
When the ABRAM address represented by bits H
4
to H
0
(binary) is in the range "00" to "13" in hexadecimal,
data is output to the LCD as the arbitrator.
Note: The execution time of this instruction is 37
s at an oscillation frequency (OSC) of 270 kHz.
FEDL9042-01
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ML9042-xx
38/58
Examples of Combinations of ML9042 and LCD Panel
(1) Driving the LCD of one 20-character line under the conditions of the 1-line display mode and no arbitrator
display
(1/8 duty, ABE = "0", AS = "0" or "1", CSR = "0", SSR = "1")
COM
1
Character
COM
8
SEG
100
SEG
1
ML9042
COM
9
to COM
17
output Display-OFF common signals.
(1/8 duty, ABE = "0", AS = "0" or "1", CSR = "1", SSR = "0")
COM
8
Character
COM
1
SEG
1
SEG
100
ML9042
COM
9
to COM
17
output Display-OFF common signals.
FEDL9042-01
OKI Semiconductor
ML9042-xx
39/58
(2) Driving the LCD of one 20-character line under the conditions of the 1-line display mode and the arbitrator
display
(1/9 duty, ABE = "1", AS = "0", CSR = "0", SSH = "1")
COM
1
COM
8
COM
9
SEG
100
SEG
1
ML9042
Character
Arbitrator
COM
10
to COM
17
output Display-OFF common signals.
(1/9 duty, ABE = "1", AS = "1", CSR = "0", SSR = "1")
COM
1
COM
2
COM
9
SEG
100
SEG
1
ML9042
Character
Arbitrator
COM
10
to COM
17
output Display-OFF common signals.
FEDL9042-01
OKI Semiconductor
ML9042-xx
40/58
(1/9 duty, ABE = "1", AS = "0", CSR = "1", SSR = "0")
COM
9
COM
2
COM
1
SEG
1
SEG
100
ML9042
Character
Arbitrator
COM
10
to COM
17
output Display-OFF common signals.
(1/9 duty, ABE = "1", AS = "1", CSR = "1", SSR = "0")
COM
9
COM
8
COM
1
SEG
1
SEG
100
ML9042
Character
Arbitrator
COM
10
to COM
17
output Display-OFF common signals.
FEDL9042-01
OKI Semiconductor
ML9042-xx
41/58
(3) Driving the LCD of two 20-character lines under the conditions of the 2-line display mode and no arbitrator
display
(1/16 duty, ABE = "0", AS = "0" or "1", CSR = "0", SSR = "1")
COM
1
COM
8
SEG
100
SEG
1
ML9042
COM
9
COM
16
Character
Character
COM
17
outputs Display-OFF common signal.
(1/16 duty, ABE = "0", AS = "0" or "1", CSR = "1", SSR = "0")
COM
16
COM
9
SEG
1
SEG
100
ML9042
COM
8
COM
1
Character
Character
COM
17
outputs Display-OFF common signal.
FEDL9042-01
OKI Semiconductor
ML9042-xx
42/58
(4) Driving the LCD of two 20-character lines under the conditions of the 2-line display mode and the arbitrator
display
(1/17 duty, ABE = "1", AS = "0", CSR = "0", SSR = "1")
COM
1
COM
8
SEG
100
SEG
1
ML9042
COM
9
COM
16
COM
17
Character
Character
Arbitrator
(1/17 duty, ABE = "1", AS = "1", CSR = "0", SSR = "1")
COM
2
COM
1
COM
9
SEG
100
SEG
1
ML9042
COM
10
COM
17
Character
Character
Arbitrator
FEDL9042-01
OKI Semiconductor
ML9042-xx
43/58
(1/17 duty, ABE = "1", AS = "0", CSR = "1", SSR = "0")
COM
17
COM
10
SEG
1
SEG
100
ML9042
COM
9
COM
1
Character
Character
Arbitrator
COM
2
(1/17 duty, ABE = "1", AS = "1", CSR = "1", SSR = "0")
COM
16
COM
17
COM
9
SEG
1
SEG
100
ML9042
COM
8
COM
1
Character
Character
Arbitrator
FEDL9042-01
OKI Semiconductor
ML9042-xx
44/58
EXAMPLES OF VLCD GENERATION CIRCUITS
With 1/4 bias, a voltage multiplier
ML9042
BE
V
IN
V
CC
V
C
GND
V
0
V
4
V
3B
V
3A
V
2
V
1
V
DD
Reference potential
for voltage multiplier
V
OUT
+
+
With 1/4 bias, no voltage multiplier
1) Apply V
DD
to V
OUT
and V
0.
2) Apply V
DD
to V
OUT
, and apply the V
0
level to V
0
externally.
ML9042
BE
V
IN
V
CC
V
C
GND
V
0
V
4
V
3B
V
3A
V
2
V
1
V
DD
V
0
level
V
OUT
FEDL9042-01
OKI Semiconductor
ML9042-xx
45/58
With 1/5 bias, a voltage multiplier
ML9042
BE
V
IN
V
CC
V
C
GND
V
0
V
4
V
3B
V
3A
V
2
V
1
V
DD
Reference potential
for voltage multiplier
V
OUT
+
+
With 1/5 bias, no voltage multiplier
1) Apply V
DD
to V
OUT
and V
0.
2) Apply V
DD
to V
OUT
, and apply the V
0
level to V
0
externally.
ML9042
BE
V
IN
V
CC
V
C
GND
V
0
V
4
V
3B
V
3A
V
2
V
1
V
DD
V
0
level
V
OUT
FEDL9042-01
OKI Semiconductor
ML9042-xx
46/58
LCD Drive Waveforms
The COM and SEG waveforms (AC signal waveforms for display) vary according to the duty (1/9 and 1/17 duties).
See 1) and 2) below.
The relationship between the duty ratio and the frame frequency is as follows:
Duty ratio
Frame Frequency
1/8 84.4
Hz
1/9 75.0
Hz
1/16 84.4
Hz
1/17 79.4
Hz
Note: At an oscillation frequency (OSC) of 270 kHz
1) COM and SEG Waveforms on 1/9 Duty (ABE = "1")
V
0
1 frame
V
1
V
2
, V
3B
V
4
V
5
V
0
V
1
V
2
, V
3B
V
4
V
5
V
0
V
1
V
2
, V
3B
V
4
V
5
V
0
V
1
V
2
, V
3B
V
4
V
5
COM
1
(CSR = "L", AS = "L")
COM
2
(CSR = "L", AS = "H")
COM
9
(CSR = "H", AS = "L")
COM
8
(CSR = "H", AS = "H")
(first character line)
COM
2
(CSR = "L", AS = "L")
COM
3
(CSR = "L", AS = "H")
COM
8
(CSR = "H", AS = "L")
COM
7
(CSR = "H", AS = "H")
(second character line)
COM
8
(CSR = "L", AS = "L")
COM
9
(CSR = "L", AS = "H")
COM
2
(CSR = "H", AS = "L")
COM
1
(CSR = "H", AS = "H")
(eighth character line)
COM
9
(CSR = "L", AS = "L")
COM
1
(CSR = "L", AS = "H")
COM
1
(CSR = "H", AS = "L")
COM
9
(CSR = "H", AS = "H")
(arbitrator line)
V
0
V
1
V
2
, V
3B
V
4
V
5
COM
10
to
COM
17
V
0
V
1
V
2
, V
3B
V
4
V
5
SEG
Display
turning-off
waveform
Display
turning-on
waveform
8 9 1 2 3 4 7 8 9 1 2 3 4 7 8 9 1 2
2 1 9 8 7 6 3 2 1 9 8 7 6 3 2 1 9 8
CSR="H"
CSR="L"
FEDL9042-01
OKI Semiconductor
ML9042-xx
47/58
2) COM and SEG Waveforms on 1/17 Duty (ABE = "1")
V
0
1 frame
V
1
V
2
V
3A
(V
3B
)
V
4
Display
turning-off
waveform
Display
turning-on
waveform
V
5
V
0
V
1
V
2
V
3A
(V
3B
)
V
4
V
5
V
0
V
1
V
2
V
3A
(V
3B
)
V
4
V
5
V
0
V
1
V
2
V
3A
(V
3B
)
V
4
SEG
V
5
V
0
V
1
V
2
V
3A
(V
3B
)
V
4
V
5
COM
1
(CSR = "L", AS = "L")
COM
2
(CSR = "L", AS = "H")
COM
17
(CSR = "H", AS = "L")
COM
16
(CSR = "H", AS = "H")
(first character line)
COM
2
(CSR = "L", AS = "L")
COM
3
(CSR = "L", AS = "H")
COM
16
(CSR = "H", AS = "L")
COM
15
(CSR = "H", AS = "H")
(second character line)
COM
16
(CSR = "L", AS = "L")
COM
17
(CSR = "L", AS = "H")
COM
2
(CSR = "H", AS = "L")
COM
1
(CSR = "H", AS = "H")
(sixteenth character line)
COM
17
(CSR = "L", AS = "L")
COM
1
(CSR = "L", AS = "H")
COM
1
(CSR = "H", AS = "L")
COM
17
(CSR = "H", AS = "H")
(arbitrator line)
16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 16 17 1 2 3 4
CSR="L"
2 1 17 16 15 14 13 12 11 10 9 8 7 6 5 2 1 17 16 15 14
CSR="H"
FEDL9042-01
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ML9042-xx
48/58
Initial Setting of Instructions
(a) Data transfer from and to the CPU using 8 bits of DB
0
to DB
7
1) Turn on the power.
2) Wait for 15 ms or more after V
DD
has reached 2.7 V or higher.
3) Set "8 bits" with the Function Setting instruction.
4) Wait for 4.1 ms or more.
5) Set "8 bits" with the Function Setting instruction.
6) Wait for 100
s or more.
7) Set "8 bits" with the Function Setting instruction.
8) Check the Busy Flag for No Busy (or wait for 100
s or more).
9) Set "8 bits", "Number of LCD lines" and "Font size" with the Function Setting instruction.
(After this, the number of LCD lines and the font size cannot be changed.)
10) Check the Busy Flag for No Busy.
11) Execute the Display ON/OFF control Instruction, Display Clear Instruction, Entry Mode Setting
instruction and Arbitrator Display Line Setting Instruction.
12) Check the Busy Flag for No Busy.
13) Initialization is completed.
An example of instruction code for 3), 5) and 7)
RS
1
1
RS
0
0
R/
W
0
DB
7
0
DB
6
0
DB
5
1
DB
4
1
DB
3
DB
2
DB
1
DB
0
: Don't Care
(b) Data transfer from and to the CPU using 4 bits of DB
4
to DB
7
1) Turn on the power.
2) Wait for 15 ms or more after V
DD
has reached 2.7 V or higher.
3) Set "8 bits" with the Function Setting instruction.
4) Wait for 4.1 ms or more.
5) Set "8 bits" with the Function Setting instruction.
6) Wait for 100
s or more.
7) Set "8 bits" with the Function Setting instruction.
8) Check the Busy Flag for No Busy (or wait for 100
s or longer).
9) Set "4 bits" with the Function Setting instruction.
10) Wait for 100
s or longer.
11) Set "4 bits", "Number of LCD lines" and "Font size" with the Function Setting instruction. (After this,
the number of LCD lines and the font size cannot be changed.)
12) Check the Busy Flag for No Busy.
13) Execute the Display ON/OFF control Instruction, Display Clear Instruction, Entry Mode Setting
instruction and Arbitrator Display Line Setting Instruction.
14) Check the Busy Flag for No Busy.
15) Initialization is completed.
An example of instruction code for 3), 5) and 7)
RS
1
1
RS
0
0
R/
W
0
DB
7
0
DB
6
0
DB
5
1
DB
4
1
FEDL9042-01
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ML9042-xx
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An example of instruction code for 9)
RS
1
1
RS
0
0
R/
W
0
DB
7
0
DB
6
0
DB
5
1
DB
4
0
*: From 11), input data twice by the use of 4-bit data.
*: In 13), check the Busy Flag for No Busy before executing each instruction.
(c) Data transfer from and to the CPU using the serial I/F
1) Turn on the power.
2) Wait for 15 ms or more after V
DD
has reached 2.7 V or higher.
3) Check the busy flag for No Busy.
4) Set "Number of LCD lines" and "Font size" with the Function Setting Instruction. (After this, the
number of LCD lines and the font size cannot be changed.)
5) Check the busy flag for No Busy.
6) Execute the Display ON/OFF control Instruction, the Display Clear Instruction, the Entry Mode
Instruction and the Arbitrator Display Line Setting Instruction.
7) Check the busy flag for No Busy.
8) Initialization is completed.
*: In 6), check the Busy Flag for No Busy before executing each instruction.
FEDL9042-01
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ML9042-xx
50/58
ML9042-xx CVWA/DVWA PAD CONFIGURATION
Pad Layout
Chip Size:
7.8
1.8 mm
Chip Thickness: 625
20 m
Bump Size:
100
44 m
Y
X
220
221
114
233
101
1
115
100
Pad Coordinates
Pad Symbol X
(
m) Y
(
m) Pad
Symbol
X
(
m) Y
(
m)
1
DUMMY -3750
750
21
DUMMY -2250 750
2
OSC2 -3675 750
22
E/SHTB -2175 750
3
OSCR5 -3600 750
23
E/SHTB -2100 750
4
OSCR3 -3525 750
24
DUMMY -2025 750
5
OSC1 -3450 750
25
DUMMY -1950 750
6
DUMMYGND
-3375 750
26
DB0/SO -1875 750
7
T1 -3300 750
27
DB0/SO -1800 750
8
T2 -3225 750
28
DUMMY -1725 750
9
T3 -3150 750
29
DUMMY -1650 750
10
ROM1S -3075 750
30
DB1 -1575 750
11
DUMMYV
DD
-3000
750
31
DB1 -1500 750
12
RS1 -2925 750
32
DUMMY -1425 750
13
RS1 -2850 750
33
DUMMY -1350 750
14
RSO/CSB -2775
750
34
DB2 -1275 750
15
RSO/CSB -2700
750
35
DB2 -1200 750
16
DUMMY -2625
750
36
DUMMY -1125 750
17
DUMMY -2550
750
37
DUMMY -1050 750
18
RW/SI -2475 750
38
DB3 -975 750
19
RW/SI -2400 750
39
DB3 -900 750
20
DUMMY -2325
750
40
DUMMY -825 750
FEDL9042-01
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ML9042-xx
51/58
Pad Symbol X
(
m) Y
(
m) Pad
Symbol
X
(
m) Y
(
m)
41
DUMMY -750
750
81
V0 2250 -750
42
DB4 -675 750
82
V0 2325 -750
43
DB4 -600 750
83
V0 2400 -750
44
DUMMY -525
750
84
V0 2475 -750
45
DUMMY -450
750
85
V1 2550 -750
46
DB5 -375 750
86
V2 2625 -750
47
DB5 -300 750
87
V2 2700 -750
48
DUMMY -225
750
88
V3A 2775 -750
49
DUMMY -150
750
89
V3A 2850 -750
50
DB6 -75 750
90
V3B 2925 -750
51
DB6 0 750
91
V3B 3000 -750
52
DUMMY 75
750
92
V4 3075 -750
53
DUMMY 150
750
93
V
C
3150 -750
54
DB7 225 750
94
V
C
3225 -750
55
DB7 300 750
95
V
C
3300 -750
56
DUMMYV
DD
375 750
96
V
C
3375 -750
57
SP 450 750
97
V
CC
3450 -750
58
GND 525 750
98
V
CC
3525 -750
59
GND 600 750
99
V
CC
3600 -750
60
GND 675 750
100
DUMMY 3675
-750
61
GND 750 750
101
DUMMY 3750
-462
62
GND 825 750
102
COM
17
3750 -392
63
GND 900 750
103
COM
16
3750 -322
64
BE 975 750
104
COM
15
3750 -252
65
V
DD
1050 750
105
COM
14
3750 -182
66
V
DD
1125 750
106
COM
13
3750 -112
67
V
DD
1200 750
107
COM
12
3750
-42
68
V
DD
1275 750
108
COM
11
3750
28
69
V
DD
1350 750
109
COM
10
3750
98
70
V
DD
1425 750
110
COM
9
3750 168
71
TEST
IN
1500 750
111
DUMMY 3750
238
72
TEST
IN
1575 750
112
DUMMY 3750
308
73
TEST
OUT
1650 750
113
DUMMY 3750
378
74
TEST
OUT
1725 750
114
DUMMY 3750
448
75
V
IN
1800 750
115
DUMMY 3675
750
76
V
IN
1875 750
116
DUMMY 3605
750
77
V
OUT
1950 750
117
DUMMY 3535
750
78
V
OUT
2025 750
118
SEG
100
3465
750
79
V0 2100 750
119
SEG
99
3395 750
80
V0 2175 750
120
SEG
98
3325 750
FEDL9042-01
OKI Semiconductor
ML9042-xx
52/58
Pad Symbol X
(
m) Y
(
m) Pad
Symbol
X
(
m) Y
(
m)
121
SEG
97
3255 750
161
SEG
57
455 750
122
SEG
96
3185 750
162
SEG
56
385 750
123
SEG
95
3115 750
163
SEG
55
315 750
124
SEG
94
3045 750
164
SEG
54
245 750
125
SEG
93
2975 750
165
SEG
53
175 750
126
SEG
92
2905 750
166
SEG
52
105 750
127
SEG
91
2835 750
167
SEG
51
35 750
128
SEG
90
2765 750
168
SEG
50
-35 750
129
SEG
89
2695 750
169
SEG
49
-105 750
130
SEG
88
2625 750
170
SEG
48
-175 750
131
SEG
87
2555 750
171
SEG
47
-245 750
132
SEG
86
2485 750
172
SEG
46
-315 750
133
SEG
85
2415 750
173
SEG
45
-385 750
134
SEG
84
2345 750
174
SEG
44
-455 750
135
SEG
83
2275 750
175
SEG
43
-525 750
136
SEG
82
2205 750
176
SEG
42
-595 750
137
SEG
81
2135 750
177
SEG
41
-665 750
138
SEG
80
2065 750
178
SEG
40
-735 750
139
SEG
79
1995 750
179
SEG
39
-805 750
140
SEG
78
1925 750
180
SEG
38
-875 750
141
SEG
77
1855 750
181
SEG
37
-945 750
142
SEG
76
1785 750
182
SEG
36
-1015 750
143
SEG
75
1715 750
183
SEG
35
-1085 750
144
SEG
74
1645 750
184
SEG
34
-1155 750
145
SEG
73
1575 750
185
SEG
33
-1225 750
146
SEG
72
1505 750
186
SEG
32
-1295 750
147
SEG
71
1435 750
187
SEG
31
-1365 750
148
SEG
70
1365 750
188
SEG
30
-1435 750
149
SEG
69
1295 750
189
SEG
29
-1505 750
150
SEG
68
1225 750
190
SEG
28
-1575 750
151
SEG
67
1155 750
191
SEG
27
-1645 750
152
SEG
66
1085 750
192
SEG
26
-1715 750
153
SEG
65
1015 750
193
SEG
25
-1785 750
154
SEG
64
945 750
194
SEG
24
-1855 750
155
SEG
63
875 750
195
SEG
23
-1925 750
156
SEG
62
805 750
196
SEG
22
-1995 750
157
SEG
61
735 750
197
SEG
21
-2065 750
158
SEG
60
665 750
198
SEG
20
-2135 750
159
SEG
59
595 750
199
SEG
19
-2205 750
160
SEG
58
525 750
200
SEG
18
-2275 750
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Pad Symbol X
(
m) Y
(
m)
201
SEG
17
-2345 750
202
SEG
16
-2415 750
203
SEG
15
-2485 750
204
SEG
14
-2555 750
205
SEG
13
-2625 750
206
SEG
12
-2695 750
207
SEG
11
-2765 750
208
SEG
10
-2835 750
209
SEG
9
-2905 750
210
SEG
8
-2975 750
211
SEG
7
-3045 750
212
SEG
6
-3115 750
213
SEG
5
-3185 750
214
SEG
4
-3255 750
215
SEG
3
-3325 750
216
SEG
2
-3395 750
217
SEG
1
-3465 750
218
DUMMY -3535
750
219
DUMMY -3605
750
220
DUMMY -3675
750
221
DUMMY -3750
448
222
DUMMY -3750
378
223
DUMMY -3750
308
224
DUMMY -3750
238
225
COM
1
-3750 168
226
COM
2
-3750 98
227
COM
3
-3750 28
228
COM
4
-3750 -42
229
COM
5
-3750 -112
230
COM
6
-3750 -182
231
COM
7
-3750 -252
232
COM
8
-3750 -322
233
DUMMY -3750
-392
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ML9042-xx CVWA/DVWA ALIGNMENT MARK SPECIFICATION
Alignment Mark Coordinates
Alignment Mark
X (
m) Y
(
m)
A 3770 770
B 3770 770
C 3770 770
The coordinates (X, Y) indicate the distances to the center of an alignment mark (the center of the maximum
outline of the L shape).
Alignment Mark Layer
Gold bump
Alignment Mark Gold Bump Specification
Symbol Parameter Mark
Size
(
m)
a
Alignment Mark Width
A, B, C
30
b
Alignment Mark Size
A, B, C
80
A
B
C
X
Y
....................................................................................................
(0, 0)
....................................................................................................
:
:
:
:
a
b
+
a
b
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ML9042-xx CVWA GOLD BUMP SPECIFICATION (HIGH
HARDNESS)
Gold Bump Specification
(Unit:
m)
Symbol
Parameter
MIN
TYP
MAX
A
Bump Pitch (I/O Section: Pitch Direction)
70
--
--
B
Bump Size (I/O Section: Pitch Direction)
40
44
48
C
Bump Size (I/O Section: Depth Direction)
96
100
104
D
Bump-to-Bump Distance (I/O Section: Pitch Direction)
22
26
30
E
Bump Size (L-mark Section: Length)
76
80
84
F
Bump Size (L-mark Section: Width)
26
30
34
G
Sliding of Total Bump Pitches
--
--
2
Bump Height
10
15
20
H
Bump Height Dispersion Inside Chip (Range)
--
--
4
I
Bump Edge Height
--
--
5
J
Shear Strength (g)
27
--
--
K
Bump Hardness (Hv: 25 g load)
50
90
130
Wafer Thickness; 625
20
m
Chip Size; 7.80 mm
1.80 mm
Top View and Cross Section View
B
D
E
[Cross Section View]
[I/O Section]
[L-Alignment Mark]
A
C
F
I
H
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ML9042-xx CVWA GOLD BUMP SPECIFICATION (LOW HARDNESS)
Gold Bump Specification
(Unit:
m)
Symbol
Parameter
MIN
TYP
MAX
A
Bump Pitch (I/O Section: Pitch Direction)
70
--
--
B
Bump Size (I/O Section: Pitch Direction)
40
44
48
C
Bump Size (I/O Section: Depth Direction)
96
100
104
D
Bump-to-Bump Distance (I/O Section: Pitch Direction)
22
26
30
E
Bump Size (L-mark Section: Length)
76
80
84
F
Bump Size (L-mark Section: Width)
26
30
34
G
Sliding of Total Bump Pitches
--
--
2
Bump Height
10
15
20
H
Bump Height Dispersion Inside Chip (Range)
--
--
4
I
Bump Edge Height
--
--
5
J
Shear Strength (g)
27
--
--
K
Bump Hardness (Hv: 25 g load)
30
--
80
Wafer Thickness; 625
20
m
Chip Size; 7.80 mm
1.80 mm
Top View and Cross Section View
B
D
E
[Cross Section View]
[I/O Section]
[L-Alignment Mark]
A
C
F
I
H
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REVISION HISTORY
Page
Document
No.
Date
Previous
Edition
Current
Edition
Description
PEDL9042-01
Jun. 16, 2003
Preliminary first edition
5
5
Changed descriptions of Symbols V
C
and V
CC
8 8
Changed DC Characteristics
Condition
VDD = 4.5 to 5.5V
VDD = 4.0 to 5.5V
Ta = 25
C
Ta =- 20 to 75
C
Spec
Min. 175 Typ. 270 Max. 365
Min. 200 Typ. 270 Max. 351
Min. 175 Typ. 270 Max. 365
Min. 200 Typ. 280 Max. 364
25
25
Added of table
44 44
Partially changed figure of generation circuits
(V
C
+)
(V
CC
+) and V
2
,V
3A
,V
3B
FEDL9042-01
Nov. 19, 2003
45 45
Partially changed figure of generation circuits
(V
C
+)
(V
CC
+)
FEDL9042-01
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NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party's right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any
system or application that requires special or enhanced quality and reliability characteristics nor in any
system or application where the failure of such system or application may result in the loss or damage of
property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2003 Oki Electric Industry Co., Ltd.
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