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Электронный компонент: ML7033GA

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FEDL7033-02
1Semiconductor
This version: Dec. 2001
Previous version: Jul. 2001
ML7033
Dual-Channel Line Card CODEC
1/51
GENERAL DESCRIPTION
The ML7033 is a 2-channel PCM CODEC CMOS IC designed for Central Office (CO) and Customer Premise
Equipment (CPE) environments. The ML7033 device contains 2-channel analog-to-digital (A/D) and digital-to-
analog (D/A) converters with multiplexed PCM input and output. The ML7033 is designed for single-rail, low
power applications. The high integration of the ML7033 reduces the number of external components and overall
board size. The ML7033 is best suited for line card applications and provides an easy interface to subscriber line
interface circuits (SLIC's), in particular the Intersil RSLIC
TM
series.
FEATURES
Seamlessly interfaces with Intersil RSLIC
TM
series devices
Single 5 volt power supply (4.75 V to 5.25 V)
-
ADC and DAC
PCM format: -law/A-law (ITU-T G.711 compliant), 14-bit linear (2's complement)
Optional wideband filter for V.90 data modem applications
Low power consumption
- 2-channel operating mode: 115 mW (typical)
180 mW (max)
- 1-channel operating mode: 80 mW (typical)
115 mW (max)
- Power-down mode:
0.1 mW (typical)
0.25 mW (max); PDN pin = logic "0"
Power-on reset
Dual programmable tone generators (300 Hz to 3400 Hz; 10 Hz intervals; 0.1 dB intervals)
- Call progress tone, DTMF tone
Ringing tone generator (15 Hz to 50 Hz; 1Hz intervals; 0.1 dB intervals)
Pulse metering tone generator (12 kHz, 16 kHz; gain level selectable)
Call ID tone generator (ITU-T V.23, Bell 202)
Analog and digital loop back test modes
Time-slot assignment
Serial MCU interface
Master clock: 2.048 MHz/4.096 MHz selectable
Serial PCM transmission data rate: 256 kbps to 4096 kbps
Adjustable transmit/receive gain (1 dB intervals)
Built-in reference voltage generator
Differential or single-ended analog output selectable
Package: 64-pin plastic QFP (QFP64-P-1414-0.80-BK) (Ordering Part number: ML7033GA)
FEDL7033-02
1Semiconductor
ML7033
2/51
BLOCK DIAGRAM
RC LP
F
RC LP
F
-

AD
CON
V
BP
F
BP
F
-

AD
CON
V
AI
N2N
AI
N2P
GS
X2
AI
N1N
AI
N1P
GS
X1
P
CM
OSY
TC
O
N
T
XS
YN
C
PC
MO
U
T
Co
m
p
re
s
s
o
r
Co
m
p
re
s
s
o
r
Pu
l
s
e
Me
te
r
Ge
n.
2
TO
U
T
1
TO
U
T
2
AO
U
T
1N
RC LP
F
RC LP
F
-

DA
CON
V
-

DA
CON
V
Pu
l
s
e
M
e
t
e
r
G
en.
1
CH1
T
G
2
CR9
B
7
-
B
1
CR7
B
4
-
B
1
CR7
B
6
C
R
14 B
6
C
R
14 B
5
CR7
B
5
CR1
8
B7
,
B6
CR1
8
B5
,
B4
CR2
B
2
-
B
1
CR2
B
6
-
B
5
C
R
12 B
3
-B
0
CR5
B
3
-
B
0
CR2
B
0
SG G
en.
SG
C
V
DD
D
V
DD
A
AG
DG
F2_1
F1_1
F0_1
E0_1
SWC1
BSEL1
DET1
ALM1
F2_2
F1_2
F0_2
E0_2
SWC2
BSEL2
DET2
ALM2
AO
U
T
2P
AO
U
T
1P
LP
F
RC LP
F
RC LP
F
-

DA
CON
V
-

DA
CON
V
LP
F
RC
ON
T
RS
YN
C
PC
MI
N
M
CU C
o
n
t
r
o
l
&
Cl
o
c
k
Ge
n.
PDN
RESET
MCK
TEST
CIDATA1
CIDATA2
DIO
DEN
EXCK
INT
E
x
pan
de
r
E
x
pan
de
r
BC
LK
AO
U
T
2N
SG
CR5
B
7
-
B
4
C
R
12 B
7
-B
4
CR2
B
4
CR1
8
B7
-
B4
,
B0
CH2
T
G
2
C
R
16 B
7
-B
1
C
R
14 B
4
-B
1
C
R
14-B
7
CR7
-
B
7
Ca
l
l
-
I
D2
R
i
n
g
T
one
2
CH2
T
G
1
Ca
l
l
-
I
D1
R
i
n
g
T
one
1
CH1
T
G
1
CR1
B
0
CR
1 B
6
C
R
11-B
3
CR1
B
1
CR
1 B
7
C
R
11-B
7
S
L
IC
C
ontr
o
l
FEDL7033-02
1Semiconductor
ML7033
3/51
PIN CONFIGURATION (TOP VIEW)
N.C
AIN1N
GSX1
AOUT1P
AOUT1N
TOUT1
AG
SG
SGC
AG
TOUT2
AOUT2N
AOUT2P
GSX2
AIN2N
N.C
N.C
RESET
RSYNC
XSYNC
PCMOUT
PCMOSY
PCMIN
DG
BCLK
MCK
V
DDD
DIO
DEN
EXCK
INT
N.C
N.C
AIN1P
V
DDA
V
DDD
SWC
1
F2_1
F1_1
F0_1
E0_1
DET
1
ALM
1
BSEL1
DG
TEST
PDN
N.C
N.C
AIN2P
V
DDA
V
DDD
BSEL2
ALM
2
DET
2
E0_2
F0_2
F1_2
F2_2
SWC
2
DG
CIDATA1
CIDATA2
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
64-Pin Plastic QFP
FEDL7033-02
1Semiconductor
ML7033
4/51
PIN DESCRIPTIONS
Pin
Symbol
Type
Description
1
N.C
--
(Leave unconnected)
2
AIN1N
I
CH1 Transmit Op-amp Input Negative
3
GSX1
O
CH1 Transmit Op-amp Output
4
AOUT1P
O
CH1 Receive Output Positive
5
AOUT1N
O
CH1 Receive Output Negative
6
TOUT1
O
CH1 Tone Output
7
AG
--
Analog Ground
8
SG
O
Signal Ground for External Circuit
9
SGC
O
Signal Ground for Internal Circuit
10
AG
--
Analog Ground
11
TOUT2
O
CH2 Tone Output
12
AOUT2N
O
CH2 Receive Output Negative
13
AOUT2P
O
CH2 Receive Output Positive
14
GSX2
O
CH2 Transmit Op-amp Output
15
AIN2N
I
CH2 Transmit Op-amp Input Negative
16
N.C
--
(Leave unconnected)
17
N.C
--
(Leave unconnected)
18
AIN2P
I
CH2 Transmit Op-amp Input Positive
19
V
DDA
--
Power Supply for Internal Analog Circuit
20
V
DDD
--
Power Supply for Internal Digital Circuit
21
BSEL2
O
Output for SLIC2 Battery Select
22
ALM2
I
Input from SLIC2 Thermal Shut Down Alarm Detector
23
DET2
I
Input from SLIC2 Switch Hook, Ground Key or Ring Trip Detector
24
E0_2
O
Output for SLIC2 Detector Mode Selection
25
F0_2
O
Mode Control Output to SLIC2 F0
26
F1_2
O
Mode Control Output to SLIC2 F1
27
F2_2
O
Mode Control Output to SLIC2 F2
28
SWC2
O
Output for SLIC2 Uncommitted Switch Control
29
DG
--
Digital Ground
30
CIDATA1
I
Call ID Data Input for CH1
31
CIDATA2
I
Call ID Data Input for CH2
32
N.C
--
(Leave unconnected)
33
N.C
--
(Leave unconnected)
34
INT
O
Interrupt Output (from SLIC status)
35
EXCK
I
MCU Interface Data Clock Input
36
DEN
I
MCU Interface Data Enable Input
37
DIO
I/O
MCU Interface Control Data Input/Output
FEDL7033-02
1Semiconductor
ML7033
5/51
Pin
Symbol
Type
Description
38
V
DDD
--
Power Supply for Internal Digital Circuit
39
MCK
I
Master Clock (2.048/4.096 MHz)
40
BCLK
I
PCM Data Shift Clock
41
DG
--
Digital Ground
42
PCMIN
I
PCM Data Input
43
PCMOSY
O
PCM Data Output Indicator for Time-Slot Assignment
44
PCMOUT
O
PCM Data Output
45
XSYNC
I
Transmit Synchronizing Clock Input
46
RSYNC
I
Receive Synchronizing Clock Input
47
RESET
I
Reset for Control Register
48
N.C
--
(Leave unconnected)
49
N.C
--
(Leave unconnected)
50
PDN
I
Power-down Control
51
TEST
I
LSI Manufacturer's Test Input (keep logic "0")
52
DG
--
Digital Ground
53
BSEL1
O
Output for SLIC1 Battery Select
54
ALM1
I
Input from SLIC1 Thermal Shut Down Alarm Detector
55
DET1
I
Input from SLIC1 Switch Hook, Ground Key or Ring Trip Detector
56
E0_1
O
Output for SLIC1 Detector Mode Selection
57
F0_1
O
Mode Control Output to SLIC1 F0
58
F1_1
O
Mode Control Output to SLIC1 F1
59
F2_1
O
Mode Control Output to SLIC1 F2
60
SWC1
O
Output for SLIC1 Uncommitted Switch Control
61
V
DDD
--
Power Supply for Internal Digital Circuit
62
V
DDA
--
Power Supply for Internal Analog Circuit
63
AIN1P
I
CH1 Transmit Op-amp Input Positive
64
N.C
--
(Leave unconnected)
Note: In this datasheet, "1" and "2" in names for pins which respectively exist for CH1 and CH2 are often
substituted by "n" (in a small letter).
Ex) GSX1, GSX2
GSXn
AOUT1N, AOUT2N
AOUTnN
DET1, DET2
DETn
FEDL7033-02
1Semiconductor
ML7033
6/51
Control Register Assignment
Address
Data
Register
A4 A3 A2 A1 A0
B7
B6
B5
B4
B3
B2
B1
B0
R/W
CR0
0
0
0
0
0
Filter2
SEL
Filter1
SEL
MCK
SEL
SHORT
LIN
ALAW
MODE1 MODE0 R/W
CR1
0
0
0
0
1
CH2TG
ON
CH1TG
ON
CID
FMT
CID
CH2ON
CID
CH1ON
R/W
CR2
0
0
0
1
0
PMG2
FRQ
PMG2
LV1
PMG2
LV0
PMG2
TOUT2
PMG1
FRQ
PMG1
LV1
PMG1
LV0
PMG1
TOUT1
R/W
CR3
0
0
0
1
1
TSAE
TSAC
TSA5
TSA4
TSA3
TSA2
TSA1
TSA0
W
CR4
0
0
1
0
0
DET2
TIM3
DET2
TIM2
DET2
TIM1
DET2
TIM0
DET1
TIM3
DET1
TIM2
DET1
TIM1
DET1
TIM0
R/W
CR5
0
0
1
0
1
LV1R3
LV1R2
LV1R1
LV1R0
LV1X3
LV1X2
LV1X1
LV1X0 R/W
CR6
0
0
1
1
0
F2_1
F1_1
F0_1
SWC1
BSEL1
E0_1
DET1*
ALM1* R/W
CR7
0
0
1
1
1
AOUT1
SEL
CH1TG2
TX
CH1TG2
TOUT1
CH1TG2
LV3
CH1TG2
LV2
CH1TG2
LV1
CH1TG2
LV0
CH1TG2
_8
R/W
CR8
0
1
0
0
0
CH1TG2
_7
CH1TG2
_6
CH1TG2
_5
CH1TG2
_4
CH1TG2
_3
CH1TG2
_2
CH1TG2
_1
CH1TG2
_0
R/W
CR9
0
1
0
0
1
CH1TG1
LV6
CH1TG1
LV5
CH1TG1
LV4
CH1TG1
LV3
CH1TG1
LV2
CH1TG1
LV1
CH1TG1
LV0
CH1TG1
_8
R/W
CR10
0
1
0
1
0
CH1TG1
_7
CH1TG1
_6
CH1TG1
_5
CH1TG1
_4
CH1TG1
_3
CH1TG1
_2
CH1TG1
_1
CH1TG1
_0
R/W
CR11
0
1
0
1
1
CH2
RING
CH2TG1
TRP2
CH2TG1
TRP1
CH2TG1
TRP0
CH1
RI NG
CH1TG1
TRP2
CH1TG1
TRP1
CH1TG1
TRP0
R/W
CR12
0
1
1
0
0
LV2R3
LV2R2
LV2R1
LV2R0
LV2X3
LV2X2
LV2X1
LV2X0 R/W
CR13
0
1
1
0
1
F2_2
F1_2
F0_2
SWC2
BSEL2
E0_2
DET2*
ALM2* R/W
CR14
0
1
1
1
0
AOUT2
SEL
CH2TG
TX
CH2TG
TOUT2
CH2TG2
LV3
CH2TG2
LV2
CH2TG2
LV1
CH2TG2
LV0
CH2TG2
_8
R/W
CR15
0
1
1
1
1
CH2TG2
_7
CH2TG2
_6
CH2TG2
_5
CH2TG2
_4
CH2TG2
_3
CH2TG2
_2
CH2TG2
_1
CH2TG2
_0
R/W
CR16
1
0
0
0
0
CH2TG1
LV6
CH2TG1
LV5
CH2TG1
LV4
CH2TG1
LV3
CH2TG1
LV2
CH2TG1
LV1
CH2TG1
LV0
CH2TG1
_8
R/W
CR17
1
0
0
0
1
CH2TG1
_7
CH2TG1
_6
CH2TG1
_5
CH2TG1
_4
CH2TG1
_3
CH2TG1
_2
CH2TG1
_1
CH2TG1
_0
R/W
CR18
1
0
0
1
0
CH2
LOOP1
CH2
LOOP0
CH1
LOOP1
CH1
LOOP0
TEST3
TEST2
TEST1
TEST0 R/W
CR19
1
0
0
1
1 TEST11 TEST10 TEST9
TEST8
TEST7
TEST6
TEST5
TEST4 R/W
*: Read only bit
Note: In this datasheet, numbers in names for control register bits are often substituted by "n" (in a small letter). In
the case, the "n" does not always refer to a channel number.
Ex) MODE0, MODE1
MODEn
CH1TG2_7, CH1TG2_6
CH1TG2_n
PMG2FRQ, PMG1FRQ
PMGnFRQ
FEDL7033-02
1Semiconductor
ML7033
7/51
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Rating
Unit
Power Supply Voltage
V
DD
V
DDD
, V
DDA
0.3 to +7.0
V
Analog Input Voltage
V
AIN
--
0.3 to V
DD
+0.3
V
Digital Input Voltage
V
DIN
--
0.3 to V
DD
+0.3
V
Storage Temperature
T
STG
--
55 to +150
C
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Power Supply Voltage
V
DD
Voltage to be fixed; V
DDD
, V
DDA
4.75
5.0
5.25
V
Operating Temperature
T
OP
--
40
--
+85
C
High Level Input Voltage
V
IH
2.2
--
V
DD
V
Low Level Input Voltage
V
IL
All digital input pins
0
--
0.8
V
MCK = 2.048 MHz
MCKSEL (CR0-B5) bit = "0"
0.01%
2048
+0.01%
kHz
MCK Frequency
F
MCK
MCK = 4.096 MHz
MCKSEL (CR0-B5) bit = "1"
0.01%
4096
+0.01%
kHz
BCLK Frequency
F
BCLK
BCLK
256
--
4096
kHz
Sync Pulse Frequency
F
SYNC
XSYNC, RSYNC
0.01%
8
+0.01%
kHz
Clock Duty Ratio
D
CLK
MCK,BCLK
40
50
60
%
Digital Input Rise Time
t
IR
--
--
50
ns
Digital Input Fall Time
t
IF
All digital input pins
--
--
50
ns
MCK to BCLK Phase Difference
t
MB
MCK, BCLK
--
--
50
ns
t
XS
BCLK to XSYNC
50
--
--
ns
Transmit Sync Pulse Setting Time
t
SX
XSYNC to BCLK
50
--
--
ns
t
RS
BCLK to RSYNC
50
--
--
ns
Receive Sync Pulse Setting Time
t
SR
RSYNC to BCLK
50
--
--
ns
XSYNC, RSYNC
SHORT (CR0-B4) bit = "0"
1 BCLK
--
125
s
1BCLK
s
Sync Pulse Width
t
WS
XSYNC, RSYNC
SHORT (CR0-B4) bit = "0"
210
--
1BCLK
ns
PCMOUT Set-up Time
t
DS
PCMOUT
50
--
--
ns
PCMOUT Hold Time
t
DH
PCMOUT
50
--
--
ns
R
DL
Pull-up Resistor, PCMOUT
0.5
--
--
k
C
DL1
PCMOUT
--
--
50
pF
Digital Output Load
C
DL2
Other output pins
--
--
50
pF
Bypass Capacitor for SGC
C
SG
SGC to AG
0.1
--
--
F
FEDL7033-02
1Semiconductor
ML7033
8/51
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(V
DD
= 4.75 to 5.25 V, Ta = 40 to +85
C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
I
DD1
2CH Operating Mode, No Signal
--
23.0
35.0
mA
I
DD2
1CH Operating Mode, No Signal
--
16.0
22.0
mA
Power Supply Current
I
DD4
Power-down Mode
PDN pin = logic "0"
--
25.0
50.0
A
High Level Input Leakage Current
I
IH
All Digital Input Pins
V
I
= V
DD
--
0.1
5.0
A
Low Level Input Leakage Current
I
IL
All Digital Input Pins
V
I
= 0 V
5.0
0.1
--
A
V
OL1
PCMOUT, Pull-up = 0.5 k
0
0.2
0.4
V
Digital Output Low Voltage
V
OL2
Other output pins, I
OL
= 0.4 mA
0
0.2
0.4
V
Digital Output High Voltage
V
OH
I
OH
= 0.4 mA
2.5
--
--
V
Digital Output Leakage Current
I
O
PCMOUT High Impedance State
--
--
10
A
Input Capacitance
C
IN
--
--
5
--
pF
Analog Interface Characteristics
(V
DD
= 4.75 to 5.25 V, Ta = 40 to +85
C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
SG, SGC Output Voltage
V
SG
SGC to AG 0.1
F
--
2.4
--
V
SG, SGC Rise Time
t
SGC
SGC to AG 0.1
F
Rise time to 90% of max. level
--
--
10
ms
SG Output Load Resistance
R
LSG
SG
10
--
--
k
Transmit Analog Interface Characteristics
(V
DD
= 4.75 to 5.25 V, Ta = 40 to +85
C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Input Resistance
R
INX
AINnN, AINnP
--
10
--
M
Output Load Resistance
R
LGX
20
--
--
k
Output Load Capacitance
C
LGX
--
--
30
pF
Output Amplitude
V
OGX
GSXn
(to SGC)
*1
--
--
2.226
Vpp
Offset Voltage
V
OSGX
Gain = 1
50
--
50
mV
*1 3.0 dBm (600
) = 0 dBm0
FEDL7033-02
1Semiconductor
ML7033
9/51
Receive Analog Interface Characteristics
(V
DD
= 4.75 to 5.25 V, Ta = 40 to +85
C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
R
LAO
AOUTnN, AOUTnP
(to SGC)
20
--
--
k
Output Load Resistance
R
LTO
TOUTn
(to SGC)
10
--
--
k
Output Load Capacitance
C
LAO
AOUTnN, AOUTnP, TOUTn
--
--
50
pF
Output Amplitude
V
OAO
AOUTnN, AOUTnP, TOUTn
R
LAO
= 20 k
(to SGC)
--
--
3.4*
Vpp
Offset Voltage
V
OSAO
AOUTnN, AOUTnP, TOUTn
R
LAO
= 20 k
(to SGC)
100
--
100
mV
* 0.658 dBm (600
) = 0 dBm0
FEDL7033-02
1Semiconductor
ML7033
10/51
AC Characteristics
(V
DD
= 4.75 to 5.25 V, Ta = 40 to +85
C)
Condition
Parameter
Symbol
Freq.
(Hz)
Level
(dBm0)
Min.
Typ.
Max.
Unit
Loss T1
60
25
45
--
Loss T2
300
0.15
0.15
0.20
Loss T3
1020
Reference
Loss T4
3000
0.15
0.02
0.20
Loss T5
3300
0.15
0.1
0.80
Transmit
Frequency Response
Loss T6
3400
0
GSXn to
PCMOUT
(Attenuation)
0
0.6
0.80
dB
Loss R1
100
0.15
0.04
0.2
Loss R2
1020
Reference
Loss R3
3000
0.15
0.07
0.2
Loss R4
3300
0.15
0.2
0.8
Receive
Frequency Response
Loss R5
3400
0
PCMIN to
AOUTn
(Attenuation)
0
0.6
0.8
dB
SDT1
3
36
43
--
SDT2
0
36
40
--
SDT3
30
36
38
--
SDT4
40
30
32
--
Transmit
Signal to Distortion
Ratio
SDT5
1020
45
GSXn to
PCMOUT
*1
25
29
--
dB
SDR1
3
36
42
--
SDR2
0
36
39
--
SDR3
30
36
39
--
SDR4
40
30
33
--
Receive
Signal to Distortion
Ratio
SDR5
1020
45
PCMIN to
AOUTn
*1
25
30
--
dB
GTT1
3
0.2
0.02
0.2
GTT2
10
Reference
GTT3
40
0.2
0.06
0.2
GTT4
50
0.6
0.4
0.6
Transmit
Gain Tracking
GTT5
1020
55
GSXn to
PCMOUT
1.2
0.4
1.2
dB
GTR1
3
0.2
0
0.2
GTR2
10
Reference
GTR3
40
0.2
0.02
0.2
GTR4
50
0.6
0.1
0.6
Receive
Gain Tracking
GTR5
1020
55
PCMIN to
AOUTn
1.2
0.2
1.2
dB
*1
C-message filter used
FEDL7033-02
1Semiconductor
ML7033
11/51
AC Characteristics (Continued)
(V
DD
= 4.75 to 5.25 V, Ta = 40 to +85
C)
Condition
Parameter
Symbol
Freq.
(Hz)
Level
(dBm0)
Min.
Typ.
Max.
Unit
NIDLE
T
--
--
Analog input = SGC
*1
AINn to PCMOUT
Gain = 1
(
-law)
--
9
15
Idle Channel Noise
NIDLE
R
--
--
PCMIN = `FF'h (
-law)
PCMIN = `D5'h (A-law)
PCMIN = all `0' (linear)
*1
PCMIN to AOUTn
--
4
10
dBm0
GSXn to PCMOUT
V
DD
= 5 V, Ta = 25
C
0.511
0.548
0.587
Absolute Level
(Initial Difference)
AV
T
/AV
R
PCMIN to AOUTn
(Single-ended)
V
DD
= 5 V, Ta = 25
C
0.806
0.835
0.864
Vrms
AV
TT
0.3
--
0.3
Absolute Level
(Deviation of
Temperature and Power)
AV
RT
1020
0
V
DD
= 4.75 to 5.25 V
Ta = 40 to 85
C
0.3
--
0.3
dB
Absolute Delay
T
D
1020
0
A to A Mode
BCLK = 2048 kHz
--
0.58
0.6
ms
T
GD
T1
500
--
0.26
0.75
T
GD
T2
600
--
0.16
0.35
T
GD
T3
1000
--
0.02
0.125
T
GD
T4
2600
--
0.05
0.125
Transmit Group Delay
T
GD
T5
2800
0
*2
--
0.07
0.75
ms
T
GD
R1
500
--
0.00
0.75
T
GD
R2
600
--
0.00
0.35
T
GD
R3
1000
--
0.00
0.125
T
GD
R4
2600
--
0.09
0.125
Receive Group Delay
T
GD
R5
2800
0
*2
--
0.12
0.75
ms
CR
T
Trans to Receive
75
83
--
CR
R
Receive to Trans
75
80
--
Cross Talk
Attenuation
CR
CH
1020
0
Channel to Channel
75
78
--
dB
Discrimination
DIS
4.6 to
72k
0
0 to 4 kHz
30
32
--
dB
Out of Band Spurious
OBS
300 to
3.4K
0
4.6 to 1000 kHz
--
37.5
35
dB
SFD
T
--
50
40
Signal Frequency
Distortion
SFD
R
1020
0
0 to 4 kHz
--
48
40
dBm0
IMD
T
--
50
40
Intermodulation Distortion
IMD
R
fa = 470
fb = 320
4
2 fa fb
--
54
40
dBm0
PSR
T1
0 to 4k
40
44
--
PSR
T2
4 to 50k
50
55
--
PSR
R1
0 to 4k
40
45
--
Power Supply Noise
Rejection Ratio
PSR
R2
4 to 50k
100
mVrms
*3
50
56
--
dB
*1
C-message filter used
*2
Minimum value of the group delay distortion
*3
Under idle channel noise
FEDL7033-02
1Semiconductor
ML7033
12/51
AC Characteristics (Continued)
(V
DD
= 4.75 to 5.25 V, Ta = 40 to +85
C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
t
SD
--
--
100
t
XD1
--
--
100
t
XD2
PCMOUT
Pull-up resister = 0.5 k
C
L
= 50 pF and 1 LSTTL
--
--
100
ns
t
XD3
--
--
100
Digital Output Delay Time
t
XD4
PCMOSY, C
L
= 50 pF
--
--
100
ns
PCMOUT Operation Delay
Time
t
DDO
Time to operation
after Power-down release
--
4
--
ms
AOUTn/TOUTn Signal Output
Delay Time
t
DAO
Time to baseband signal output
after power-on
--
4
--
ms
t
1
50
--
--
ns
t
2
50
--
--
ns
t
3
50
--
--
ns
t
4
50
--
--
ns
t
5
100
--
--
ns
t
6
50
--
--
ns
t
7
50
--
--
ns
t
8
--
--
50
ns
t
9
50
--
--
ns
t
10
50
--
--
ns
Serial Port I/O Setting Time
t
11
C
LOAD
= 50 pF
--
--
50
ns
EXCK Clock Frequency
f
EXCK
EXCK
0.5
--
10
MHz
t
20
--
--
200
ns
t
21
--
20
--
s
t
22
--
--
200
ns
t
23
--
--
200
ns
SLIC Interface Delay Time
t
24
--
--
225
ms
FEDL7033-02
1Semiconductor
ML7033
13/51
TIMING DIAGRAM
Transmit Timing - 8-bit PCM Mode with LIN (CR0-B3) bit = "0"
Long Frame Sync Mode with SHORT (CR0-B4) bit = "0"
MCK
BCLK
XSYNC
PCMOUT
PCMOSY
t
XS
D2
1
2
3
4
5
6
7
8
t
SX
t
XD1
t
SD
D3
D4
D5
D6
D7
D8
MSD
t
W S
t
XD2
t
MB
t
XD3
t
XD4
Short Frame Sync Mode with SHORT (CR0-B4) bit = "1"
MCK
BCLK
XSYNC
PCMOUT
PCMOSY
t
SX
D2
1
2
3
4
5
6
7
8
t
XS
t
XD1
D3
D4
D5
D6
D7
MSD
t
W S
t
XD2
t
MB
t
XD3
t
XD4
D8
Figure 1 Transmit Side Timing Diagram
Receive Timing - 8-bit PCM Mode with LIN (CR0-B3) bit = "0"
Long Frame Sync Mode with SHORT (CR0-B4) bit = "0"
t
RS
D2
1
2
3
4
5
6
7
8
t
SR
t
DS
t
W S
t
DH
D3
D4
D5
MS D
D6
D7
D8
t
MB
MCK
BCLK
RSYN C
PCMIN
Short Frame Sync Mode with SHORT (CR0-B4) bit = "1"
t
SR
D2
1
2
3
4
5
6
7
8
t
RS
t
DS
t
W S
t
DH
D3
D4
D5
MS D
D6
D7
t
MB
MCK
BCLK
RSYN C
PCMIN
Figure 2 Receive Side Timing Diagram
Note: The above timings are also valid in 14-bit linear PCM Mode with the LIN (CR0-B3) bit = "1",
except that the number of data bits on the PCMIN and PCMOUT signals changes from 8 to 14.
FEDL7033-02
1Semiconductor
ML7033
14/51
PCM Interface Bit Configuration
8-bit PCM Mode with LIN (CR0-B3) bit ="0" & Long Frame Sync Mode with SHORT (CR0-B4) bit = "0"
BCLK
RSYNC
PCMIN
PCMOUT
PCMOSY
1
9
17
25
1
MS
D
D2
D3
D4
D5
D6
D7
D8
MS
D
D2
D3
D4
D5
D6
D7
D8
MS
D
D2
D3
CH1 PCM DATA
CH2 PCM DATA
14-bit Linear PCM Mode with LIN (CR0-B3) bit = "1" & Long Frame Sync Mode with SHORT (CR0-B4) bit = "0"
BCLK
RSYNC
PCMIN
PCMOUT
PCMOSY
1 9 17 25 1
MS
D
D2
D3
MS
D
D1
0
D2
D3
D4
D5
D6
D7
D8
D9
D1
1
D1
2
CH1 Linear DATA
D1
3
D1
4
MS
D
D1
0
D2
D3
D4
D5
D6
D7
D8
D9
D1
1
D1
2
CH2 Linear DATA
D1
3
D1
4
8-bit PCM Mode with LIN (CR0-B3) bit = "0" & Short Frame Sync Mode with SHORT (CR0-B4) bit = "1"
BCLK
RSYNC
PCMIN
PCMOUT
PCMOSY
1
9
17
25
1
MS
D
D2 D3 D4 D5 D6 D7 D8
MS
D
D2 D3 D4 D5 D6 D7 D8
MS
D
D2 D3
CH1 PCM DATA
CH2 PCM DATA
14-bit Linear PCM Mode with LIN (CR0-B3) bit = "1" & Short Frame Sync Mode with SHORT (CR0-B4) bit = "1"
BCLK
RSYNC
PCMIN
PCMOUT
PCMOSY
1
9
17
25
1
MS
D
D2 D3
MS
D
D1
0
D2 D3 D4 D5 D6 D7 D8 D9
D1
1
D1
2
CH1 Linear DATA
D1
3
D1
4
MS
D
D1
0
D2 D3 D4 D5 D6 D7 D8 D9
D1
1
D1
2
CH2 Linear DATA
D1
3
D1
4
Figure 3 PCM Interface Bit Configuration
FEDL7033-02
1Semiconductor
ML7033
15/51
SGC, PCMOUT, and AOUT Output Timing
PDN
MO
D
E
n
-
b
i
t
PCM
O
U
T
SG
C
t
DDO
t
DA
O
AO
UTn
SG
L
e
v
e
l
H
i
gh I
m
pe
dance
O
FF
ON
t
SG
C
SG
G
ND
Hi
g
h
i
m
pe
da
n
c
e
Figure 4 SGC, PCMOUT, and AOUT Output Timing
FEDL7033-02
1Semiconductor
ML7033
16/51
MCU Serial Interface
Figure 5 MCU Serial Interface
SLIC Interface
DEN


EXCK


SLIC_I/F
*5


E0_n
14
t
20
13
t
21
16
15
*5 SLIC_I/F = F2_n pin, F1_n pin, F0_n, SWCn pin, BSELn pin
Figure 6 SLIC Interface 1 (to SLIC)
t
24
ALMn, DETn

INT (from ALMn)

INT (from DETn)
t
22
t
23
t
23
Either ALMn pin or DETn pin,or
DEN pin (CR6 and CR13)
Figure 7 SLIC Interface 2 (from SLIC)
* The INT pin driven to a logic "1" in either of the following cases
;
(1) (
PDN pin = logic "1") Any of the ALMn or DETn pins (maximum 4 pins concerned) in a logic "0"
state go to logic "1".
(2) (
PDN pin = logic "0") All of the ALMn or DETn pins (maximum 4 pins concerned) in a logic "0" state
go to logic "1".
(3) Both SLIC 1 control (CR6) and SLIC 2 control (CR13) are read by the MCU.

DEN
EXCK
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
11
t
10
W A4 A3 A2 A1 A0
B1
DIO
(Write)
R A4 A3 A2 A1 A0
B1 B0
DIO
(Read)
1 2 3 4 5 6
13
14 15
B0
FEDL7033-02
1Semiconductor
ML7033
17/51
FUNCTIONAL DESCRIPTION
Pin Functional Description
AIN1N, AIN1P, AIN2N, AIN2P, GSX1, GSX2
The AINnN and AINnP pins are the transmit path analog inputs for Channel-n, where n equals channel 1 or
channel 2. The AINnN pin is the inverting input, and the AINnP pin is the non-inverting input for the op-amp.
The GSXn pin functions as the transmit path level adjustment for Channel-n and is connected to the output of the
op-amp. It is used to adjust the output level as shown in Figure 8 below.
When the AINnN or AINInP pins are not in use, connect the AINnN pin to the GSXn pin and the AINnP pin to
the SGC pin. During power-down mode, the GSXn output is in a high impedance state.
In the case of the analog input 2.226 Vpp at the GSXn pin, the digital output will be +3.00 dBm0.
CH1 Gain
Gain = R2/R1
10
R1: Variable
R2
>
20 k
C1
>
1/(2
3.14
30
R1)
CH2 Gain
Gain = R4/R3
10
R3: Variable
R4
>
20 k
C2
>
1/(2
3.14
30
R3)
CH2
Analog
Input
GSX2
AIN2N
SGC
R4
R3
C2
CH1
Analog
Input
GSX1
AIN1N
SGC
R2
R1
C1
AIN1P
AIN1P
Figure 8 Example of Analog Input Setting Schematic
AOUT1P, AOUT1N, AOUT2P, AOUT2N
The AOUTnN and AOUTnP pins are the receive path analog outputs from Channel-n, where n equals channel 1
or channel 2. These pins can drive a load of 20 k
or more. When the AOUTnSEL register bit (CR7-B7/CR14-
B7) is cleared (0), the AOUTnP pin is a single-ended output from Channel-n and the AOUTnN pin is at high
impedance. When the AOUTnSEL bit is set (1), the AOUTnN and AOUTnP pins are differentials outputs from
the corresponding channel.
The output signal from each of these pins has an amplitude of 3.4 Vpp above and below the signal ground
voltage (SG). Hence, when the maximum PCM code (+3.00 dBm0) is input to the PCMIN pin, the maximum
amplitude between the AOUTnN pin and the AOUTnP pin will be 6.8 Vpp.
While the device is in power-down mode, or the corresponding channel (1 or 2) is in power saving mode, the
related outputs are high impedance. Refer to Table 5 for more information.
FEDL7033-02
1Semiconductor
ML7033
18/51
TOUT1, TOUT2
TOUTn is the tone analog output for the corresponding channel. The output signal has an amplitude of 2.5 Vpp
above and below the signal ground voltage (SG). While the device is in power-down mode, or the corresponding
channel is in power-save mode, the related outputs are high impedance.
V
DDA
, V
DDD
+5 V power supply for analog and digital circuits. The V
DDA
pin is the power pin for the analog circuits. The
V
DDD
pin is the power pin for the digital circuits. If these signals are connected together externally, The V
DDA
pin
must be connected to the V
DDD
pin in the shortest distance on the printed circuit board. Internal to the ML7033,
the V
DDA
plane is separate from the V
DDD
plane.
To minimize power supply noise, a 0.1
F bypass capacitor (with excellent high frequency characteristics) and a
10
F electrolytic capacitor should be connected between the V
DDA
pin and the AG pin. In addition, the same
capacitive network should also be connected between the V
DDD
pin and the DG pin. If the AG and DG pins are
connected together externally, only one capacitive network is required.
AG, DG
The AG pin is a ground for the analog circuits. The DG pin is a ground for the digital circuits.
The analog ground and the digital ground are separated internally within the device. The AG pin and DG pins
must be connected in the shortest distance on the printed circuit board, and then to system ground with a low
impedance.
SGC
The SGC pin used is to internally generate the signal ground voltage level by connecting a bypass capacitor. The
output impedance is approximately 50 k
. Connect a 0.1
F bypass capacitor with excellent high frequency
characteristics between the SGC pin and the AG pin. During power-down mode, the SGC output is at the voltage
level of the AG pin.
SG
The SG pin is the signal ground level output for the system circuits. The output voltage is 2.4 V, the as same as
the SGC pin in a normal operating state. During power-down mode, this output is high impedance.
MCK
Master clock input. Input either 2.048 or 4.096 MHz clock. After turning on the power, the appropriate value
must be written into the MCKSEL bit (CR0-B5) depending upon the desired master clock frequency.
If the supplied master clock frequency and the value of the MCKSEL bit (CR0-B5) do not match, the power-
down control circuit and the MCU interface circuit will continue to operate properly. Access to the control
registers can also occur. However, other circuits may not operate properly.
As for the power-on sequence, please refer to "Power-On Sequence" in the later page.
FEDL7033-02
1Semiconductor
ML7033
19/51
BCLK
Shift clock signal input for the PCMIN and the PCMOUT signals. The clock frequency, equal to the data rate, is
256 kHz to 4096 kHz. This signal must be generated from the same clock source as the master clock and
synchronized in phase with the master clock. Please refer to Figures 1 and 2 for more information about the
phase difference between MCK and BCLK.
RSYNC
Receive synchronizing clock input. The PCMIN signals are received in synchronization with this clock. The 8
kHz input clock is generated from the identical clock source as MCK and must be synchronized in phase with
the master clock.
XSYNC
Transmit synchronizing clock input. The PCMOUT signals are transmitted in synchronization with this clock.
The 8 kHz input clock is generated from the identical clock source as MCK and must be synchronized in phase
with the master clock.
PCMIN
Serial PCM data input. The serial PCM data input on the PCMIN pin is converted to analog signals and output
from the AOUTnP pin (or from the AOUTnN pin and the AOUTnP pin) in synchronization with the RSYNC
clock and the BCLK clock.
When in Long Frame Sync Mode (CR0-B4 = "0"), the first bit of the serial PCM data (MSD of channel 1) is
identified at the rising edge of the RSYNC clock.
When in Short Frame Sync Mode (CR0-B4 = "1"), the first bit of the serial PCM data (MSD of channel 1) is
identified at the falling edge of the RSYNC clock.
PCMOUT
Serial PCM data output. Channel 1 data is output in sequential order, from most significant data (MSD) to least
significant data (LSD). Data is synchronized with the rising edge of BCLK.
When in Long Frame Sync Mode (CR0-B4 = "0"), the first bit of PCM data may be output at the rising edge of
the XSYNC signal, depending on the timing between BCLK and XSYNC.
When in Short Frame Sync Mode (CR0-B4 = "1"), the first bit of PCM data may be output at the falling edge of
the XSYNC signal, depending on the timing between BCLK and XSYNC.
This pin is in a high impedance state during power-down. A pull-up resistor must be connected to this pin since
it is an open drain output.
PCMOSY
PCMOSY is asserted to a logic 0 when PCM data is valid on the PCMOUT pin. This includes both normal mode
and power-save mode.
When PCM data is not being output from the PCMOUT pin (including during power-down mode), this pin goes
a logic "1".
This signal is used to control the TRI-STATE Enable of a backplane line-driver.
FEDL7033-02
1Semiconductor
ML7033
20/51
Table 1 PCM Codes in 8-bit PCM Mode with the LIN (CR0-B3) bit = "0"
PCMIN/PCMOUT
ALAW (CR0-B2) bit = "0" (
-law )
ALAW (CR0-B2) bit = "1" (A-law )
INPUT/OUTPUT
Level
MSD D2 D3 D4 D5 D6 D7 D8 MSD D2 D3 D4 D5
D6
D7
D8
+Full scale
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
+0
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
0
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
Full scale
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
Table 2 PCM Codes in 14-bit Linear PCM Mode with the LIN (CR0-B3) bit = "1"
PCMIN/PCMOUT
INPUT/OUTPUT
Level
MSD
D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
D12
D13
D14
+Full scale
0
1
1
1
1
1
1
1
1
1
1
1
1
1
+1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Full scale
1
0
0
0
0
0
0
0
0
0
0
0
0
0
PDN
Power-down control signal. When
PDN is a asserted (logic "0"), both the channel 1 and channel 2 circuits enter
the power-down state. However, even in power-down mode, the state of the control registers is maintained.
Reads and writes to the registers are also possible, and the state of the
INT pin also changes in accordance with
inputs from the SLIC devices. This pin is deasserted (logic "1") by external logic during normal operation.
This power-down function is available even in power saving mode by the MODEn (CR0-B1/CR0-B0) bit.
RESET
An input to reset control registers. By asserting the
RESET pin (applying a logic "0"), all control registers are
initialized. During a normal operation mode, set this pin logic "1".
Table 3 State of PCMOUT in 8-bit PCM Mode with LIN (CR0-B3) bit = "0"
PDN pin
MODE1 bit
MODE0 bit
ALAW bit
CH2 PCM Data
CH1 PCM Data
0
0/1
0/1
0/1
Hi-Z *1
Hi-Z *1
0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1
0
0
1
1 1 0 1 0 1 0 1
1 1 0 1 0 1 0 1
0
1 1 1 1 1 1 1 1
Operate
1
0
1
1
1 1 0 1 0 1 0 1
Operate
0
Operate
1 1 1 1 1 1 1 1
1
1
0
1
Operate
1 1 0 1 0 1 0 1
0
Operate
Operate
1
1
1
1
Operate
Operate
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Table 4 State of PCMOUT in 14-bit Linear PCM Mode with LIN (CR0-B3) bit = "1"
PDN pin
MODE1 bit
MODE0 bit
ALAW bit
CH2 PCM Data
CH1 PCM Data
0
0/1
0/1
Hi-Z *1
Hi-Z *1
1
0
0
ALL "0"
ALL "0"
1
0
1
ALL "0"
Operate
1
1
0
Operate
ALL "0"
1
1
1
0/1
Operate
Operate
Table 5 State of Analog Output Pins
PDN
pin
MODE1
bit
MODE0
bit
GSX1
pin
GSX2
pin
AOUT1
pin
AOUT2
pin
SG
pin
SGC
pin
MCU
Interface
0
0/1
0/1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
AG level *2 Operate
1
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
AG level *2 Operate
1
0
1
Operate
Hi-Z
Operate
Hi-Z
Operate
Operate
Operate
1
1
0
Hi-Z
Operate
Hi-Z
Operate
Operate
Operate
Operate
1
1
1
Operate
Operate
Operate
Operate
Operate
Operate
Operate
*1
The data will be `H' by an external pull-up resistor.
*2 Output impedance = about 50 k
F2_1, F1_1, F0_1, F2_2, F1_2, F0_2
The F2_n, F1_n and F0_n pins are data outputs used when the SLIC connected to the corresponding channel is
an Intersil RSLIC
TM
series device. The output levels from the F2_n, the F1_n and F0_n pins are determined by
the F2_n, F1_n, and F0_n register bits (CR6-B7 to B5 and CR13-B7 to B5). By inputting these outputs directly
into the corresponding input pin of the SLIC device, the SLIC operating mode selection is possible.
Even in the power-down state with the
PDN pin is asserted, these pins remain functional.
E0_1, E0_2
The E0_n pins are the detector mode selection data outputs. These pins are used when the SLIC connected to the
corresponding channel is an Intersil RSLIC
TM
series device. Though the output level from the E0_n pin is
determined by the E0_n bit (CR6-B2/CR13-B2), the output level changes in 20
s (= hold timer) in the power-
on mode with the
PDN pin = logic "1" and in 200 ns in the power-down mode with the PDN pin = logic "0"
after the change of E0_n bit (CR6-B2 /CR13-B2). Refer to Figure 6 for information.
What event is actually detected by the SLIC is determined by the combination of the F2_n, F1_n, F0_n and E0_n
pins. Refer to Table 6 for more information. By connecting the output directly into the corresponding input pin
of the SLIC device, detector mode selection in the SLIC is possible. Even in the power-down state with the
PDN
pin = logic "0", this pin remains functional. However, the hold timer is ignored in this state.
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Table 6 SLIC Device Operation Mode and Detector Mode
Operating Mode
F2_n
F1_n
F0_n
E0_n = 1
E0_n = 0
Description
Low Power Standby
0
0
0
SHD
GKD
Standby mode
Forward Active
0
0
1
SHD
GKD
Forward battery loop feed
Unbalanced Ringing
0
1
0
RTD
RTD
Unbalanced ringing mode
Reverse Active
0
1
1
SHD
GKD
Reverse battery loop feed
Ringing
1
0
0
RTD
RTD
Balanced ringing mode
Forward Loop Back
1
0
1
SHD
GKD
Test mode
Tip Open
1
1
0
SHD
GKD
For PBX type application
Power Denial
1
1
1
n/a
n/a
Device shutdown
SHD: Switch Hook Detection RTD: Ring Trip Detection GKD:Ground Key Detection
BSEL1, BSEL2
The BSELn pin is the battery mode selection data output. This pin is used when the SLIC connected to the
corresponding channel is an Intersil RSLIC
TM
series SLIC device. A logic "0" on this pin selects the low battery
mode, and the logic "1" selects the high battery mode within the SLIC device. The output levels from the BSELn
pins are determined by the BSELn register bits (CR6-B3/CR13-B3).
By connecting these outputs directly to the corresponding SLIC device input pins, battery mode selection of the
SLIC is possible. This pin remains functional even in power-down mode.
SWC1, SWC2
The
SWCn pin is the uncommitted switch control data output. This pin is used when the SLIC connected to the
corresponding channel is an Intersil RSLIC
TM
series SLIC device. By connecting this pin directly to the
corresponding input pin of the SLIC device, the uncommitted switch control can be made. The uncommitted
switch is located between the SW+ pin and the SW- pin. A logic "0" on this pin enables the SLIC internal switch
on, and a logic "1" disables the switch.
The output levels from the
SWC1 and SWC2 pins are determined by the SWCn register bits (CR6-B4/CR13-
B4). This pin remains functional even in power-down mode with the
PDN pin is a logic "0".
DET1, DET2
The
DETn pins are the SLIC's detection signal (switch hook, ring trip or ground key detection) inputs. These
pins are used when the SLIC connected to the corresponding channel is an Intersil RSLIC
TM
series device. A
logic "0" on this pin clears the corresponding
DETn register bit (CR6-B1/CR13-B1). A logic `1' on this pin
input sets the register bit.
The Intersil RSLIC
TM
series SLIC device is equipped with a function to switch the output on its
DET pin from a
logic "1" state to a logic "0" state when it detects an assigned event of either off-hook, ring trip or ground key.
Therefore, by connecting these pins to the corresponding pins on the SLIC device and reading the
DETn register
bit (CR6-B1/CR13-B1), the occurrence of an assigned event can be detected.
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The event detected by the SLIC is determined by the F2_n, F1_n, and F0_n register bits (CR6-B7 to B5/CR13-
B7 to B5), and the E0_n register bits (CR6-B2 /CR13-B2). To avoid the unintended detection of these conditions
due to glitches on the
DETn signal of the SLIC, the ML7033 is equipped with a debounce timer to hold the DET
register bit (CR6-B1/CR13-B1) and the output of the
INT pin for a set period, even when an input to the DETn
pin changes from a logic "1" to a logic "0". For more information on the debounce timer, refer to the
DETnTIM3 through DETnTIM0 register bit descriptions (CR4-B7 to B0).
This pin remains functional in power-down mode (
PDN pin low). However, while in the power-down state, the
debounce timer is disabled.
When this pin is not used, it should be tied to V
DDD
.
ALM1, ALM2
The
ALMn pins are the thermal shut down alarm signals. These pins are used when the SLIC connected to the
corresponding channel is an Intersil RSLIC
TM
series device. A logic "0" on the
ALMn input pin clears the
corresponding ALM register bit (CR6-B0/CR13-B0). A logic "1" on this pin sets the bit.
The Intersil RSLIC
TM
series device is equipped with a function that allows it to automatically enter power-down
mode and toggle its
ALMn pin from a logic "1" to a logic "0" state when the SLIC die temperature exceeds a
safe operating temperature. Hence, by connecting the corresponding pin of the SLIC device to the
ALM1 and
ALM2 pins and reading the ALM register bit (CR6-B0/CR13-B0), it is possible to know whether the concerned
SLIC device is operating normally, or is in a thermal shutdown state.
This pin remains functional in power-down mode. However, while in the power-down state, the debounce timer
is disabled.
When this pin is not used, it should be tied to V
DDD
.
INT
The ML7033 asserts the
INT interrupt pin when either the DETn pin or the ALMn pin are asserted by the SLIC
device when the device is an Intersil RSLIC
TM
series SLIC device. The Intersil RSLIC
TM
series device is
equipped with detector and thermal shut down alarm functions to notify a change of SLIC state by driving a
logic 0 onto the output pins connected to
DETn and ALMn. Refer to the DETn and ALMn pin descriptions
above. By monitoring the state of the
INT pin and reading the DETn (CR6-B0/CR13-B0) and ALMn (CR6-
B0/CR13-B0) register bits, it is possible to know that a change of a state occurred within the SLIC device.
The
INT pin transitions from a logic "1" to a logic "0" in the following cases;
(1) (
PDN pin = logic "0") Any of the ALMn or DETn pins in the logic "1" state transition to the logic "0"
state.
(2) (
PDN pin = logic "1") Any of the ALMn or DETn pins transition from the logic "1" state to the logic "0"
state when all the four pins (
ALM1, ALM2, DET1, and DET2) have been in the logic "1" state.
Note that the debounce timer with the
DETn pin is not valid while in power-down mode (PDN pin = logic "0").
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The
INT pin is released to the logic "1" state in either of the following cases;

(1) (
PDN pin = logic "1") Any one of the ALMn or DETn pins in the logic "0" state transition to the logic "1"
state.
(2) (
PDN pin = logic "0") All of the ALMn or DETn pins in the logic "0" state transition to the logic "1"
state.
(3) Both SLIC 1 control (CR6 register) and SLIC 2 control (CR13 register) are read by the MCU.
Note that the debounce timer, which works when the
DETn pin changes from a logic "1" state to a to logic "0"
state, does not work when the pin changes from logic "0" to logic "1".
DEN, EXCK, DIO
Serial control ports for the MCU interface. These pins are used by an external MCU to access the internal control
registers of the ML7033. The
DEN pin is the data enable input. The EXCK pin is the data shift clock input. The
DIO pin is the address and data input/output. Figure 9 shows the MCU interface input/output timing diagram.
Note that EXCK must be a continuous clock of at least 15 pulses or more.
R
A4
A3
A2
A1
A0
B7
B6
B5
B4
B3
B2
B1
B0
EXCK
DEN
DIO (I)
W
A4
A3
A2
A1
A0
B7
B6
B5
B4
B3
B2
B1
B0
EXCK
DEN
DIO (O)
Write timing
Read timing
Input
Output
Figure 9 MCU Interface Timing Diagram
CIDATA1, CIDATA2
The CIDATA1 and CDATA2 data inputs are used for Caller ID generation. While in a Caller ID tone generation
mode with the CIDCHnON register bit set, (CR1-B1/CR1-B0), signals on the CIDATAn pins are modulated in
either the ITU-T V.23 or Bell 202 schemes. The scheme is determined by the CIDFMT register bit (CR1-B2),
and output from the analog output pin(s).
The analog output pins for modulated Caller ID data can be selected by the CHnTG2TX (CR7-B6/CR14-B6),
the CHnTGTOUTn (CR7-B5/CR14-B5), and the AOUTnSEL (CR7-B7/CR14-B7) register bits.
The output level for the modulated Caller ID data can be tuned by the CHnTG1LVn (CR9-B7 to B1/CR16-B7 to
B1) register bits.
TEST
The TEST input is used for testing purposes only during the manufacturing process and has no function once the
testing process is completed. This pin is not used during normal operation of the device and should be kept at a
logic "0" state.
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Power-On Sequence
While in the power-on state, the following chart is recommended.
Figure 10 Power-on Sequence Flow Chart
As the ML7033 is equipped with a power-on
reset function, initialization of the control
registers automatically occurs as the power is
turned on, even with the
RESET pin = logic "1".
However, if any of input pins are not in a high
impedance state, the power-on reset may not
function properly.
Control Register Setting
(CH1/CH2)
Normal Operation
PDN pin = "1"
Even during power-down mode with the
PDN
pin = logic "0", the SLIC interface registers
(CR6, CR13) and the
INT pin are working. Data
set in other registers becomes valid after the
PDN pin is driven to a logic "1" state.
POWER OFF
Power supply on
<Recommendation>
PDN pin = logic "0", RESET pin= "0"
RESET pin = "0" to "1"
(or Power-on Reset Function)
Keep the input to the
RESET pin in the logic "0"
state for 100ns or longer before changing to a
logic "1".
<NOTE>
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Control Registers Functional Description
CR0 (Basic operating mode)
B7
B6
B5
B4
B3
B2
B1
B0
CR0
FILTER1SEL
FILTER2SEL
MCKSEL
SHORT
LIN
ALAW
MODE1
MODE0
default
0
0
0
0
0
0
0
0
B7
... Transmit and receive filter select for CH1
0 : ITU-T G.714 filter
1 : wideband filter for V.90 data modem application
B6
... Transmit and receive filter select for CH2
0 : ITU-T G.714 filter
1 : wideband filter for V.90 data modem application
B5
... MCK frequency select
0 : 2.048 MHz
1 : 4.096 MHz
B4
... Frame synchronizing scheme select
0 : Long frame SYNC 1 : Short frame SYNC
Refer to Figure 3.
B3
... PCM companding law select
0 : 8-bit PCM mode
1 : 14-bit linear PCM (2's complement) mode
"1" is selected, a setting with the ALAW (CR0-B2) bit is ignored.
B2
... PCM companding law select
0 :
-law
1 : A-law
When the LIN (CR0-B3) is "1", a setting with this bit is ignored.
B1, B0
... Power saving control
0 : Power saving mode
1 : Normal operation
The MODE1 (CR0-B1) bit is for channel 2, and the MODE0 (CR0-B0) bit is for channel 1.
In power saving mode, power for the corresponding channel is turned off except for the last
output stage of the PCMOUT pin. The power saving mode differs from the power-down
mode controlled by the
PDN pin in the following aspects;
- Possible to control a state for an individual channel independently
- The last stage of the PCMOUT pin is operational, and outputs `positive zero' PCM code
in the 8-bit PCM mode or `zero' PCM code in the 14-bit Linear PCM mode during the
assigned time slot.
- Debounce timer and hold timer are valid.
As in power-down mode, the power saving mode does not initialize control registers and
read and write of control registers are possible in the power saving mode. The power-down
mode setting by the
PDN pin takes precedence over the power saving mode.
Table 7 Mode Settings for CH1 and CH2
Power of Channel
MODE1
bit
MODE0
bit
PDN
pin
RESET
pin
CH2
CH1
Register
0
*1
0
*1
0
0
OFF
OFF
Initialized to default
0
*1
0
*1
1
0
OFF
*2
OFF
*2
Initialized to default
0/1
0/1
0
1
OFF
OFF
Read/Write possible
0
0
1
1
OFF
*2
OFF
*2
Read/Write possible
0
1
1
1
OFF
*2
ON
Read/Write possible
1
0
1
1
ON
OFF
*2
Read/Write possible
1
1
1
1
ON
ON
Read/Write possible
*1 forced to be default by the
RESET pin = logic "0".
*2 The last output stage is powered.
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CR1 (Tone generator and Call ID tone control)
B7
B6
B5
B4
B3
B2
B1
B0
CR1
CH2TG
ON
CH1TG
ON
CIDFMT
CID
CH2ON
CID
CH1ON
default
0
0
0
0
0
0
0
0
B7
... State control for a tone generator on CHl
0 : disabled
1 : enabled
B6
... State control for a tone generator on CH2
0 : disabled
1 : enabled
B5, B4, B3
... Reserved (The default alternation is prohibited.)
When a write action is executed for CR1, set these bits to "0".
B2
... Caller ID generator modulation scheme select
0 : ITU-T V.23 scheme (1: 1300 Hz, 0: 2100 Hz)
1 : Bell 202 format (1: 1200 Hz, 0: 2200 Hz)
B1
... State control for Caller ID generator on CH2
0 : OFF
1 : ON
Regardless of how the CH2TGON bit (CR1-B7) is set, signals input into the CIDATA2 pin
are modulated and output as Caller ID tones. When this bit is set, the level setting by the
CH2TG1LVn (CR16-B7 to B1) bits is valid, but the CH2TG1_n (CR16-B0/CR17-B7 to
B0) bits, CH2RING (CR11-B7) bit, and CH2TG1TRPn (CR11-B6 to B4) bits are invalid.
B0
... State control for Caller ID generator on CH1
0 : OFF
1 : ON
Regardless of how the CH1TGON bit (CR1-B6) is set, signals input into the CIDATA1 pin
are modulated and output as Caller ID tones. When this bit is set, the level set by the
CH1TG1LVn (CR9-B7 to B1) bits is valid, but the CH1TG1_n (CR9-B0/CR11-B7 to B0)
bits, the CH1RING (CR11-B3) bit, and the CH1TG1TRPn (CR11-B2 to B0) bits are
invalid.
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CR2 (Pulse metering tone generator control)
B7
B6
B5
B4
B3
B2
B1
B0
CR2
PMG2
FRQ
PMG2
LV1
PMG2
LV0
PMG2
TOUT2
PMG1
FRQ
PMG1
LV1
PMG1
LV0
PMG1
TOUT1
default
0
0
0
0
0
0
0
0
B7
... Pulse metering tone frequency select for CH2
0 : 12 kHz
1 : 16 kHz
B6, B5
... Pulse metering tone level setting for CH2
(B6, B5) (0, 0) = OFF
(0, 1) = 0.5 Vpp
(1, 0) = 1.0 Vpp
(1, 1) = 1.5 Vpp
The level of the pulse metering tone, as shown in Figure 11, reaches the assigned level in
10 ms and gradually fades out over 10 ms.
The ramp-up and ramp-down times also apply when a tone is cancelled by writing (0,0)
into these register bits. Once the register bits are set, the tone begins to fade out and
completely fades out after 10 ms. In addition, subsequent writes to these bits are prohibited
for 10 ms.
Figure 11 Pulse Metering Tone Waveform
B4
... Pulse metering tone output pin select for CH2
0 : AOUT2 pin (added to voice signals)
1 : TOUT2 pin
B3
... Pulse metering tone frequency select for CH2
0 : 12 kHz
1 : 16 kHz
B2, B1
... Pulse metering tone level setting for CH1
(B2, B1) (0,0) = OFF
(0, 1) = 0.5 Vpp
(1, 0) = 1.0 Vpp
(1, 1) = 1.5 Vpp
The level of the pulse metering tone, as shown in Figure 11, reaches the assigned level in
10 ms and gradually fades over 10 ms.
The ramp-up and ramp-down times also apply when a tone is cancelled by writing (0,0)
into these register bits. In this case the tone fades out after 10 ms. In addition, subsequent
writes to these bits are prohibited for 10 ms.
B0
... Pulse metering tone frequency select for CH1
0 : 12 kHz
1 : 16 kHz
Ramp up time=10ms
Ramp down time=10ms
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CR3 (Time slot assignment control)
B7
B6
B5
B4
B3
B2
B1
B0
CR3
TSAE
TSAC
TSA5
TSA4
TSA3
TSA2
TSA1
TSA0
default
0
0
0
0
0
0
0
0
* CR3 is a write only register.
B7
... Time slot assignment customization enable
0 : Default time slot assignment
1 : Customized time slot assignment
The default time slot assignment is CH1 for Slot 0 and CH2 for Slot 2.
B6
... Time slot assignment channel select
0 : CH1
1 : CH2
This bit is used to specify the channel for which the accompanied TSAn
(CR3-B5 to B0) bits are going to assign a time slot. Hence, when a customized time slot
assignment is enabled, CR3 should be written twice; once for CH1 and another for CH2.
B5 to B0
... Assigned time slot select
Each time slot consists of 8 BCLK cycles. The number of time slots available for time slot
assignment depends upon the applied BCLK frequency, and can be calculated in the
following equations;
Number of time slots available for time slot assignment
= (BCLK frequency)/(SYNC frequency)/8
= (BCLK frequency)/64k
For instance, when the BCLK frequency is 4096 kHz, time slots that can be assigned are
from 0 (000000) to 63 (111111). The specification of a time slot beyond 63 is prohibited.
Note that in 14-bit linear PCM (2's complement) mode, specified when the LIN bit (CR0-
B3) is set, only even numbered time slots (0, 2, 4, ... 62) can be assigned.
In any mode, the assigned time slot for a channel is common both for transmit and receive,
and different time slots cannot be assigned for transmit and receive. When the TSAE bit
(CR3-B7) is cleared, the time slot assignment specified by these bits is ignored, and the
default time slots are assigned (CH1 for Time Slot 0 and CH2 for Time Slot 2). Figure 12
shows an example of how CH1 is assigned for Time Slot 0 (000000) and CH2 is assigned
for Time Slot 3 (000011) in 8-bit PCM mode.
MSD
D2
D3
D4
D5
D6
D7
D8
BCLK
XSYNC
PCMOUT/
PCMIN
PCMOSY
1
9
17
25
33
CH1 PCM DATA
MSD
D2
D3
D4
D5
D6
D7
D8
CH2 PCM DATA
Slot 0
Slot 1
Slot 2
Slot 3
Figure 12 Example of Time Slot Assignment: CH1 = Slot 0, CH2 = Slot 3
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CR4 (Debounced timer setting)
B7
B6
B5
B4
B3
B2
B1
B0
CR4
DET2
TIM3
DET2
TIM2
DET2
TIM1
DET2
TIM0
DET1
TIM3
DET1
TIM2
DET1
TIM1
DET1
TIM0
default
0
0
0
0
0
0
0
0
B7 to B4
... Debounce timer setting for CH2
B3 to B0
... Debounce timer setting for CH1
To avoid the unintended detection of glitches on the
DETn signal, the ML7033 is equipped with
a debounce timer to hold the
DETn (CR6-B1/CR13-B1) bit and the INT output state for a set
period, even when the state of the
DETn pin changes from logic "1" to logic "0". Bits B7 to B4
determine the debounce timer setting for CH2. Bits B3 to B0 determine the debounce timer
setting CH1.
The debounce timer is operational only in the power-on state when the
PDN pin = logic "1",
and remains operational in the power-saving mode with the MODEn (CR0-B1, B0) bits = "0" as
long as the device is in the power-on state.
The debounce timer holding time ranges from 0 ms to 225 ms at 15 ms intervals for each
individual channel. The values written into B7 to B4 (channel 2) or B3 to B0 (channel 1)
determine the holding time for each channel.
The timer value is calculated by the equation of [Decimal(B7,B6,B5,B4) * 15] or
[Decimal(B3,B2,B1,B0) * 15]. Refer to Table 8.
Table 8 Debounce Timer Setting
B7/B3
B6/B2
B5/B1
B4/B0
Timer (ms)
0
0
0
0
0
0
0
0
1
15
0
0
1
0
30
0
0
1
1
45
0
1
0
0
60
:
:
:
:
:
0
1
1
1
105
1
0
0
0
120
1
0
0
1
135
:
:
:
:
:
1
1
1
1
225
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CR5 (CH1 transmit/receive level control)
B7
B6
B5
B4
B3
B2
B1
B0
CR5
LV1R3
LV1R2
LV1R1
LV1R0
LV1X3
LV1X2
LV1X1
LV1X0
default
0
0
0
0
0
0
0
0
B7 to B4
... Level setting for CH1 on its receive side
The LV1R3 to LV1R0 bits determine the level for the CH1 receive side as shown in Table
9.
B3 to B0
... Level setting for CH1 on its transmit side
The LV1X3 to LV1X0 bits determine the level for the CH1 transmit side as shown in Table
9.
Table 9 Receive and Transmit Level Setting
LV1R3/LV1X3
LV1R2/ LV1X2
LV1R1/LV1X1
LV1R0/LV1X0
Level (dBm0)
0
0
0
0
0.0
0
0
0
1
1.0
0
0
1
0
2.0
0
0
1
1
3.0
0
1
0
0
4.0
0
1
0
1
5.0
0
1
1
0
6.0
0
1
1
1
7.0
1
0
0
0
8.0
1
0
0
1
9.0
1
0
1
0
10.0
1
0
1
1
11.0
1
1
0
0
12.0
1
1
0
1
13.0
1
1
1
0
14.0
1
1
1
1
OFF
FEDL7033-02
1Semiconductor
ML7033
32/51
CR6 (SLIC 1 control)
B7
B6
B5
B4
B3
B2
B1
B0
CR6
F2_1
F1_1
F0_1
SWC1
BSEL1
E0_1
DET1
ALM1
default
0
0
0
0
0
0
--
--
*
CR6-B1 and B0 are read-only bits. Though either of "0" or "1" will do for these registers when a byte-wide write action is
made, the written values are ignored.
*
The
INT pin which stays at logic "0" will be released to logic "1" when both of this control register (CR6) and SLIC 2
control register (CR13) are read.
B7 to B5
... Operation mode setting for SLIC1
The F2_1 to F0_1 bits determine the output level for the Fn_1 pins. For more details, refer
to Table 6. When each bit is cleared ("0"), the corresponding Fn_1 pin outputs a logic "0".
When each bit is set ("1"), the corresponding Fn_1 pin outputs a logic "1".
B4
... Uncommitted switch control for SLIC1
0 : switch on
1 : switch off
This bit determines the output level for the
SWC1 pin. When this bit is cleared, the SWC1
pin outputs a logic "0". When this bit is set, the pin outputs a logic "1".
When the SLIC connected to CH1 is the Intersil RSLIC
TM
series, the SLIC's internal
uncommitted switch, located between the SW+ pin and the SW- pin, can be controlled by
inputting the output from the SWC1 pin directly into the corresponding input pin of the
SLIC device.
B3
... Battery mode select for SLIC1
0 : low battery mode
1 : high battery mode
This bit determines the output level for the BSEL1 pin. When this bit is cleared, the BSEL1
pin outputs a logic "0". When this bit is set, the pin outputs a logic "1".
When the SLIC connected to CH1 is from the Intersil RSLIC
TM
series, the SLIC's battery
mode selection is possible by inputting the output from the BSEL1 pin directly into the
corresponding input pin of the SLIC device.
B2
... Detector mode selection for SLIC1
This bit determines the output level for the E0_1 pin. When this bit is cleared, the E0_1 pin
outputs a logic "0". When this bit is set, the pin outputs a logic "1".
When a SLIC connected to CH1 is Intersil RSLIC
TM
series, the SLIC's detector mode
selection is possible by connecting the E0_1 pin directly to the corresponding input pin of
the SLIC device. The event detected by the SLIC is determined by the combination of the
F2_1, the F1_1, the F0_1 and the E0_1 pins as shown in Table 6.
The output level of the E0_1 pin changes 20
s later (hold timer) in the power-on mode with
the
PDN pin = logic "1", and 200ns later in the power-down mode with the PDN pin =
logic "0" than a change of this bit value. Refer to Figure 6.
FEDL7033-02
1Semiconductor
ML7033
33/51
B1
... Event detection indicator for SLIC1 (Read-only bit)
0 : detected 1 : not detected
By reading the state of this bit, the input level to the
DET1 pin can be known. If this bit is
cleared it indicates that the
DET1 pin is in the logic "0" state. If this bit is set it indicates
that the
DET1 pin is in the logic "1" state.

When the SLIC connected to channel 1 is from the Intersil RSLIC
TM
series, the
DET1 pin
can be connected directly to the corresponding output pin of the SLIC device. This allows
an assigned event such as off-hook, ring trip, or ground key to be detected. The event
detected by the SLIC detects is determined by the F2_1, F1_1, F0_1 (CR6-B7 to B5), and
E0_1 (CR6-B2) bits.
When the debounce timer is enabled by setting the DET1TIM3 through DET1TIM0 bits
(CR4-B3 to B0), the DET1 (CR6-B1) bit is held unchanged for a set period, even when the
DET1 input pin changes from logic "1" to logic "0".
B0
... Thermal Shutdown Alarm indicator for SLIC1 (Read-only bit) 0 : detect
1 : not
detect
By reading this bit, the input level to the
ALM1 pin can be known. When this bit is cleared,
the
ALM1 pin is a logic "0". When this bit is set, the pin is a logic "1".
When the SLIC connected to channel 1 is from the Intersil RSLIC
TM
series, the ALM1 pin
can be connected directly to the corresponding output pin of the SLIC device. This allows
the user to know whether the SLIC1 is in the normal operating state, or in the thermal
shutdown state.
FEDL7033-02
1Semiconductor
ML7033
34/51
CR7 (CH1 Tone generator 2 control 1)
B7
B6
B5
B4
B3
B2
B1
B0
CR7
AOUT1 SEL
CH1TG 2
TX
CH1TG 2
TOUT1
CH1TG2
LV3
CH1TG2
LV2
CH1TG2
LV1
CH1TG2
LV0
CH1TG2 _8
default
0
0
0
0
0
0
0
0
CR8 (CH1 Tone generator 2 control 2)
B7
B6
B5
B4
B3
B2
B1
B0
CR8
CH1TG2 _7 CH1TG2 _6 CH1TG2 _5 CH1TG2 _4 CH1TG2 _3 CH1TG2 _2 CH1TG2 _1 CH1TG2 _0
CR7-B7
... AOUT1P, AOUT1N output select
0 : Single-ended output with the AOUT1P pin with the AOUT1N pin at high impedance
1 : Differential output with the AOUT1P and the AOUT1N pins
B6
... CH1 tone generator output select
0 : to Rx side
1 : to Tx side
B5
... CH1 tone generator Rx side output pin select
0 : AOUT1 pin
1 : TOUT1 pin
B4 to B1
... CH1 Tone Generator 2 (TG2) output level setting
This 4-bit field defines the output level for TG2 on CH1 as shown in Table 10.
Table 10 TG2 Level Setting
B4
(TG2LV3)
B3
(TG2LV2)
B2
(TG2LV1)
B1
(TG2LV0)
Level
(dBm0)
0
0
0
0
OFF
0
0
0
1
12.0
0
0
1
0
11.0
0
0
1
1
10.0
0
1
0
0
9.0
0
1
0
1
8.0
0
1
1
0
7.0
0
1
1
1
6.0
1
0
0
0
5.0
1
0
0
1
4.0
1
0
1
0
3.0
1
0
1
1
2.0
1
1
0
0
1.0
1
1
0
1
0.0
1
1
1
0
+1.0
1
1
1
1
+2.0
FEDL7033-02
1Semiconductor
ML7033
35/51
CR7-B0, CR8-B7 to B0 ... CH1 Tone Generator 2 (TG2) Frequency Select
These bits define the output frequency from TG2 on CH1. The frequency is between 300
and 3400Hz at 10Hz intervals. The values written to these bits determine the frequency as
shown in the following equation. Refer to Table 11.
Binary data for CR7-B0, CR8-B7 to B0
= (Output Frequency [Hz])/10
Below is an example of how these bits are programmed when the intended frequency is
1500Hz;
Ex) (Output Frequency [Hz])/10 = 1500/10 = 150d = 10010110b
Bits to set in CR7-B0, CR8-B7 to B0 = (0,1,0,0,1,0,1,1,0)
Note that the operations are not guaranteed when these bits define a frequency out of a band
between 300 and 3400 Hz.
Table 11 Tone Generator Frequency Setting
CR7
CR8
Frequency
(Hz)
decimal
hex
B0
B7
B6
B5
B4
B3
B2
B1
B0
300
30
01Eh
0
0
0
0
1
1
1
1
0
310
31
01Fh
0
0
0
0
1
1
1
1
1
320
32
020h
0
0
0
1
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
400
40
028h
0
0
0
1
0
1
0
0
0
410
41
029h
0
0
0
1
0
1
0
0
1
:
:
:
:
:
:
:
:
:
:
:
:
1000
100
064h
0
0
1
1
0
0
1
0
0
1010
101
065h
0
0
1
1
0
0
1
0
1
:
:
:
:
:
:
:
:
:
:
:
:
2000
200
0C8h
0
1
1
0
0
1
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
3000
300
12Ch
1
0
0
1
0
1
1
0
0
:
:
:
:
:
:
:
:
:
:
:
:
3390
339
153h
1
0
1
0
1
0
0
1
1
3400
340
154h
1
0
1
0
1
0
1
0
0
FEDL7033-02
1Semiconductor
ML7033
36/51
CR9 (CH1 tone generator 1 control1)
B7
B6
B5
B4
B3
B2
B1
B0
CR9
CH1TG1
LV6
CH1TG1
LV5
CH1TG1
LV4
CH1TG1
LV3
CH1TG1
LV2
CH1TG1
LV1
CH1TG1
LV0
CH1TG1 _8
default
0
0
0
0
0
0
0
0
CR10 (CH1 tone generator 1 control2)
B7
B6
B5
B4
B3
B2
B1
B0
CR10
CH1TG1 _7 CH1TG1 _6 CH1TG1 _5 CH1TG1 _4 CH1TG1 _3 CH1TG1 _2 CH1TG1 _1 CH1TG1 _0
default
0
0
0
0
0
0
0
0
CR9-B7 to B1
... CH1 Tone Generator 1 (TG1) Output Level Setting
This 7-bit field defines the output level of TG1 on CH1. The output level can be turned
OFF or ON. When turned on, the level is between 12.1 dBm0 and +0.5 dBm0 at 0.1 dBm0
intervals as shown in Table 12.
The value written to this field is calculated based on the desired output level as shown in
the following equation.
Binary data for CR9- B7 to B1
= [(Output Level [dBm0]) + 12.2]*10
The following is an example of how to program this field when the intended output level is
5.8 dBm0;
Ex) [(Output Level [dBm0]) + 12.2]*10 = (-5.8 + 12.2)*10 = 64d = 1000000b
Bits to set in CR9-B7 to B1 = (1,0,0,0,0,0,0)
Table 12 Tone Generator 1 Level Setting
B7
TG1LV6
B6
TG1LV5
B5
TG1LV4
B4
TG1LV3
B3
TG1LV2
B2
TG1LV1
B1
TG1LV0
Level
(dBm0)
0
0
0
0
0
0
0
OFF
0
0
0
0
0
0
1
12.1
0
0
0
0
0
1
0
12.0
0
0
0
0
0
1
1
11.9
0
0
0
0
1
0
0
11.8
:
:
:
:
:
:
:
:
0
1
1
1
1
1
1
5.9
1
0
0
0
0
0
0
5.8
1
0
0
0
0
0
1
5.7
:
:
:
:
:
:
:
:
1
1
1
1
0
1
0
0.0
1
1
1
1
0
1
1
0.1
1
1
1
1
1
0
0
0.2
1
1
1
1
1
0
1
0.3
1
1
1
1
1
1
0
0.4
1
1
1
1
1
1
1
0.5
(= 1.25 V
op
)
FEDL7033-02
1Semiconductor
ML7033
37/51
CR9-B0, CR10-B7 to B0 ...CH1 Tone Generator 1 Output Frequency Select
When the CH1RING (CR11-B3) bit is cleared ("0"), these 9 bits determine the output
frequency of tone generator 1 on channel 1 to a value between 300 and 3400 Hz at 10Hz
intervals. A sample list of frequencies is shown in Table 13. The value programmed into
this field is calculated based on the desired frequency using the following equation.
Binary data for CR9-B0, CR10-B7 to B0
= (Output Frequency [Hz])/10
The following is an example of how to program this field when the intended frequency is
1500 Hz;
Ex) (Output Frequency [Hz])/10 = 1500/10 = 150d = 10010110b
Bits to set in CR9-B0, CR10-B7 to B0 = (0,1,0,0,1,0,1,1,0)
Note that the operations are not guaranteed when these bits define a frequency out of a band
between 300 and 3400 Hz.
Table 13 Tone Generator Frequency Setting (CH1RING bit = "0")
CR9
CR10
Frequency
(Hz)
decimal
hex
B0
B7
B6
B5
B4
B3
B2
B1
B0
300
30
01Eh
0
0
0
0
1
1
1
1
0
310
31
01Fh
0
0
0
0
1
1
1
1
1
320
32
020h
0
0
0
1
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
400
40
028h
0
0
0
1
0
1
0
0
0
410
41
029h
0
0
0
1
0
1
0
0
1
:
:
:
:
:
:
:
:
:
:
:
:
1000
100
064h
0
0
1
1
0
0
1
0
0
1010
101
065h
0
0
1
1
0
0
1
0
1
:
:
:
:
:
:
:
:
:
:
:
:
2000
200
0C8h
0
1
1
0
0
1
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
3000
300
12Ch
1
0
0
1
0
1
1
0
0
:
:
:
:
:
:
:
:
:
:
:
:
3390
339
153h
1
0
1
0
1
0
0
1
1
3400
340
154h
1
0
1
0
1
0
1
0
0
FEDL7033-02
1Semiconductor
ML7033
38/51
When the CH1RING (CR11-B3) bit is set ("1"), the CH1TG1_8 (CR9-B0) bit and the
CH1TG1_7 to CH1TG1_6 (CR10-B7 to B6) bits are ignored and the CH1TG1_5 to
CH1TG1_0 (CR10-B5 to B0) bits are used to define the ringing tone frequency.
When the CH1RING (CR11-B3) bit is set, the frequency can be set to a value between 15
Hz and 50 Hz at 1 Hz intervals. The value programmed into this field is calculated based on
the desired frequency using the following equation. A partial list of frequencies is shown in
Table 14.
Binary data for CR10-B5 to B0
= (Output Frequency [Hz])
The following is an example of how to program this field when the intended frequency is
20Hz;
Ex) Output Frequency [Hz] = 20d = 010100b
Bits to set in CR10-B5 to B0 = (0,1,0,1,0,0)
Note that the operations are not guaranteed when these bits define a frequency out of a band
between 15 and 50Hz.
Table 14 Tone Generator Frequency Setting (CH1RING bit = "1")
CR9
CR10
Frequency
(Hz)
decimal
hex
B0
B7
B6
B5
B4
B3
B2
B1
B0
15
15
0Fh
--
--
--
0
0
1
1
1
1
16
16
10h
--
--
--
0
1
0
0
0
0
17
17
11h
--
--
--
0
1
0
0
0
1
18
18
12h
--
--
--
0
1
0
0
1
0
19
19
13h
--
--
--
0
1
0
0
1
1
20
20
14h
--
--
--
0
1
0
1
0
0
:
:
:
:
:
:
:
:
:
:
:
:
48
48
30h
--
--
--
1
1
0
0
0
0
49
49
31h
--
--
--
1
1
0
0
0
1
50
50
32h
--
--
--
1
1
0
0
1
0
FEDL7033-02
1Semiconductor
ML7033
39/51
CR11 (Ringing_ON and Trapezoid crest factors control)
B7
B6
B5
B4
B3
B2
B1
B0
CR11
CH2
RING
CH2TG1
TRP2
CH2TG1
TRP1
CH2TG1
TRP0
CH1
RING
CH1TG1
TRP2
CH1TG1
TRP1
CH1TG1
TRP0
default
0
0
0
0
0
0
0
0
B7
... CH2 Tone Generator 1 (TG1) function select
0 : CH2TG1 works as a non-ringing tone generator (300 to 3400 Hz)
1 : CH2TG1 works as a ringing tone generator (15 to 50 Hz)
The frequency and level of CH2TG1 are set by CR16 to CR17.
B6 to B4
... CH2 ringing tone waveform setting
This 3-bit field determines the type of ringing tone waveform for TG1 on CH2. A
sinusoidal waveform, or a trapezoidal waveform with a crest factor between 1.225 V and
1.375 V at 0.025 V intervals, can be selected as shown in Table 15. For a definition of
`crest factor', refer to Figure 13. These bits are valid when the CH2RING (CR11-B7) bit is
set.
B3
... CH1 TG1 function select
0 : CH1TG1 works as a non-ringing tone generator (300 to 3400 Hz)
1 : CH1TG1 works as a ringing tone generator (15 to 50 Hz)
The frequency and level of CH1TG1 are set by CR9 to CR10.
B2 to B0
... CH1 ringing tone waveform setting
This 3-bit field determines the type of ringing tone waveform for TG1 on CH1. A
sinusoidal waveform, or a trapezoidal waveform with a crest factor between 1.225 V and
1.375 V at 0.025 V intervals, can be selected as shown in Table 15. For a definition of
`crest factor', refer to Figure 13. These bits are valid when the CH1RING (CR11-B3) bit is
set.
Figure 13 Ringing Tone Waveform
Table 15 Crest Factor Setting
B6/B2
TG1 TRP2
B5/B1
TG1 TRP1
B4/B0
TG1 TRP0
Crest Factor
0
0
0
OFF
0
0
1
1.225
0
1
0
1.250
0
1
1
1.275
1
0
0
1.300
1
0
1
1.325
1
1
0
1.350
1
1
1
1.375
a
1
a
Vp
3
/
4
1
/
1
a
r
CrestFacto
-
=
FEDL7033-02
1Semiconductor
ML7033
40/51
CR12 (CH2 transmit/receive level control)
B7
B6
B5
B4
B3
B2
B1
B0
CR12
LV2R3
LV2R2
LV2R1
LV2R0
LV2X3
LV2X2
LV2X1
LV2X0
default
0
0
0
0
0
0
0
0
B7 to B4
... Level setting for CH2 on its receive side
This 4-bit field determines the level setting for the CH2 receive side. The settings range
from 0 to 14 dBm0 as shown in Table 16.
B3 to B0
... Level setting for CH2 on its transmit side
This 4-bit field determines the level setting for the CH2 transmit side. The settings range
from 0 to 14 dBm0 as shown in Table 16.
Table 16 Receive and Transmit Level Setting
LV2R3/ LV2X3
LV2R2/ LV2X2
LV2R1/ LV2X1
LV2R0/ LV2X0
Level (dBm0)
0
0
0
0
0.0
0
0
0
1
1.0
0
0
1
0
2.0
0
0
1
1
3.0
0
1
0
0
4.0
0
1
0
1
5.0
0
1
1
0
6.0
0
1
1
1
7.0
1
0
0
0
8.0
1
0
0
1
9.0
1
0
1
0
10.0
1
0
1
1
11.0
1
1
0
0
12.0
1
1
0
1
13.0
1
1
1
0
14.0
1
1
1
1
OFF
FEDL7033-02
1Semiconductor
ML7033
41/51
CR13 (SLIC 2 control)
B7
B6
B5
B4
B3
B2
B1
B0
CR13
F2_2
F1_2
F0_2
SWC2
BSEL2
E0_2
DET2
ALM2
default
0
0
0
0
0
0
-
-
*
CR13-B1 and B0 are read-only bits. Though either of "0" or "1" will do for these registers when a byte-wide write action is
made, the written values are ignored.
*
The
INT pin which stays at logic "0" will be released to logic "1" when both of this control register (CR13) and SLIC 1
control register (CR6) are read.
B7 to B5
... Operation mode setting for SLIC2
This 3-bit field determines the output level of the Fn_2 pins. For more detail, refer to Table
6. When any of these bits are cleared, the corresponding Fn_2 pin outputs a logic "0".
When any of these bits are set, the corresponding Fn_2 pin outputs a logic "1".
B4
... Uncommitted switch control for SLIC2
0 : switch on
1 : switch off
This bit determines the output level of the
SWC2 pin. When this bit is cleared, the SWC2
pin outputs a logic "0". When this bit is set, the
SWC2 pin outputs a logic "1".
When the SLIC connected to channel 2 is an Intersil RSLIC
TM
series device, the internal
uncommitted switch of the SLIC, located between the SW+ and the SW- pins, can be
controlled by connecting the
SWC2 pin directly to the corresponding input pin of the SLIC
device.
B3
... Battery mode select for SLIC2
0 : low battery mode
1 : high battery mode
This bit determines the output level for the BSEL2 pin. When this bit is cleared, the BSEL2
pin outputs a logic "0". When this bit is set, the BSEL2 pin outputs a logic "1".
When the SLIC connected to CH2 is an Intersil RSLIC
TM
series device, the battery mode
selection of the SLIC is possible by connecting the BSEL2 pin directly to the corresponding
input pin of the SLIC device.
B2
... Detector mode selection for SLIC2
This bit determines the output level of the E0_2 pin. When this bit is cleared, the E0_2 pin
outputs a logic "0". When this bit is set, the E0_2 pin outputs a logic "1".
When the SLIC connected to channel 2 is an Intersil RSLIC
TM
series device, the detector
mode selection of the SLIC is possible by connecting the E0_2 pin directly to the
corresponding input pin of the SLIC device. The event detected by the SLIC is determined
by the F2_2, F1_2, F0_2 and E0_2 output pins as shown in Table 6.
The output level from the E0_2 pin changes 20
s later (hold timer) in the power-on mode
with the
PDN pin = logic "1", and 200 ns later in the power-down mode with the PDN pin
= logic "0" than a change of this bit value. Refer to Figure 6 for more information.
FEDL7033-02
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ML7033
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B1
... Event detection indicator for SLIC2 (Read-only bit)
0 : detected 1 : not detected
By reading the state of this bit, the input level to the
DET2 pin can be determined.
If this bit is cleared, the
DET2 pin is a logic "0". If this bit is set, the DET2 pin is a logic
"1".
When the SLIC connected to channel 2 is an Intersil RSLIC
TM
series device, an assigned
event of off-hook, ring trip or ground key can be detected by connecting the
DET2 pin of
the ML7033 directly to the corresponding output pin of the SLIC device.
The event detected by the the SLIC is determined by the F2_2, F1_2, F0_2 (CR13-B7 to
B5), and E0_2 (CR13-B2) bits.
When a debounce timer is enabled by a setting with the DET2TIM3 through DET2TIM0
bits (CR4-B7 to B4), the DET2 (CR13-B1) bit is held unchanged for a set period, even
when the DET2 pin changes from a logic "1" to a logic "0".
B0
... Thermal Shutdown Alarm indicator for SLIC2 (Read-only bit) 0 : detect
1 : not
detect
By reading the state of this bit, the input level to the ALM2 pin can be determined.
If this bit is cleared, the
ALM2 pin is a logic "0". If this bit is set, the ALM2 pin is a logic
"1".
When the SLIC connected to channel 2 is an Intersil RSLIC
TM
series device, connecting the
ALM2 pin directly to the corresponding output pin of the SLIC device allows the ML7033
to know whether the SLIC is in the normal operating mode, or in a thermal shutdown state.
FEDL7033-02
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ML7033
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CR14 (CH2 tone generator 2 control1)
B7
B6
B5
B4
B3
B2
B1
B0
CR14
AOUT2 SEL CH2TG2 TX
CH2TG2
TOUT2
CH2TG2
LV3
CH2TG2
LV2
CH2TG2
LV1
CH2TG2
LV0
CH2TG2 _8
default
0
0
0
0
0
0
0
0
CR15 (CH2 tone generator 2 control2)
B7
B6
B5
B4
B3
B2
B1
B0
CR15
CH2TG2 _7 CH2TG2 _6 CH2TG2 _5 CH2TG2 _4 CH2TG2 _3 CH2TG2 _2 CH2TG2 _1 CH2TG2 _0
default
0
0
0
0
0
0
0
0
CR14-B7
... AOUT2P, AOUT2N output select
0 : Single-ended output with the AOUT2P pin with the AOUT2N pin at high impedance.
1 : Differential output with the AOUT2P and the AOUT2N pins.
B6
... CH2 tone generator output select
0 : to Rx side
1 : to Tx side
B5
... CH2 tone generator Rx side output pin select
0 : AOUT2 pin
1 : TOUT2 pin
B4 to B1
... CH2 TG2 output level setting
This 4-bit field determines the output level of TG2 on CH2. The output level ranges from
12 to +2 dBmO as shown in Table 17.
Table 17 Tone Generator 2 Level Setting
B4
TG2LV3
B3
TG2LV2
B2
TG2LV1
B1
TG2LV0
Level
(dBm0)
0
0
0
0
OFF
0
0
0
1
12.0
0
0
1
0
11.0
0
0
1
1
10.0
0
1
0
0
9.0
0
1
0
1
8.0
0
1
1
0
7.0
0
1
1
1
6.0
1
0
0
0
5.0
1
0
0
1
4.0
1
0
1
0
3.0
1
0
1
1
2.0
1
1
0
0
1.0
1
1
0
1
0.0
1
1
1
0
+1.0
1
1
1
1
+2.0
FEDL7033-02
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CR14-B0, CR15-B7 to B0... CH2 TG2 frequency select
These 9 bits define the output frequency for TG2 on CH2. The frequency range is between
300 and 3400 Hz in 10 Hz intervals as shown in Table 18.
The output frequency is calculated using the following formula:
Binary data for CR14-B0, CR15-B7 to B0
= (Output Frequency [Hz])/10
The following example shows how to program the output frequency when the intended
frequency is 1500 Hz;
Ex) (Output Frequency [Hz]) / 10 = 1500/10 = 150d = 10010110b
Bits to set in CR14-B0, CR15-B7 to B0 = (0,1,0,0,1,0,1,1,0)
Note that the operations are not guaranteed when these bits define a frequency out of a band
between 300 and 3400 Hz.
Table 18 Tone Generator Frequency Setting
CR14
CR15
Frequency
(Hz)
decimal
hex
B0
B7
B6
B5
B4
B3
B2
B1
B0
300
30
01Eh
0
0
0
0
1
1
1
1
0
310
31
01Fh
0
0
0
0
1
1
1
1
1
320
32
020h
0
0
0
1
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
400
40
028h
0
0
0
1
0
1
0
0
0
410
41
029h
0
0
0
1
0
1
0
0
1
:
:
:
:
:
:
:
:
:
:
:
:
1000
100
064h
0
0
1
1
0
0
1
0
0
1010
101
065h
0
0
1
1
0
0
1
0
1
:
:
:
:
:
:
:
:
:
:
:
:
2000
200
0C8h
0
1
1
0
0
1
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
3000
300
12Ch
1
0
0
1
0
1
1
0
0
:
:
:
:
:
:
:
:
:
:
:
:
3390
339
153h
1
0
1
0
1
0
0
1
1
3400
340
154h
1
0
1
0
1
0
1
0
0
FEDL7033-02
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CR16 (CH2 tone generator 1 control1)
B7
B6
B5
B4
B3
B2
B1
B0
CR16
CH2TG1
LV6
CH2TG1
LV5
CH2TG1
LV4
CH2TG1
LV3
CH2TG1
LV2
CH2TG1
LV1
CH2TG1
LV0
CH2TG1 _8
default
0
0
0
0
0
0
0
0
CR17 (CH2 tone generator 1 control2)
B7
B6
B5
B4
B3
B2
B1
B0
CR17
CH2TG1 _7 CH2TG1 _6 CH2TG1 _5 CH2TG1 _4 CH2TG1 _3 CH2TG1 _2 CH2TG1 _1 CH2TG1 _0
default
0
0
0
0
0
0
0
0
CR16-B7 to B1 ... CH2 TG1 output level setting
This 7-bit field defines the output level of tone generator 1 on channel 2. The output level
ranges from 12.1 to +0.5 dBm0 in 0.1 dBm0 intervals as shown in Table 19. A value of 0
in this field disables the tone generator.
The output level is calculated using the following formula.
Binary data for CR16- B7 to B1
= [(Output Level [dBm0]) + 12.2]*10
The following example shows how to program this field when the intended output level is
5.8 dBm0;
Ex) [(Output Level [dBm0]) + 12.2]*10 = (5.8 + 12.2)*10 = 64d = 1000000b
Bits to set in CR9-B7 to B1 = (1,0,0,0,0,0,0)
Table 19 Tone Generator 1 Level Setting
B7
TG1LV6
B6
TG1LV5
B5
TG1LV4
B4
TG1LV3
B3
TG1LV2
B2
TG1LV1
B1
TG1LV0
Level
(dBm0)
0
0
0
0
0
0
0
OFF
0
0
0
0
0
0
1
12.1
0
0
0
0
0
1
0
12.0
0
0
0
0
0
1
1
11.9
0
0
0
0
1
0
0
11.8
:
:
:
:
:
:
:
:
0
1
1
1
1
1
1
5.9
1
0
0
0
0
0
0
5.8
1
0
0
0
0
0
1
5.7
:
:
:
:
:
:
:
:
1
1
1
1
0
1
0
0.0
1
1
1
1
0
1
1
0.1
1
1
1
1
1
0
0
0.2
1
1
1
1
1
0
1
0.3
1
1
1
1
1
1
0
0.4
1
1
1
1
1
1
1
0.5
(= 1.25 V
op
)
FEDL7033-02
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ML7033
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CR16-B0, CR17-B7 to B0 ... CH2 TG1 frequency select
When the CH2RING (CR11-B7) bit is cleared, this 9-bit field is valid and determines the
output frequency from tone generator 1 on channel 2. The frequency range is between 300
and 3400 Hz at 10 Hz intervals as shown in Table 20.
The output level is calculated using the following formula.
Binary data for CR16-B0, CR17-B7 to B0
= (Output Frequency [Hz])/10
The following is an example of how to program this register field when the intended
frequency is 1500 Hz;
Ex) (Output Frequency [Hz]) / 10 = 1500/10 = 150d = 10010110b
Bits to set in CR16-B0, CR17-B7 to B0 = (0,1,0,0,1,0,1,1,0)
Note that the operations are not guaranteed when these bits define a frequency out of a band
between 300 and 3400 Hz.
Table 20 Tone Generator Frequency Setting (CH2RING bit = "0")
CR16
CR17
Frequency
(Hz)
decimal
hex
B0
B7
B6
B5
B4
B3
B2
B1
B0
300
30
01Eh
0
0
0
0
1
1
1
1
0
310
31
01Fh
0
0
0
0
1
1
1
1
1
320
32
020h
0
0
0
1
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
400
40
028h
0
0
0
1
0
1
0
0
0
410
41
029h
0
0
0
1
0
1
0
0
1
:
:
:
:
:
:
:
:
:
:
:
:
1000
100
064h
0
0
1
1
0
0
1
0
0
1010
101
065h
0
0
1
1
0
0
1
0
1
:
:
:
:
:
:
:
:
:
:
:
:
2000
200
0C8h
0
1
1
0
0
1
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
3000
300
12Ch
1
0
0
1
0
1
1
0
0
:
:
:
:
:
:
:
:
:
:
:
:
3390
339
153h
1
0
1
0
1
0
0
1
1
3400
340
154h
1
0
1
0
1
0
1
0
0
When the CH2RING (CR11-B7) bit is set, the setting of the CH2TG1_8 (CR16-B0) bit and
the CH2TG1_7 to CH2TG1_6 (CR16-B7 to B6) bits are ignored, and the CH2TG1_5 to
CH2TG1_0 (CR16-B5 to B0) field defines the ringing tone frequency.
When the CH2RING (CR11-B7) bit is set, the frequency range is between 15 and 50 at 1
Hz intervals as shown in Table 21.
The output frequency is calculated using the following formula.
Binary data for CR17-B5 to B0
= (Output Frequency [Hz])
FEDL7033-02
1Semiconductor
ML7033
47/51
The following example shows how to program this register field when the intended
frequency is 20 Hz;
Ex) Output Frequency [Hz] = 20d = 010100b
Bits to set in CR17-B5 to B0 = (0,1,0,1,0,0)
Note that the operations are not guaranteed when these bits define a frequency out of a band
between 15 and 50 Hz.
Table 21 Tone Generator Frequency Setting (CH2RING bit = "1")
CR16
CR17
Frequency
(Hz)
decimal
hex
B0
B7
B6
B5
B4
B3
B2
B1
B0
15
15
0Fh
--
--
--
0
0
1
1
1
1
16
16
10h
--
--
--
0
1
0
0
0
0
17
17
11h
--
--
--
0
1
0
0
0
1
18
18
12h
--
--
--
0
1
0
0
1
0
19
19
13h
--
--
--
0
1
0
0
1
1
20
20
14h
--
--
--
0
1
0
1
0
0
:
:
:
:
:
:
:
:
:
:
:
:
48
48
30h
--
--
--
1
1
0
0
0
0
49
49
31h
--
--
--
1
1
0
0
0
1
50
50
32h
--
--
--
1
1
0
0
1
0
FEDL7033-02
1Semiconductor
ML7033
48/51
CR18 (Test control)
B7
B6
B5
B4
B3
B2
B1
B0
CR18
CH2
LOOP1
CH2
LOOP0
CH1
LOOP1
CH1
LOOP0
TEST3
TEST2
TEST1
TEST0
default
0
0
0
0
0
0
0
0
B7, B6
... CH2 loop-back test mode select
(B7, B6):
(0, 0) = Loop-back OFF
(0, 1) = Loop-back OFF
(1, 0) = Channel 2 digital loop-back test. PCM data output on the PCMOUT pin during
normal operation is internally looped back through the Receive path via the
PCMIN pin. In digital loop-back test mode, input data on PCMIN pin is ignored,
but PCM data continues to be output on the PCMOUT pin.
(1, 1) = Channel 2 analog loop-back test. Analog signals output on the AOUT2P pin (or the
AOUT2P and AOUT2N pins) are internally looped back to the transmit path
behind a built-in feedback amplifier located after the AIN2P, AIN2N and GSX2
pins. In this mode, the AIN2P and AIN2N input pins are ignored. However, analog
signals continue to be output on the AOUT2P pin (or the AOUT2P and the
AOUT2N pins).
A loop-back test is functional only if XSYNC and RSYNC are from the same clock source.
B5, B4
... CH1 loop-back test mode select
(B5, B4):
(0, 0) = Loop-back OFF
(0, 1) = Loop-back OFF
(1, 0) = Channel 1 digital loop-back test. PCM data is output on the PCMOUT pin in
normal operation is internally looped back through the Receive path via the
PCMIN pin. In loop-back test mode, input data on PCMIN pin is ignored. However,
PCM data can be output on the PCMOUT pin.
(1, 1) = Channel 1 analog loop-back test. Analog signals output on the AOUT1P pin (or
from the AOUT1P and the AOUT1N pins) are internally looped back to the
transmit path via a built-in feedback amplifier located after the AIN1P, AIN1N and
GSX1 pins. In this mode, the AIN1P and AIN1N input pins are ignored. However,
analog signals can be output from the AOUT1P pin (or from the AOUT1P and the
AOUT1N pins).
A loop-back test is functional if XSYNC and RSYNC are from the same clock source.
B3 to B0
... LSI test registers for an LSI manufacturer
The default alternation is prohibited. When a write action is executed for CR18, set all of
these bits to "0".
FEDL7033-02
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CR19 (LSI manufacturer's test control)
B7
B6
B5
B4
B3
B2
B1
B0
CR19
TEST11
TEST10
TEST9
TEST8
TEST7
TEST6
TEST5
TEST4
default
0
0
0
0
0
0
0
0
B7 to B0
... LSI test registers for an LSI manufacturer
For manufacturing use only. Both reads and writes to this register are prohibited.
FEDL7033-02
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ML7033
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PACKAGE DIMENSIONS
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
QFP64-P-1414-0.80-BK
Mirror finish
Package material
Epoxy resin
Lead frame material
42 alloy
Pin treatment
Solder plating (
J5m)
Package weight (g)
0.87 TYP.
5
Rev. No./Last Revised
6/Feb. 23, 2001
(Unit: mm)
FEDL7033-02
1Semiconductor
ML7033
51/51
NOTICE
1.
The information contained herein can change without notice owing to product and/or technical
improvements. Before using the product, please make sure that the information being referred to is up-to-
date.
2.
The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product,
please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the
specified maximum ratings or operation outside the specified operating range.
5.
Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained
herein. No responsibility is assumed by us for any infringement of a third party's right which may result
from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires
special or enhanced quality and reliability characteristics nor in any system or application where the failure
of such system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices,
aerospace equipment, nuclear power control, medical equipment, and life-support systems.
7.
Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2001 Oki Electric Industry Co., Ltd.