FEDL671000-02

1Semiconductor

This version: Jul. 2001

Previous version: Jul. 2001

ML671000

OKI's CMOS 32-Bit Single-Chip Microcontroller with Built-in USB Device Controller

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GENERAL DESCRIPTION

The ML671000 is a high-performance CMOS 32-bit microcontroller combining a RISC based, 32-bit CPU core -
the ARM7TDMI

- with USB device controller, memory and peripherals.

The built-in USB device controller which is based on USB1.1 Full-speed (12 Mbps) makes interface with PCs or
other devices by USB. The ML671000, which provides the 32-bit data processing capability and built-in
peripheral functions performed by UART, serial ports, 16-bit timers, a DMA controller, and a memory controller,
is a single-chip microcontroller idealy suited to PC peripheral equipment and communication terminal control
applications.

FEATURES (1)

CPU

RISC 32-bit CPU

(ARM7TDMI)

Executable 32-bit instructions and 16-bit instructions
General registers:

32-bit

31 registers

Built-in multiplier
Little-endian format

Memory Spaces

Internal RAM :

4K bytes

External ROM, RAM, I/O :

26M bytes

External DRAM :

32M bytes

I/O Ports

I/O pins: 64 pins (I/O directions are specified at the bit level)

Timers

16-bit flexible timer

2ch

(auto-reload, compare-output, PWM, capture modes)
16-bit auto-reload timer

2ch

12-bit watchdog timer

Serial Ports

UART (16550A equivalent)

1ch, UART/synchronous serial

1ch

USB Device Controller

USB1.1 compliant, support full-speed (12 Mbps)
Transmission type: control, bulk, isochronous, interrupt
Remote wakeup function
Adaptable to USB bus powered devices
Four endpoint addresses
Endpoint FIFO size

EP0

64 bytes

2 (transmit/receive)

EP1

64 bytes

1 (transmit-receive)

EP2

64 bytes

2 (transmit-receive, 2 levels)

EP3

256 bytes

2 (transmit-receive, 2 levels)

DMA Controller

2ch

Single and Dual addressing modes
Cycle steal and Burst transfers
8- or 16-bit data transfers
Maximum transferring: 65536 times
Addressing area:

64M bytes

ARM7TDMI and the ARM POWERED logo are registered trademarks of ARM Ltd., UK.
The information contained herein can change without notice owing to the product being under development.

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FEATURES (2)

Interrupt Controller

Interrupt sources:

22 (13 internal , 9 external )

Interrupt priority:

8 levels

Memory Controller

Direct connection to ROM, SRAM, DRAM and I/O.
4-bank memory control

ROM, RAM, I/O

2 banks; DRAM

2 banks

Access wait control parameters for each bank.

Other

Arbitration of external bus request
Power saving functions

Standby modes:

HALT and STOP modes

Clock gears:

Selection of 1/2 OSC, 1/1 OSC, OSC

Onboard debugging is possible with JTAG interface.
Built-in PLL:

Power Supply Voltage

3.0 to 3.6 V

Operating Frequency

CPU: 6, 12, 24 MHz; USB: 48 MHz @12 MHz (Operating USBC)
CPU: 4 to 24 MHz (Non-Operating USBC)

Operating Temperature
Range

C to +70

Package

128-pin plastic QFP (QFP128-P-1420-0.50-K)

APPLICATIONS

Digital still camera, Printer, Terminal Adapter for PC peripherals and Communication terminals.

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BLOCK DIAGRAM

ARM7DTMI

RAM

Interrupt

Controller

Time Base

Generator

Flexible Timer/

Auto-reload Timer

UART Port

Serial Port

USB Device Controller

PLL

2-channel

DMAC

Internal Bus/External Memory Controller

I/O Port

[7:0]*

Asterisks indicate pins with secondary functions.

[7:0]*

[7:0]

XA[15:1]

XA0/nLB

nCS0

nRD

nWRE/nWRL

P0[7:0]/XA[23:16]

XD[15:0]

P1.7/nXWAIT

P1.6/nCS1

P1.5/nHB/nWRH

P1.4/nRAS1

P1.3/nWH/nCASH

P1.2/nRAS0

P1.1/nCAS/nCASL

P1.0/nWL/nWE

P6.7/nBACK

P6.6/nBREQ

nEFIQ

P2[7:0]/nEIR[7:0]

P3.7/TMCLK3

P3.6/TMCLK2

P3.5/TMCLK1

P3.4/TMCLK0

P3.3/TMIN1/TMOUT1

P3.2/TMIN0/TMOUT0

D +

P4.7/SOUT

P4.6/ SIN

P4.5/TXD0

P4.4/RXD0

P4.3/ TXC

P4.2/ RXC

P6.5/DACK1

P6.4/DACK0

P6.3/nDREQ1

P6.2/nDREQ0

nRST

nEA

DBSEL

TEST

OSC0

OSC1

CLKOUT

PLLEN

TCK

TMS

nTRST

TDI

TDO

P5.7/ DTR

P5.6/ RTS

P5.5/ CTS

P5.4/ DSR

P5.3/ DCD

P5.2/ RI

P5.1/OUT1

P5.0/OUT2

nR/W

OSCV

32-bit Core Address Bus

(two each)

pheral

ddress B

pheral

dress B

(16

ts)

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PIN CONFIGURATION (TOP VIEW)

103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

XD1 XD2 XD3 XD4 XD5 XD6 XD7 XD8 XD9

XD1

XD12

XD13

XD14

XD15

XA0

/
n

XA1

XA4

XA3

XA2

XA5

XA7 XA8 XA9

XA1

.
1

/
XA1

.
0

/
XA1

.
2

/
XA1

.
3

/
XA1

.
4

/
XA2

.
5

/
XA2

.
6

/
XA2

.
7

/
XA2

DBSEL

XD0

nCS0

nRD

nWRE/nWRL

P1.1/nCAS/nCASL

P1.2/nRAS0

P1.3/nWH/nCASH

P1.4/nRAS1

P1.5/nHB/nWRH

P1.6/nCS1

.0/nE

I
R0

.1/nE

I
R1

.2/nE

I
R2

.3/nE

I
R3

.4/nE

I
R4

.5/nE

I
R5

.6/nE

I
R6

.7/nE

I
R7

P7.7

nEFIQ

P7.6

P7.5

P7.4

P7.3

P7.2

P7.1

P7.0

nEA

D+

D-

nTRST

TDO

TDI

TMS

TCK

TEST

nRST

KOUT

OSCV

OSC0

OSC1

OSCV

P1.7/nXWAIT

P6.7/nBACK

P6.6/nBREQ

P6.5/DACK1

P6.4/DACK0

P6.3/nDREQ1

P6.2/nDREQ0

P6.0

.7/DT

.6/RT

.5/CT

.4/DS

.3/DCD

.2/RI

.1/OUT

.0/OUT

.7/S

OUT

.6/S

.5/T

.4/RX

.3/T

.2/RX

.
1

.
0

.7/T

.6/T

.5/T

.4/T

.3/T

I
N1/T

.2/T

I
N0/T

.
1

.
0

nR/W

P1.0/nWL/nWE

XA6

P6.1

102

101

100

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39

128-Pin Plastic QFP

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PIN DESCRIPTION (1)

Classification

Pin Name

I/O

Function

Description

XA15 to XA1

External address bus bits 15 to 1

Address Bus

nLB/XA0

Bank 0/1 lower byte select or external address bus bit 0

Data Bus

XD15 to XD0

I/O

External data bus

nCS0

Bank 0 chip select signal

nRD

Bank 0/1 read enable signal

nR/W

Read strobe signal

Bus Control

nWRE/nWRL

Bank 0/1 write enable or lower byte write enable signal

OSC0

Connection pin for crystal oscillator or ceramic resonator
If an external clock used, input the clock signal to this pin.

OSC1

Connection pin for crystal oscillator or ceramic resonator
If an external clock used, leave this pin open (unconnected).

CLKOUT

Internal system clock output

PLLEN

Enable pin for internal PLL. If PLL is to be used, connect this pin to V

OSCV

Power supply pin for internal oscillator circuit and PLL. Connect to V

Clock Control

OSCV

Power supply pin for internal oscillator circuit and PLL. Connect to
GND.

I/O

Primary

Bit 7 of port 0

P0.7/XA23

Secondary

Bit 23 of external address bus

I/O

Primary

Bit 6 of port 0

P0.6/XA22

Secondary

Bit 22 of external address bus

I/O

Primary

Bit 5 of port 0

P0.5/XA21

Secondary

Bit 21 of external address bus

I/O

Primary

Bit 4 of port 0

P0.4/XA20

Secondary

Bit 20 of external address bus

I/O

Primary

Bit 3 of port 0

P0.3/XA19

Secondary

Bit 19 of external address bus

I/O

Primary

Bit 2 of port 0

P0.2/XA18

Secondary

Bit 18 of external address bus

I/O

Primary

Bit 1 of port 0

P0.1/XA17

Secondary

Bit 17 of external address bus

I/O

Primary

Bit 0 of port 0

P0.0/XA16

Secondary

Bit 16 of external address bus

I/O

Primary

Bit 7 of port 1

P1.7/nXWAIT

Secondary

External wait cycle insert input

I/O

Primary

Bit 6 of port 1

P1.6/nCS1

Secondary

Bank 1 chip select signal

I/O

Primary

Bit 5 of port 1

P1.5/nHB/
nWRH

Secondary

Bank 0/1 upper byte select or upper byte write enable signal

I/O

Primary

Bit 4 of port 1

P1.4/nRAS1

Secondary

Bank 3 row address strobe signal

I/O

Primary

Bit 3 of port 1

P1.3/
nWH/nCASH

Secondary

Bank 2/3 upper byte column address strobe signal.

I/O

Primary

Bit 2 of port 1

P1.2/nRAS0

Secondary

Bank 2 row address strobe signal

I/O

Primary

Bit 1 of port 1

P1.1/
nCAS/nCASL

Secondary

Bank 2/3 column address strobe or lower byte column address strobe
signal

I/O

Primary

Bit 0 of port 1

I/O Ports

P1.0/
nWL/nWE

Secondary

Bank 2/3 lower byte write enable or write enable signal

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PIN DESCRIPTION (2)

Classification

Pin Name

I/O

Function

Description

I/O

Primary

Bit 7 of port 2

P2.7/nEIR7

Secondary

External interrupt request 7 input pin

I/O

Primary

Bit 6 of port 2

P2.6/nEIR6

Secondary

External interrupt request 6 input pin

I/O

Primary

Bit 5 of port 2

P2.5/nEIR5

Secondary

External interrupt request 5 input pin

I/O

Primary

Bit 4 of port 2

P2.4/nEIR4

Secondary

External interrupt request 4 input pin

I/O

Primary

Bit 3 of port 2

P2.3/nEIR3

Secondary

External interrupt request 3 input pin

I/O

Primary

Bit 2 of port 2

P2.2/nEIR2

Secondary

External interrupt request 2 input pin

I/O

Primary

Bit 1 of port 2

P2.1/nEIR1

Secondary

External interrupt request 1 input pin

I/O

Primary

Bit 0 of port 2

P2.0/nEIR0

Secondary

External interrupt request 0 input pin

I/O

Primary

Bit 7 of port 3

P3.7/TMCLK3

Secondary

External clock input pin for timer 3

I/O

Primary

Bit 6 of port 3

P3.6/TMCLK2

Secondary

External clock input pin for timer 2

I/O

Primary

Bit 5 of port 3

P3.5/TMCLK1

Secondary

External clock input pin for timer 1

I/O

Primary

Bit 4 of port 3

P3.4/TMCLK0

Secondary

External clock input pin for timer 0

I/O

Primary

Bit 3 of port 3

P3.3/
TMIN1/
TMOUT1

I/O

Secondary

If timer 1 is set to the compare-output or PWM modes, this pin is an
output.
If set to the capture mode, this pin is an input.

I/O

Primary

Bit 2 of port 3

P3.2/
TMIN1/
TMOUT0

I/O

Secondary

If timer 0 is set to the compare-output or PWM modes, this pin is an
output.
If set to the capture mode, this pin is an input.

P3.1

I/O

Bit 1 of port 3

P3.0

I/O

Bit 0 of port 3

I/O

Primary

Bit 7 of port 4

P4.7/SOUT

Secondary

Serial data output pin for UART serial port

I/O

Primary

Bit 6 of port 4

P4.6/SIN

Secondary

Serial data input pin for UART serial port

I/O

Primary

Bit 5 of port 4

P4.5/TXD

Secondary

Transmit data output pin for UART/synchronous serial port

I/O

Primary

Bit 4 of port 4

P4.4/RXD

Secondary

Receive data input pin for UART/synchronous serial port

Primary

Bit 3 of port 4

P4.3/TXC

I/O

Secondary

Transmit clock I/O pin for UART/synchronous serial port

Primary

Bit 2 of port 4

P4.2/RXC

I/O

Secondary

Receive clock I/O pin for UART/synchronous serial port

P4.1

I/O

Bit 1 of port 4

I/O Ports

P4.0

I/O

Bit 0 of port 4

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PIN DESCRIPTION (3)

Classification

Pin Name

I/O

Function

Description

I/O Primary

Bit 7 of port 5

P5.7/DTR

Secondary

DTR signal output pin for UART serial port

I/O Primary

Bit 6 of port 5

P5.6/RTS

Secondary

RTS signal output pin for UART serial port

I/O Primary

Bit 5 of port 5

P5.5/CTS

Secondary

CTS signal input pin for UART serial port

I/O Primary

Bit 4 of port 5

P5.4/DSR

Secondary

DSR signal input pin for UART serial port

I/O Primary

Bit 3 of port 5

P5.3/DCD

Secondary

DCD signal input pin for UART serial port

I/O Primary

Bit 2 of port 5

P5.2/RI

Secondary

RI signal input pin for UART serial port

I/O Primary

Bit 1 of port 5

P5.1/OUT1

Secondary

OUT1 signal output pin for UART serial port

I/O Primary

Bit 0 of port 5

P5.0/OUT2

Secondary

OUT2 signal output pin for UART serial port

I/O Primary

Bit 7 of port 6

P6.7/nBACK

Secondary

Bus release request acknowledged signal output pin

I/O Primary

Bit 6 of port 6

P6.6/nBREQ

Secondary

Bus release request signal input pin

I/O Primary

Bit 5 of port 6

P6.5/DACK1

Secondary

Data transfer request 1 acknowledged signal output pin

I/O Primary

Bit 4 of port 6

P6.4/DACK0

Secondary

Data transfer request 0 acknowledged signal output pin

I/O Primary

Bit 3 of port 6

P6.3/nDREQ1

Secondary

Data transfer request 1 signal input pin

I/O Primary

Bit 2 of port 6

P6.2/nDREQ0

Secondary

Data transfer request 0 signal input pin

P6.1

I/O

Bit 1 of port 6

P6.0

I/O

Bit 0 of port 6

P7.7

I/O

Bit 7 of port 7

P7.6

I/O

Bit 6 of port 7

P7.5

I/O

Bit 5 of port 7

P7.4

I/O

Bit 4 of port 7

P7.3

I/O

Bit 3 of port 7

P7.2

I/O

Bit 2 of port 7

P7.1

I/O

Bit 1 of port 7

I/O Ports

P7.0

I/O

Bit 0 of port 7

I/O

USB Port

I/O

USB data I/O pins

TCK

Test clock input pin

TMS

Test mode select pin

TDI

Test data input pin

TDO

Test data output pin

Debug
Interface

nTRST

Boundary scan logic reset input pin

Interrupt

nEFIQ

External FIQ (high-speed interrupt) interrupt request signal input pin

nEA

Normally connected to ground

nRST

System reset signal input pin for this LSI device

DBSEL

During a system reset of this LSI device, this pin sets the bank 0 data
bus width. To set a 16-bit bus width, connect to V

. To set an 8-bit bus

width, connect to GND.

System
Control

TEST

This pin sets the test and debug modes for this LSI device. Normally
connected to GND.

Power supply pin. Connect all V

pins to the power supply.

Power Supply

Ground pin. Connect all V

pins to GND.

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OVERVIEW OF INTERNAL PERIPHERAL FUNCTIONS

I/O Ports

The 64 I/O ports are configured from the 8-bit ports P0 to P7. Each bit of each port can be specified as an input
or output. If specified as an input, the port becomes a high impedance input. In addition to their port function
(primary function), some ports are assigned secondary functions such as an external interface function or an
I/O pin for an internal peripheral.

Timers

The timers consist of a 2-channel 16-bit flexible timer and a 2-channel 16-bit general-purpose timer. A count
clock can be selected for each channel.
-

Flexible timer

Operating modes: auto-reload timer, compare-output, PWM, capture

General-purpose timer

Auto-reload timer

Synchronous timer operation

Timer channel can be started and stopped in union.

Count clock

A count clock can be selected for each timer as: 1/1, 1/2, 1/4, 1/8, 1/16, and 1/32 of the system clock,
or as an external clock.

Time Base Generator

The time base generator consists of the time base counter, which drives frequency dividers deriving the time
base signals for on-chip peripherals from the system clock signals, and a watchdog timer, which counts time
base clock cycles and produces a system reset signal when its internal counter overflows.

UART Serial Port

Functionally the same as the 16550A, the UART serial port is equipped with 16-byte FIFOs for both receive
and transmit, modem control signals, a dedicated baud rate generator, etc.
-

Full duplex operation

Independent controls for transmit, receive, line status and data set interrupt

Modem control signals: CTS, DSR, DCD, DTR, RTS and RI

Built-in dedicated baud rate generator

Data length:5, 6, 7, or 8 bits

Stop bit:

1, 1.5, or 2 bits

Parity:

odd, even, or none

Detection of receive errors: parity error, framing error, overrun error, or data error of break interrupt

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UART/Synchronous Serial Port

The UART/synchronous serial port is a serial port that operates in two communication modes, the UART
mode and synchronous mode. In the UART mode, characters units are synchronized according to the
controlled start bit and stop bit, and data is transferred. In the synchronous mode, the data transfer is
synchronized to the controlled shift clock.
-

Built-in dedicated baud rate generator

Data length:7 or 8 bits

Stop bit:

1 or 2 bits (UART mode only)

Parity:

even or odd parity (none in the synchronous mode)

Detection of receive errors: parity error, framing error, and overrun error
(only overrun error in the synchronous mode)

Full-duplex operation

Interrupt Controller

The interrupt controller manages interrupt requests from 9 external sources and 13 internal sources, and passes
them on to the CPU as interrupt request (IRQ) or fast interrupt request (FIQ) exception requests. An interrupt
level can be set for each interrupt and priority can be controlled.
-

Supports 9 external interrupt sources from nEFIQ and nEIR [7:0] pins and 13 internal interrupt sources
from internal peripherals such as the USB device controller and the timers.

To simplify the control of interrupt priority, 8 interrupt levels can be set for each interrupt source.

The interrupt controller assigns a unique interrupt number to each interrupt source to permit rapid
branching to the appropriate routine.

Direct Memory Access (DMA) Controller

The direct memory access (DMA) controller is used instead of the CPU to transfer data between internal
memory, internal peripherals, external memory and memory mapped external devices.
-

Built-in 2 channels

Supports 64MB address area

Transfer data size:

8 or 16 bits

Maximum transferring:

65536 times

Addressing modes:

single or dual address mode

Bus modes:

cycle-steal or burst mode

Supports transfer requests from nDREQ[0:1] pins, internal peripheral devices and software.

Generates transfer complete interrupt requests when transfer is completed.

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Universal Serial Bus (USB) Device Controller

The USB device controller consists of a protocol engine to control the USB communications protocol, DPLL,
status/control, FIFO control, a USB transceiver, etc. The USB device controller conforms to USB spec. 1.1
full-speed (12Mbps) .
-

Supports the 4 types of transfers that are specified by the USB standard.
(control transfer, bulk transfer, isochronous transfer, and interrupt transfer)

Remote wakeup function

Adaptable to USB bus powered devices

4 endpoint addresses

Endpoint FIFO contents and functions

Endpoint

FIFO contents

Transfer mode

64 bytes

1 (transmit)

EP0

64 bytes

1 (receive)

Control

EP1

64 bytes

1 (transmit-receive)

Bulk, interrupt

EP2

64 bytes

2 (transmit-receive)

Bulk, interrupt, isochronous

EP3

256 bytes

2 (transmit-receive)

Bulk, interrupt, isochronous

External Memory Controller

The external memory controller generates control signals for accessing external memory (ROM, RAM,
DRAM, etc.) and peripheral devices mapped in the external memory space, and arbitrates external bus
requests from external devices.
-

Manages memory by dividing the memory space into 4 banks

2 banks of ROM, SRAM, and I/O

2 banks of DRAM

Each bank has a 16MB address space.

Bus width (8 or 16 bits) and wait cycles can be specified for each bank.

ROM, SRAM and I/O can be connected directly.
Outputs a strobe signal for the ROM, SRAM and I/O.

DRAM can be connected directly.

Row and column addresses are output as multiplexed signals.

Random access mode or high-speed page mode

Supports CAS before RAS refresh and self-refresh.

Clock Control

The clock controller generates and controls the system clock based on the internal oscillator circuit and phase
locked loop (PLL). It also controls the transitions to and from standby modes (HALT and STOP modes) and
returns to normal operation of mode.
-

It offers a choice of divider ratio for adjusting operating clock frequency to match the load processing.
When using PLL:

f, f, f/2

Not using PLL:

f, f/2, f/4, f/8

f = input clock frequency

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ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Condition

Rated value

Unit

Supply voltage

0.3 to +4.6

Input voltage

0.3 to V

0.3

Output current

Power dissipation

GND = 0 V

Ta = 25

Storage temperature

STG

55 to

150

RECOMMENDED OPERATING CONDITIONS

(GND = 0 V)

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Supply voltage

3.0

3.3

3.6

Storage holding voltage

DDH

= 0 Hz

2.0

3.6

Operating frequency

= 3.0 to 3.6

MHz

Ambient temperature

Input Clock Conditions

Connecting a crystal oscillator

PLLEN Pin

Input frequency

Operating frequency (f

)

"H" Level

6 to 12 MHz

12 to 24 MHz

"L" Level

4 to 12 MHz

Using an external clock supply

PLLEN Pin

Input frequency

Operating frequency (f

)

"H" Level

6 to 12 MHz

12 to 24 MHz

"L" Level

4 to 48 MHz

4 to 24 MHz

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ELECTRICAL CHARACTERISTICS

DC Characteristics (1)

= 3.0 to 3.6 V, GND = 0 V, Ta=

10 to

Parameter

Symbol

Condition

Min.

Typ. (*1)

Max.

Unit

H-level input voltage 1

IH1

0.76

5.5

H-level input voltage 2, 3

IH2

0.76

+0.3

H-level input voltage 4

IH3

2.0

5.5

L-level input voltage 1, 2, 3

IL1

0.3

0.2

L-level input voltage 4

IL2

0.3

0.8

H-level output voltage

4 mA

100

2.2

0.2

--
--

L-level output voltage

= 4 mA

0.4

Input leakage current

= 0/V

1.0 (*2)

Output leakage current

= 0/V

1.0 (*2)

H-level input current 3

= V

Pull-down resistor

50k

200

L-level input current 2

= 0 V

Pull-up resistor

50k

200

Input pin capacitance

Output pin capacitance

I/O pin capacitance

(*3)

150

Current consumption
(in STOP mode)

DDS

(*4)

500

Current consumption
(in HALT mode)

DDH

Current consumption
(during operation)

= 24 MHz
No load

105

1. Applied to PIO7 to PIO0, nEFIQ, nEA, DBSEL, TEST, and PLLEN
2. Applied to nRST, TDI, TMS, and TCK
3. Applied to nTRST
4. Applied to XD0 to XD15

(*1): Typ. indicates values for the case where V

= 3.3 V and Ta = 25

(*2): 50

A when Ta is 50

C or above.

(*3): Ta =

10 to +50

(*4): Ta = +50 to +70ºC

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DC Characteristics (2)

USB Port (D+, D-)

= 3.0 to 3.6 V, GND = 0 V, Ta = 0 to

70ºC)

Parameter

Symbol

Condition

Min.

Typ. (*1)

Max.

Unit

Differential input sensitivity

VDI

{

)(D

)

}

0.2

Differential common mode
range

VCM

Including VDI

part

0.8

2.5

Single ended receiver threshold

VSE

0.8

2.0

H-level output voltage

15k

to GND

2.8

3.6

L-level output voltage

15k

to 3.6 V

0.3

Output leakage current

0 V<V

(*1): Typ. indicates values for the case where V

= 3.3 V and Ta = 25

AC Characteristics

Clock timing

= 3.0 to 3.6 V, GND = 0 V, Ta = 10 to

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Clock frequency

MHz

Clock cycle time

250

Clock H-level pulse width

Clock L-level pulse width

External clock input frequency

EXC

MHz

External clock input cycle time

EXC

250

External clock input H-level pulse
width

EXCH

External clock input L-level pulse
width

EXCL

= 3.0 to 3.6 V

Clock rise time

Clock fall time

External clock input rise time

EXR

External clock input fall time

EXF

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Control signal timing

= 3.0 to 3.6 V, GND = 0 V, Ta = 10 to

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

nRST pulse width (*1)

RSTW1

2 t

nRST pulse width (*2)

RSTW2

Oscillation

stabilization

time

nEFIQ pulse width

EFIQW

2 t

nEIR pulse width

EIRW

2 t

TMIN pulse width

TMINW

2 t

TMCLK pulse width

TMCLKW

2 t

TCX, RXC frequency

1/4 f

MHz

TXC, RXC H-level pulse width

SCLKH

2 t

TXC, RXC L-level pulse width

SCLKL

2 t

TXD delay time

TXD

= 50 pF

1 t

RXD setup time

RXS

0.5 t

RXD hold time

RXH

1.5 t

nDREQ0, nDREQ1 setup time

REQS

1.0

nDREQ0, nDREQ1 hold time

REQH

2.6

DACK0, DACK1 delay time

DACKD

= 50 pF

2.4

15.2

(1*): Not including when power is turned on and during STOP mode
(2*): When power is turned on and also during STOP mode

External bus timing

= 3.0 to 3.6 V, GND = 0 V, Ta = 10 to

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

XA[23:1], nLB/XA0 delay time

XAD

XD[15:0] output delay time

XDOD

XD[15:0] output hold time

XDOH

XD[15:0] input setup time

XDIS

XD[15:0] input hold time

XDIH

nXWAIT setup time

XWAITS

nXWAIT hold time

XWAITH

nHB delay time

HBD

nCS[1:0] delay time

CSD

nWRE, nWRH, nWRL delay time

WRD

nRD assert delay time

RDD

nR/W assert delay time

R/WD

nRAS[1:0] assert delay time

RASD

nCAS assert delay time

CASD

nWE, nWH, nWL assert delay
time

WED

nBREQ setup time

BREQS

nBREQ hold time

BREQH

nBACK delay time

BACKD

= 50 pF

High impedance delay time

XHD

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PACKAGE DIMENSIONS

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).

QFP128-P-1420-0.50-K

Mirror finish

Package material

Epoxy resin

Lead frame material

42 alloy

Pin treatment

Solder plating (

5µm)

Package weight (g)

1.19 TYP.

Rev. No./Last Revised

4/Nov. 28, 1996

(Unit: mm)

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NOTICE
1.

The information contained herein can change without notice owing to product and/or technical
improvements. Before using the product, please make sure that the information being referred to is up-to-
date.

The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.

When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.

Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.

Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party's right which may result from the use
thereof.

The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special
or enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.

Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.

No part of the contents contained herein may be reprinted or reproduced without our prior permission.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ML671000

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ML671000