D
ATA
S
HEET
10-Gbps GaAs Family
High-Speed Optical Communications System
April 1999
O K I G a A s P R O D U C T S
s
s
Oki Semiconductor
CONTENTS
10-GHz GaAs Family
.........................................................................................................................1
KGL4201
10-GHz 8:1 Multiplexer ............................................................................................................................. 3
KGL4202
10-GHz 1:8 Demultiplexer ........................................................................................................................ 7
GHDD4411
EX-OR Circuit.......................................................................................................................................... 11
GHDD4414
Decision Circuit with Phase Detector ...................................................................................................... 15
1
Oki Semiconductor
10-GHz GaAs Family
High-Speed Optical Communications Systems
INTRODUCTION
Oki's 10-GHz logic devices are manufactured using a 0.2-m, ion-implanted process, which is similar to
Oki's familiar 0.5-m telecommunications process. However, the 0.2-m process uses a phase-shifting
edge line (PEL) masking method for gate fabrication. Gold-based, three-level metal interconnections are
used for high density and shorter wiring paths. Layers 1 and 2 are signal lines. Layer 3, which is formed
by electroplating, is used for ground or power supply lines because of its lower resistance. An optional
buried "p" channel structure is adopted for reducing short channel effects.
The following table shows the digital GaAs logic processes of the 10-GHz GaAs family.
The key to operating reliably at 10 Gbps is logic circuitry that can easily manipulate data at over 13 Gbps.
The higher frequency overhead is required to meet the different clock skews encountered when design-
ing and routing 10-Gbps data management hardware.
The logic is either direct-coupled FET logic (DCFL) or source-coupled FET logic (SCFL). The low-drive
disadvantage of DCFL can be improved by using super-buffer FET logic (SBFL). The basic speed of SBFL
is slower than DCFL, but SBFL is faster with higher fanouts and longer metal runs. A designer selects the
best performing logic for each logic element application. SBFLs used for clock distribution, output buff-
ers, etc. Typical gate delays of 9 ps and power of 2 mW per gate are achieved. Register logic elements like
D-flip flops are assembled using memory cell flip flops (MCFF) as shown in
Figure 1
.The operation speed
of a MCFF, which is about twice that of a conventional 6 NOR-gate circuit, operates at very low power.
To simplify device interconnections, AC-coupled clock and data input lines are created using the circuit
shown in
Figure 2
.
FEATURES
GaAs Logic Processes
Basic FET Process
Basic Gate
Circuit
Photo Masking
Gate Length
(m)
fT (GHz)
Gate Delays
(ps)
Application
MESFET
DCFL or SBFL
I-line printing
0.5
30
25
< 2.4 Gbps standard cell
MESFET
DCFL or SBFL
PEL
< 0.2
60
9
>12-Gbps hand-routed logic
Pseudomorphic-inverted HEMT
DCFL or SBFL
PEL
0.2
> 60
7
> 20-Gbps low-density logic
Pseudomorphic BP--MESFET
Analog
Deep UV
0.2
> 60
Analog amplifier
10-Gbps operation: highest speed available
ECL level logic swings: easy interface to other
logic
Inputs internally terminated: reduces noise and
phase jitter
50-
I/Os: easy to interconnect hardware
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10-GHz GaAs Family
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2
Oki Semiconductor
Many 10-Gbps inputs are self-biased and 50-
terminated, for capacitance coupling. The outputs are DC-
coupled to drive 50-
ground terminated lines.
DATA SHEETS
This document contains data sheets for the KGL4201, KGL4202, GHDD4411, and GHDD4414 10-Gbps
GaAs High-Speed Optical Communication Systems.
Data sheets for other communication devices may be obtained from the Oki Semiconductor WEB site,
www.okisemi.com or from the local sales office.
Figure 1. Memory Cell Flip-Flops
Data
Data
Clock
Clock
Q
Q
Master
Slave
Master/Slave Flip-Flop
Data
Clock
Clock
Out
Flip-Flop
Figure 2. AC-Coupled, Self-Biased Logic Input
Data or Clock In
50
Reference
Dummy Gate
3
Oki Semiconductor
KGL4201
10-GHz 8:1 Multiplexer
GENERAL DESCRIPTION
Oki's KGL4201 is a 10-GHz 8:1 multiplexer designed to operate in 10-Gbps communication links. This
circuit synchronously merges eight 1.25-Gbps data streams, clocked at low frequency rates into a single
10-Gbps stream, clocked at the higher frequency. In the KGL4201 multiplexer, the 10-GHz master clock is
first divided by two, then by four. The lower frequency components are first multiplexed by four, then
the two groups are merged into a single data stream using the master 10-Gbps clock. Complementary
1/8 synchronous clock outputs are made available from the KGL4201 for use in synchronizing lower fre-
quency logic.
All signal interfaces are 50-
with direct DC coupling on the 1.25-Gbps data inputs and phase-locked
1.25-Gbps clock outputs. The 10-Gbps data output and 10-GHz clock input are AC-capacitively-coupled
for ease of interfacing at microwave speeds and reducing ground noise induced phase jitter. All package
clock and data pins are separated by either ground or supply voltage pins to control the I/O impedance,
maintain signal isolation and reduce phase noise.
The KGL4201 is shipped in a 40-pin ceramic flat-package with impedance-controlling ground plane and
flush mounting bottom heat sink.
FEATURES
AC-coupled 10 Gbps I/O: eliminates DC
coupled phase jitter
1/8 clock generated on chip: easy to
synchronize downstream logic
2 V, 2.4 W
Isolated I/O pins: minimize noise and
impedance variation
Packaged in 40-pin ceramic flat-package with
ground plane and heat sink.
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