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1998 National Semiconductor Corporation
www.national.com
November 1998
USBN9602 (Universal Serial Bus)
Full Speed Function Controller With DMA Support
1.0 General Description
The USBN9602 is an integrated USB Node controller com-
patible with the USB Specification Versions 1.0 and 1.1.
Integrated onto a single IC are the required USB trans-
ceiver with a 3.3V Regulator, Media Access Controller,
USB endpoint (EP) FIFOs, a versatile 8-bit parallel inter-
face, MICROWIRE/PLUSTM Interface and a clock genera-
tor. A total of seven FIFO buffers support the different USB
messages: one bidirectional FIFO for the mandatory con-
Block Diagram
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
MICROWIRE/PLUS
TM
and MICROWIRE
TM
are trademarks of National Semiconductor Corporation.
Physical Layer Interface (PHY)
Media Access Controller (MAC)
Transceiver
48 MHz
Oscillator
Clock
Generator
XIN
XOUT
CLKOUT
Microcontroller Interface
D+
D-
Upstream Port
INTR
V3.3
CS
RD
WR
A0/ALE
D[7:0]/AD[7:0]
E
P
2
E
n
d
p
o
i
n
t
0
E
P
1
E
P
6
E
P
5
RX
TX
Endpoint/Control FIFOs
VReg
AGND
RESET
Vcc
GND
MODE[1:0]
Status
Control
SIE
USB Event
Detect
Clock
Recovery
E
P
4
E
P
3
trol endpoint EP0 and six FIFOs for an additional six unidi-
rectional Endpoint Pipes to support USB interrupt, bulk and
isochronous data transfers. The 8-bit parallel interface sup-
ports multiplexed and non-multiplexed style CPU
address/data buses. A programmable interrupt output
scheme allows device configuration for different interrupt
signaling requirements.
2
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2.0 Features
s
Full-Speed USB Node Device
s
USB transceiver
s
3.3V signal voltage regulator
s
48 MHz oscillator circuit
s
Programmable clock generator
s
Serial Interface Engine consisting of Physical Layer In-
terface (PHY) and Media Access Controller (MAC), USB
Specification 1.0 compliant
s
Control/Status Register File
s
USB Function Controller with seven FIFO-based End-
points:
One bidirectional Control Endpoint 0 (8 bytes)
Three Transmit Endpoints (2*32 and 1*64 bytes)
Three Receive Endpoints (2*32 and 1*64 bytes)
s
8-bit parallel interface with two selectable modes:
non-multiplexed
multiplexed (Intel compatible)
s
DMA support for parallel interface
s
MICROWIRE/PLUSTM Interface
s
28-pin SO package
3
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Table of Contents
1.0
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.0
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3.0
Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1
Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2
Voltage Regulator (VReg) . . . . . . . . . . . . . . . . . . . 4
3.3
Serial Interface Engine (SIE) . . . . . . . . . . . . . . . . . 4
3.4
Endpoint/Control FIFOs . . . . . . . . . . . . . . . . . . . . . 4
3.5
Microcontroller Interface . . . . . . . . . . . . . . . . . . . . 5
4.0
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5.0
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6.0
Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.1
Non-Multiplexed Mode . . . . . . . . . . . . . . . . . . . . . . 9
6.2
Multiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.0
DMA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8.0
MICROWIRE/PLUS Interface . . . . . . . . . . . . . . . . . . . . 13
9.0
Device Functional States . . . . . . . . . . . . . . . . . . . . . . . 16
9.1
Suspend Operation . . . . . . . . . . . . . . . . . . . . . . . 16
9.2
Remote Resume . . . . . . . . . . . . . . . . . . . . . . . . . 16
9.3
USB Resume Operation . . . . . . . . . . . . . . . . . . . 16
9.4
Functional State Transitions . . . . . . . . . . . . . . . . 16
10.0
Endpoint Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.1
Transmit and Receive Endpoint FIFOs . . . . . . . . 18
10.2
Bidirectional Control Endpoint FIFO0 Operation . 19
10.3
Transmit Endpoint FIFO Operation (TXFIFO1,
TXFIFO2, TXFIFO3) . . . . . . . . . . . . . . . . . . . . . . 19
10.4
Receive Endpoint FIFO Operation (RXFIFO1,
RXFIFO2, RXFIFO3) . . . . . . . . . . . . . . . . . . . . . . 20
10.5
Programming Model . . . . . . . . . . . . . . . . . . . . . . 21
11.0
Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
11.1
Main Control Register (MCNTRL) . . . . . . . . . . . . 23
11.2
Clock Configuration Register (CCONF) . . . . . . . . 23
11.3
DMA Control Register (DMACNTRL) . . . . . . . . . 24
11.4
Revision Identifier Register (RID)Revision Identifier (RID)
24
11.5
Node Functional State Register (NFSR) . . . . . . . 24
11.6
Main Event Register (MAEV) . . . . . . . . . . . . . . . . 25
11.7
Main Mask Register (MAMSK) . . . . . . . . . . . . . . 25
11.8
Alternate Event Register (ALTEV) . . . . . . . . . . . . 25
11.9
Alternate Mask Register (ALTMSK) . . . . . . . . . . . 26
11.10 Transmit Event Register (TXEV) . . . . . . . . . . . . . 26
11.11 Transmit Mask Register (TXMSK) . . . . . . . . . . . 26
11.12 Receive Event Register (RXEV) . . . . . . . . . . . . . 27
11.13 Receive Mask Register (RXMSK) . . . . . . . . . . . 27
11.14 NAK Event Register (NAKEV) . . . . . . . . . . . . . . 27
11.15 NAK Mask Register (NAKMSK) . . . . . . . . . . . . . 27
11.16 FIFO Warning Event Register (FWEV) . . . . . . . . 27
11.17 FIFO Warning Mask Register (FWMSK) . . . . . . 28
11.18 Frame Number High Byte Register (FNH) . . . . . 28
11.19 Frame Number Low Byte Register (FNL) . . . . . . 28
11.20 Function Address Register (FAR) . . . . . . . . . . . . 28
11.21 Endpoint Control Register 0 (EPC0) . . . . . . . . . . 29
11.22 Transmit Status Register 0 (TXS0) . . . . . . . . . . . 29
11.23 Transmit Command Register 0 (TXC0) . . . . . . . 29
11.24 Transmit Data Register 0 (TXD0) . . . . . . . . . . . . 30
11.25 Receive Status Register 0 (RXS0) . . . . . . . . . . . 30
11.26 Receive Command Register 0 (RXC0) . . . . . . . . 30
11.27 Receive Data Register 0 (RXD0) . . . . . . . . . . . . 31
11.28 Endpoint Control Register x (EPC1 through
EPC6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11.29 Transmit Status Register x (TXS1, TXS2, TXS3) 31
11.30 Transmit Command Register x (TXC1, TXC2, TXC3)
32
11.31 Transmit Data Register x (TXD1, TXD2, TXD3) . 32
11.32 Receive Status Register x (RXS1, RXS2, RXS3) 33
11.33 Receive Command Register x (RXC1, RXC2, RXC3)
33
11.34 Receive Data Register x (RXD1, RXD2, RXD3) . 34
12.0
Design considerations . . . . . . . . . . . . . . . . . . . . . . . . 35
12.1
Targeted Applications . . . . . . . . . . . . . . . . . . . . . 35
12.2
3.3V Regulator Issues . . . . . . . . . . . . . . . . . . . . 35
12.3
Simplified Application Diagrams . . . . . . . . . . . . . 35
13.0
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
14.0
Electrical Characteristics - PRELIMINARY . . . . . . . . 37
14.1
Parallel Interface Timing (MODE[1:0] = 00b) . . . 39
14.2
Parallel Interface Timing (MODE[1:0] = 01b) . . . 41
14.3
DMA Support Timing . . . . . . . . . . . . . . . . . . . . . 43
14.4
MICROWIRE Interface Timing
(MODE[1:0] = 10b) . . . . . . . . . . . . . . . . . . . . . . . 44
15.0
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 45
4
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3.0 Device Overview
The USBN9602 is an integrated USB Node controller. The
block diagram on page 1 of the data sheet shows the ma-
jor on-chip components of the device.
3.1 Transceiver
The USBN9602 contains a high-speed transceiver, which
consists of three main functional blocks:
differential receiver
single-ended receiver with on-chip voltage reference
transmitter with on-chip current source
The performance requirements met by this transceiver are
described in Chapter 7 of the Universal Serial Bus Speci-
fication Version 1.0.
To minimize signal skew, the differential output swings of
the transmitter are well balanced. Slew-rate control is
used on the driver to minimize radiated noise and cross
talk. The drivers support TRI-STATE operation to allow
bidirectional half-duplex operation of the transceiver.
The differential receiver operates over the complete com-
mon mode range, that is guaranteed to be larger than that
of the single-ended receivers, to avoid potential glitches in
the Serial Interface Engine (SIE) after Single-Ended Ze-
ros.
Single-ended receivers are present on each of the two
data lines. These are required, in addition to the differen-
tial receiver, to detect an absolute voltage with a switching
threshold between 0.8V and 2.0V (TTL inputs). An exter-
nal 1.5
5% k
resistor, tied to a voltage source between
3.0V and 3.6V referenced to the local ground, is required
on D+ to indicate that this is a high-speed node.
3.2 Voltage Regulator (VReg)
The Voltage Regulator provides a 3.3V voltage from the
5.0V device power for the integrated transceiver. This
3.3V output can be used to supply power to the 1.5 k
pull-up resistor. It can be disabled under software control
to allow using the device in a 3.3V system. This output
must be decoupled with a 10
F tantalum capacitor to
ground.
3.3 Serial Interface Engine (SIE)
The USB Serial Interface Engine (SIE) consists of a Phys-
ical Layer Interface (PHY) level and a Media Access Con-
troller (MAC) level. The PHY level includes the digital-
clock recovery circuit, a digital glitch filter, End_Of_Packet
detection circuitry, and bit stuffing and unstuffing logic.
The MAC level includes packet formatting, CRC genera-
tion and checking, endpoint address detection, and pro-
vides the necessary control to give the NAK, ACK, and
STALL responses as determined by the Endpoint Control-
ler for the specified endpoint pipe. The SIE is also respon-
sible for detecting and reporting events on detection of
USB-specific events such as Reset, Suspend, and Re-
sume. The transmitter outputs of the module to the trans-
ceiver are well matched (under 1 ns) to minimize skew on
the USB signals.
The USB standard specifies bit stuffing and unstuffing as
a method to ensure adequate transitions on the line to en-
able clock recovery at the receiving end. Whenever a
string of consecutive 1s is encountered, the bit-stuffing
logic inserts a 0 after every sixth 1 in the data stream. The
bit-unstuffing logic reverses this process.
The clock recovery block uses the incoming NRZI data to
extract a data clock (12 MHz) from an input clock derived
from a crystal or crystal oscillator (48 MHz frequency).
This clock is used in the data recovery circuit. The output
of this block is binary data (decoded from the NRZI
stream) that can be appropriately sampled using the ex-
tracted 12 MHz clock. The jitter performance and timing
characteristics meet the requirements set forth in Chapter
7 of the USB Specification.
3.4 Endpoint/Control FIFOs
The Endpoint Pipe Controller (EPC) provides the interface
for USB Function endpoints. An endpoint is the ultimate
source or sink of data. An endpoint pipe provides for the
movement of data between USB and memory, and com-
pletes the path between the USB Host and the function
endpoint. According to the USB specification, up to 31
such endpoint pipes are supported at any given time,
each with the same Function Address. The USBN9602,
however, supports a maximum of seven endpoint pipes.
A USB Function is a USB device that is able to transmit
and receive information on the bus. A Function may have
one or more configurations, each of which defines the in-
terfaces that make up the device. Each interface, in turn,
is composed of one or more endpoints.
Each endpoint is an addressable entity on USB and is re-
quired to respond to IN and OUT tokens from the USB
Host (typically a PC). An IN token indicates that the host
has requested to receive information from an endpoint,
and an OUT token indicates that the host is about to send
information to an endpoint.
Upon detection of an IN token addressed to an endpoint,
the endpoint is responsible for responding with a data
packet. If the endpoint is currently stalled, a STALL hand-
shake packet is sent under software control. If the end-
point is enabled, but no data is present, a NAK (Negative
Acknowledgment) handshake packet is sent automatically.
If the Endpoint is Isochronous and enabled, but no data
present, a bit stuff error followed by an end of packet is
sent on the bus.
Similarly, upon detection of an OUT token addressed to
an endpoint, the endpoint is responsible for receiving a
data packet sent by the host and storing it in a buffer. If
the endpoint pipe is currently stalled, a STALL handshake
packet is sent at the end of the data transmission. If the
endpoint pipe is currently disabled, no handshake packet
is sent at the end of the data transmission. If the endpoint
pipe is enabled, but no buffer is present in which to store
the data, a NAK (Negative Acknowledgment) handshake
packet is sent. If the Endpoint is Isochronous and enabled
but can't handle the data, the data will be lost.
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A Disabled endpoint does not respond to IN, OUT, or
SETUP tokens.
The Endpoint Pipe Controller maintains separate status
and control information for each endpoint pipe.
For IN tokens, the Endpoint Pipe Controller is responsible
for transferring data from the defined buffer to the host.
For OUT tokens, the Endpoint Pipe Controller is responsi-
ble for transferring data from the host to the defined buffer.
3.5 Microcontroller Interface
A CPU or microcontroller can be connected via an 8-bit
parallel interface or a MICROWIRE interface. For the par-
allel interface, there are two addressing modes (multi-
plexed or non-multiplexed). These modes are selected by
hardwiring the proper binary code on the MODE1 and
MODE0 pins.
In addition, an interrupt output is provided. The type of the
interrupt can be programmed to be either push-pull active-
high or active-low output, or an open-drain active-low out-
put.
4.0 Connection Diagram
Figure 1. USBN9602 Connection Diagram
CS
RD
WR/SK
DACK
GND
Vcc
GND
MODE1
MODE0
D6
D5
D4
D3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
INTR
XOUT
XIN
CLKOUT
D7
AGND
D
D+
V3.3
RESET
A0/ALE/SI
D0/SO
D1
D2
28 pin
SO
DRQ
Order Number USBN9602-28M
See NS Package Number M28B
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