TL H 5057
TP5089
DTMF(TOUCH-TONE)
Generator
December 1991
TP5089 DTMF (TOUCH-TONE) Generator
General Description
The TP5089 is a low threshold voltage field-implanted met-
al gate CMOS integrated circuit It interfaces directly to a
standard telephone keypad and generates all dual tone mul-
ti-frequency pairs required in tone-dialing systems The tone
synthesizers are locked to an on-chip reference oscillator
using an inexpensive 3 579545 MHz crystal for high tone
accuracy The crystal and an output load resistor are the
only external components required for tone generation A
MUTE OUT logic signal which changes state when any key
is depressed is also provided
Features
Y
3 5V 10V operation when generating tones
Y
2V operation of keyscan and MUTE logic
Y
Static sensing of key closures or logic inputs
Y
On-chip 3 579545 MHz crystal-controlled oscillator
Y
Output amplitudes proportional to supply voltage
Y
High group pre-emphasis
Y
Low harmonic distortion
Y
Open emitter-follower low-impedance output
Y
SINGLE TONE INHIBIT pin
Block Diagram
TL H 5057 1
FIGURE 1
C1995 National Semiconductor Corporation
RRD-B30M115 Printed in U S A
Absolute Maximum Ratings
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (V
DD
b
V
SS
)
15V
Maximum Voltage at Any Pin
V
DD
a
0 3V to V
SS
b
0 3V
Operating Temperature
b
30 C to
a
60 C
Storage Temperature
b
55 C to
a
150 C
Maximum Power Dissipation
500 mW
Electrical Characteristics
Unless otherwise noted limits printed in BOLD characters are guaranteed for V
DD
e
3 5V to 10V T
A
e
0 C to
a
60 C by correlation with 100% electrical testing at T
A
e
25 C All other limits are assured by
correlation with other production tests and or product design and characterization
Parameter
Conditions
Min
Typ
Max
Units
Minimum Supply Voltage for Keysense
2
V
and MUTE Logic Functions
Minimum Operating Voltage
3 5
V
for generating tones
Operating Current
Mute open
2
25
m
A
Idle
R
L
e
%
1 1
2 5
mA
Generating Tones
V
DD
e
3 5V
Input Resistors
COLUMN and ROW (Pull-Up)
25
50
kX
SINGLE TONE INHIBIT (Pull-Down)
120
kX
TONE DISABLE (Pull-Up)
Input Low Level
0 2 V
DD
V
Input High Level
0 8 V
DD
V
MUTE OUT Sink Current
V
DD
e
3 5V
0 4
mA
(COLUMN and ROW Active)
V
o
e
0 5V
MUTE Out Leakage Current
V
o
e
V
DD
1
m
A
Output Amplitude
R
L
e
240 X
190
250
340
mVrms
Low Group
V
DD
e
3 5V
R
L
e
240X
510
700
880
mVrms
V
DD
e
10V
Output Amplitude
R
L
e
240X
270
340
470
mVrms
High Group
V
DD
e
3 5V
R
L
e
240X
735
955
1265
mVrms
V
DD
e
10V
Mean Output DC Offset
V
DD
e
3 5V
1 3
V
V
DD
e
10V
4 6
V
High Group Pre-Emphasis
2 2
2 7
3 2
dB
Dual Tone Total Harmonic Distortion Ratio
V
DD
e
4V R
L
e
240X
b
23
b
22
dB
1 MHz Bandwidth
Start-Up Time (to 90% Amplitude)
3
5
mS
Note 1
R
L
is the external load resistor connected from TONE OUT to V
SS
Note 2
Crystal specification Parallel resonant 3 579545 MHz R
S
s
150 X L
e
100 mH C
O
e
5 pF C
I
e
0 02 pF
2
Connection Diagram
Dual-In-Line Package
TL H 5057 2
Top View
Order Number TP5089N
See NS Package N16A
Pin Descriptions
Symbol
Description
V
DD
This is the positive voltage
supply to the device referenced
to V
SS
The collector of the
TONE OUT transistor is
connected to this pin
V
SS
This is the negative voltage
supply All voltages are
referenced to this pin
OSC IN OSC OUT
All tone generation timing is
derived from the on-chip
oscillator circuit A low cost
3 579545 MHz A-cut crystal
(NTSC TV color-burst) is
needed between pins 7 and 8
Load capacitors and a feedback
resistor are included on-chip for
good start-up and stability The
oscillator stops when column
inputs are sensed with no valid
input having been detected The
oscillator is also stopped when
the TONE DISABLE input is
pulled to logic low
Row and Column Inputs
When no key is pushed pull-up
resistors are active on row and
column inputs A key closure is
recognized when a single row
and a single column are
connected to V
SS
which starts
the oscillator and initiates tone
generation Negative-true logic
signals simulating key closures
can also be used
TONE DISABLE
The TONE DISABLE input has
Input
an internal pull-up resistor
When this input is open or at
logic high the normal tone
output mode will occur When
TONE DISABLE input is at logic
low the device will be in the
inactive mode TONE OUT will
be at an open circuit state
Symbol
Description
MUTE Output
The MUTE output is an open-
drain N-channel device that
sinks current to V
SS
with any
key input and is open when no
key input is sensed The MUTE
output will switch regardless of
the state of the SINGLE TONE
INHIBIT input
SINGLE TONE INHIBIT
The SINGLE TONE INHIBIT
Input
input is used to inhibit the
generation of other than valid
tone pairs due to multiple row-
column closures It has a pull-
down resistor to V
SS
and when
left open or tied to V
SS
any
input condition that would
normally result in a single tone
will now result in no tone with
all other functions operating
normally When tied to V
DD
single or dual tones may be
generated see Table II
TONE OUT
This output is the open emitter
of an NPN transistor the
collector of which is connected
to V
DD
When an external load
resistor is connected from
TONE OUT to V
SS
the output
voltage on this pin is the sum of
the high and low group sine-
waves superimposed on a DC
offset When not generating
tones this output transistor is
turned OFF to minimize the
device idle current
Adjustment of the emitter load
resistor results in variation of
the mean DC current during
tone generation the sinewave
signal current through the
output transistor and the output
distortion Increasing values of
load resistance decrease both
the signal current and distortion
Functional Description
With no key inputs to the device the oscillator is inhibited
the output transistor is pulled OFF and device current con-
sumption is reduced to a minimum Key closures are sensed
statically Any key closure activates the MUTE output starts
the oscillator and sets the high group and low group pro-
grammable counters to the appropriate divide ratio These
counters sequence two ratioed-capacitor D A converters
through a series of 28 equal duration steps per sine-wave
cycle The two tones are summed by a mixer amplifier with
pre-emphasis applied to the high group tone The output is
an NPN emitter-follower requiring the addition of an external
load resistor to V
SS
This resistor facilitates adjustment of
the signal current flowing from V
DD
through the output tran-
sistor
The amplitude of the output tones is directly proportional to
the device supply voltage
3
Functional Description
(Continued)
TABLE I Output Frequency Accuracy
Tone
Valid
Standard
Tone Output
% Deviation
Group
Input
DTMF (Hz)
Frequency
from Standard
Low
R1
697
694 8
b
0 32
Group
R2
770
770 1
a
0 02
f
L
R3
852
852 4
a
0 03
R4
941
940 0
b
0 11
High
C1
1209
1206 0
b
0 24
Group
C2
1336
1331 7
b
0 32
f
H
C3
1477
1486 5
a
0 64
C4
1633
1639 0
a
0 37
TABLE II Functional Truth Table
SINGLE TONE
TONE
ROW
COLUMN
TONE OUT
MUTE
INHIBIT
DISABLE
Low
High
X
O
O C
O C
0V
0V
O C
X
X
O C
O C
0V
0V
O C
X
0
One
One
V
OS
V
OS
O
X
1
One
One
f
L
f
H
O
1
1
2 or More
One
f
H
O
1
1
One
2 or More
f
L
O
1
1
2 or More
2 or More
V
OS
V
OS
O
0
1
2 or More
One
V
OS
V
OS
O
0
1
One
2 or More
V
OS
V
OS
O
0
1
2 or More
2 or More
V
OS
V
OS
O
Note 1
X is don't care state
Note 2
V
OS
is the output offset voltage
TL H 5057 3
Adjust R
E
for desired tone amplitude
FIGURE 2 Typical Application
4
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