The TMS41x409A and TMS42x409A series are
16 777 216-bit dynamic random-access memory
(DRAM) devices organized as 4 194 304 words of
four bits each.
These devices feature maximum RAS access
times of 50, 60, and 70 ns. All address and data-in
lines are latched on chip to simplify system
design. Data out is unlatched to allow greater
system flexibility.
description
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B AUGUST 1996 REVISED APRIL 1997
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
This data sheet is applicable to all
TMS41x409As and TMS42x409As symbolized
by Revision "B", Revision "E", and subsequent
revisions as described in the device
symbolization section.
D
Organization . . . 4 194 304
4
D
Single Power Supply (5 V or 3.3 V)
D
Performance Ranges:
ACCESS ACCESS ACCESS
EDO
TIME
TIME
TIME
CYCLE
tRAC
tCAC
tAA
tHPC
MAX
MAX
MAX
MIN
'41x409A-50
50 ns
13 ns
25 ns
20 ns
'41x409A-60
60 ns
15 ns
30 ns
25 ns
'41x409A-70
70 ns
18 ns
35 ns
30 ns
'42x409A-50
50 ns
13 ns
25 ns
20 ns
'42x409A-60
60 ns
15 ns
30 ns
25 ns
'42x409A-70
70 ns
18 ns
35 ns
30 ns
D
Extended-Data-Out (EDO) Operation
D
CAS-Before-RAS ( CBR ) Refresh
D
Low Power Dissipation
D
3-State Unlatched Output
D
High-Reliability Plastic 24 / 26-Lead
300-Mil-Wide Surface-Mount Small-Outline
J-Lead (SOJ) Package (DJ Suffix) and
24/26-Lead 300-Mil-Wide Surface-Mount
Thin Small-Outline Package (TSOP)
(DGA Suffix)
D
Operating Free-Air Temperature Range
0
C to 70
C
AVAILABLE OPTIONS
DEVICE
POWER
SUPPLY
SELF
REFRESH,
BATTERY
BACKUP
REFRESH
CYCLES
TMS416409A
5 V
4 096 in 64 ms
TMS417409A
5 V
2 048 in 32 ms
TMS426409A
3.3 V
4 096 in 64 ms
TMS427409A
3.3 V
2 048 in 32 ms
The TMS416409A and TMS417409A are offered in a 24 / 26-lead plastic surface-mount SOJ package
(DJ suffix). The TMS426409A and TMS427409A are offered in a 24/26-lead plastic surface-mount SOJ
package (DJ suffix) and a 24 / 26-lead plastic surface-mount TSOP (DGA suffix). These packages are designed
for operation from 0
C to 70
C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PIN NOMENCLATURE
A0 A11
Address Inputs
DQ1 DQ4
Data In / Data Out
CAS
Column-Address Strobe
NC
No Internal Connection
OE
Output Enable
RAS
Row-Address Strobe
VCC
5-V or 3.3-V Supply
VSS
Ground
W
Write Enable
A11 is NC for TMS417409A and TMS427409A.
See Available Options Table
DJ/DGA PACKAGES
( TOP VIEW )
V
CC
DQ1
DQ2
W
RAS
A0
A1
A2
A3
V
CC
V
SS
DQ4
DQ3
CAS
OE
A7
A6
A5
A4
V
SS
26
25
24
23
22
18
17
16
15
14
1
2
3
4
5
9
10
11
12
13
A11
A9
21
6
A10
A8
19
8
Copyright
1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B AUGUST 1996 REVISED APRIL 1997
2
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
logic symbol (TMS416409A and TMS426409A)
A0
A1
A2
A3
A4
A5
A6
A7
A8
RAS
CAS
W
OE
9
10
11
12
19
15
16
17
18
5
23
4
22
20D10/21D0
20D19/21D9
C20 [ROW]
G23/[REFRESH ROW]
24 [PWR DWN]
C21[COLUMN]
G24
23C22
23,21D
24,25 EN
G25
A
0
4 194 303
RAM 4096 K
4
&
A9
21
2
3
24
25
A,Z26
A,22D
26
DQ1
DQ2
DQ3
DQ4
A10
8
20D21
A11
6
20D20
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B AUGUST 1996 REVISED APRIL 1997
3
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
logic symbol (TMS417409A and TMS427409A)
A0
A1
A2
A3
A4
A5
A6
A7
A8
RAS
CAS
W
OE
9
10
11
12
19
15
16
17
18
5
23
4
22
20D11/21D0
C20 [ROW]
G23/[REFRESH ROW]
24 [PWR DWN]
C21[COLUMN]
G24
23C22
23,21D
24,25 EN
G25
A
0
4 194 303
RAM 4096 K
4
&
A9
21
2
3
24
25
A,Z26
A,22D
26
DQ1
DQ2
DQ3
DQ4
A10
8
20D21/21D10
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B AUGUST 1996 REVISED APRIL 1997
4
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
functional block diagram
TMS416409A, TMS426409A
R
o
w
D
e
c
o
d
e
A0
A1
A11
Timing and Control
Column-
Address
Buffers
Row-
Address
Buffers
I/O
Buffers
Data-
In
Reg.
Data-
Out
Reg.
Column Decode
Sense Amplifiers
64
256K Array
256K Array
256K Array
RAS
CAS
W
DQ1 DQ4
4
4
OE
10
12
12
4
4
Column addresses A10 and A11 are not used.
TMS417409A, TMS427409A
A0
A1
A10
32
Timing and Control
Column-
Address
Buffers
Row-
Address
Buffers
I/O
Buffers
Data-
In
Reg.
Data-
Out
Reg.
Column Decode
Sense Amplifiers
R
o
w
D
e
c
o
d
e
32
256K Array
256K Array
256K Array
256K Array
256K Array
256K Array
RAS
CAS
W
DQ1 DQ4
4
4
OE
11
11
11
4
4
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B AUGUST 1996 REVISED APRIL 1997
5
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
operation
extended data out
Extended data out (EDO) allows data output rates of up to 50 MHz for 50-ns devices. When keeping the same
row address while selecting random column addresses, the time for row-address setup and hold and for address
multiplex is eliminated. The maximum number of columns that can be accessed is determined by t
RASP
, the
maximum RAS low time.
Extended data out does not place the data in / data out pins (DQ pins) into the high-impedance state with the
rising edge of CAS. The output remains valid for the system to latch the data. After CAS goes high, the DRAM
decodes the next address. OE and W can control the output impedance. Descriptions of OE and W further
explain EDO operation benefit.
address: A0 A11 ( TMS416409A and TMS426409A) and A0 A10 (TMS417409A and TMS427409A)
Twenty-two address bits are required to decode each of the 4 194 304 storage cell locations. For the
TMS416409A and TMS426409A,12 row-address bits are set up on A0 through A11 and latched onto the chip
by the row-address strobe (RAS). Ten column-address bits are set up on A0 through A9. For the TMS417409A
and TMS427409A, 11 row-address bits are set up on inputs A0 through A10 and latched onto the chip by RAS.
Eleven column-address bits are set up on A0 through A10. All addresses must be stable on or before the falling
edge of RAS and CAS. RAS is similar to a chip enable because it activates the sense amplifiers as well as the
row decoder. CAS is used as a chip select, activating the output buffers and latching the address bits into the
column-address buffers.
output enable (OE)
OE controls the impedance of the output buffers. While CAS and RAS are low and W is high, OE can be brought
low or high and the DQs transition between valid data and high impedance (see Figure 8). There are two
methods for placing the DQs into the high-impedance state and maintaining that state during CAS high time.
The first method is to transition OE high before CAS transitions high and keep OE high for t
CHO
(hold time, OE
from CAS) past the CAS transition. This disables the DQs and they remain disabled, regardless of OE, until CAS
falls again. The second method is to have OE low as CAS transitions high. Then OE can pulse high for a
minimum of t
OEP
(precharge time, OE) anytime during CAS high time, disabling the DQs regardless of further
transitions on OE until CAS falls again (see Figure 8).
write enable ( W )
The read or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded. If W goes low in an extended-data-out read cycle, the DQs are disabled so long as CAS is high
(see Figure 9).
data in / data out (DQ1 DQ4)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the later falling
edge of CAS or W strobes data into the on-chip data latch with setup and hold times referenced to the later edge.
The DQs drive valid data after all access times are met and remain valid except in cases described in the W
and OE sections.
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