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SCANSTA111
Enhanced SCAN bridge
Multidrop Addressable IEEE 1149.1 (JTAG) Port
General Description
The SCANSTA111 extends the IEEE Std. 1149.1 test bus
into a multidrop test bus environment. The advantage of a
multidrop approach over a single serial scan chain is im-
proved test throughput and the ability to remove a board
from the system and retain test access to the remaining
modules. Each SCANSTA111 supports up to 3 local
IEEE1149.1 scan rings which can be accessed individually
or combined serially. Addressing is accomplished by loading
the instruction register with a value matching that of the Slot
inputs. Backplane and inter-board testing can easily be ac-
complished by parking the local TAP Controllers in one of the
stable TAP Controller states via a Park instruction. The 32-bit
TCK counter enables built in self test operations to be per-
formed on one port while other scan chains are simulta-
neously tested.
Features
n
True IEEE 1149.1 hierarchical and multidrop
addressable capability
n
The 7 slot inputs support up to 121 unique addresses,
an Interrogation Address, Broadcast Address, and 4
Multi-cast Group Addresses (address 000000 is
reserved)
n
3 IEEE 1149.1-compatible configurable local scan ports
n
Mode Register
0
allows local TAPs to be bypassed,
selected for insertion into the scan chain individually, or
serially in groups of two or three
n
Transparent Mode can be enabled with a single
instruction to conveniently buffer the backplane IEEE
1149.1 pins to those on a single local scan port
n
LSP ACTIVE outputs provide local port enable signals
for analog busses supporting IEEE 1149.4.
n
General purpose local port passthrough bits are useful
for delivering write pulses for FPGA programming or
monitoring device status.
n
Known Power-up state
n
TRST on all local scan ports
n
32-bit TCK counter
n
16-bit LFSR Signature Compactor
n
Local TAPs can become TRI-STATE via the OE input to
allow an alternate test master to take control of the local
TAPs (LSP
0-2
have a TRI-STATE notification output)
n
3.0-3.6V V
CC
Supply Operation
n
Power-off high impedance inputs and outputs
n
Supports live insertion/withdrawal
Connection Diagrams
10124502
10124516
April 2004
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Enhanced
SCAN
bridge
Multidrop
Addressable
IEEE
1
149.1
(JT
AG)
Port
2004 National Semiconductor Corporation
DS101245
www.national.com
TABLE 1. Glossary
LFSR
Linear Feedback Shift Register. When enabled, will generate a 16-bit signature of sampled serial test
data.
LSP
Local Scan Port. A four signal port that drives a local (i.e. non-backplane) scan chain. (e.g., TCK
0
, TMS
0
,
TDO
0
, TDI
0
).
Local
Local is used to describe IEEE Std. 1149.1 compliant scan rings and the SCANSTA111 Test Access Port
that drives them. The term local was adopted from the system test architecture that the 'STA111 will most
commonly be used in; namely, a system test backplane with a 'STA111 on each card driving up to 3 local
scan rings per card. (Each card can contain multiple 'STA111s, with 3 local scan ports per 'STA111.)
Park/Unpark/Unparked Parked, unpark, and unparked, are used to describe the state of the LSP controller and the state of the
local TAP controllers (the local TAP controllers refers to the TAP controllers of the scan components that
make up a local scan ring). Park is also used to describe the action of parking a LSP (transitioning into
one of the Parked LSP controller states). It is important to understand that when a LSP controller is in
one of the parked states, TMS
n
is held constant, thereby holding or parking the local TAP controllers in a
given state.
TAP
Test Access Port as defined by IEEE Std. 1149.1.
Selected/Unselected
Selected and Unselected refers to the state of the 'STA111 Selection Controller. A selected 'STA111 has
been properly addressed and is ready to receive Level 2 protocol. Unselected 'STA111s monitor the
system test backplane, but do not accept Level 2 protocol (except for the GOTOWAIT instruction). The
data registers and LSPs of unselected 'STA111s are not accessible from the system test master.
Active Scan Chain
The Active Scan Chain refers to the scan chain configuration as seen by the test master at a given
moment. When a 'STA111 is selected with all of its LSPs parked, the active scan chain is the current
scan register only. When a LSP is unparked, the active scan chain becomes: TDI
B
the current 'STA111
register
the local scan ring registers a PAD bit TDO
B
. Refer to Table 7 for Unparked
configurations of the LSP network.
Level 1 Protocol
Level 1 is the protocol used to address a 'STA111.
Level 2 Protocol
Level 2 is the protocol that is used once a 'STA111 is selected. Level 2 protocol is IEEE Std. 1149.1
compliant when an individual 'STA111 is selected.
PAD
A one bit register that is placed at the end of each local scan port scan-chain. The PAD bit eliminates the
prop delay that would be added by the 'STA111 LSPN logic between TDI
n
and TDO
(n+1)
or TDO
B
by
buffering and synchronizing the LSP TDI inputs to the falling edge of TCK
B
, thus allowing data to be
scanned at higher frequencies without violating set-up and hold times.
LSB
Least Significant Bit, the right-most position in a register (bit 0).
MSB
Most Significant Bit, the left-most position in a register.
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Architecture
Figure 1 shows the basic architecture of the 'STA111. The
device's major functional blocks are illustrated here. The
TAP Controller, a 16-state state machine, is the central con-
trol for the device. The instruction register and various test
data registers can be scanned to exercise the various func-
tions of the 'STA111 (these registers behave as defined in
IEEE Std. 1149.1). The 'STA111 selection controller provides
the functionality that allows the 1149.1 protocol to be used in
a multi-drop environment. It primarily compares the address
input to the slot identification and enables the 'STA111 for
subsequent scan operations. The Local Scan Port Network
(LSPN) contains multiplexing logic used to select different
port configurations. The LSPN control block contains the
Local Scan Port Controllers (LSPC) for each Local Scan Port
(LSP
0
, LSP
1
... LSP
n
). This control block receives input from
the 'STA111 instruction register, mode registers, and the TAP
controller. Each local port contains all four boundary scan
signals needed to interface with the local TAPs plus the
optional Test Reset signal (TRST).
10124503
FIGURE 1. SCANSTA111 Block Diagram
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TABLE 2. Pin Descriptions
Pin Name
Description
No.
Pins
I/O
VCC
3
N/A
Power
GND
3
N/A
Ground
TMS
B
1
I
BACKPLANE TEST MODE SELECT: Controls sequencing through the TAP Controller of the
'STA111. Also controls sequencing of the TAPs which are on the local scan chains. This input
has a 25K
pull-up resistor and no ESD clamp diode (ESD is controlled with an alternate
method). When the device is power-off (V
DD
floating), this input appears to be a capacitive
load to ground (Note 4). When V
DD
= 0V (i.e.; not floating but tied to V
SS
) this input appears
to be a capacitive load with the pull-up to ground.
TDI
B
1
I
BACKPLANE TEST DATA INPUT: All backplane scan data is supplied to the 'STA111 through
this input pin. This input has a 25K
pull-up resistor and no ESD clamp diode (ESD is
controlled with an alternate method). When the device is power-off (V
DD
floating), this input
appears to be a capacitive load to ground (Note 4). When V
DD
= 0V (i.e.; not floating but tied
to V
SS
) this input appears to be a capacitive load with the pull-up to ground.
TDO
B
1
O
BACKPLANE TEST DATA OUTPUT: This output drives test data from the 'STA111 and the
local TAPs, back toward the scan master controller. This output has 24mA of drive current.
When the device is power-off (V
DD
= 0V or floating), this output appears to be a capacitive
load (Note 4).
TCK
B
1
I
TEST CLOCK INPUT FROM THE BACKPLANE: This is the master clock signal that controls
all scan operations of the 'STA111 and of the local scan ports. This input has no pull-up
resistor and no ESD clamp diode (ESD is controlled with an alternate method). When the
device is power-off (V
DD
floating), this input appears to be a capacitive load to ground (Note
4). When V
DD
= 0V (i.e.; not floating but tied to V
SS
) this input appears to be a capacitive
load to ground.
TRST
B
1
I
TEST RESET: An asynchronous reset signal (active low) which initializes the 'STA111 logic.
This input has a 25K
pull-up resistor and no ESD clamp diode (ESD is controlled with an
alternate method). When the device is power-off (V
DD
floating), this input appears to be a
capacitive load to ground (Note 4). When V
DD
= 0V (i.e.; not floating but tied to V
SS
) this
input appears to be a capacitive load with the pull-up to ground.
TRIST
B
1
O
BACKPLANE TRI-STATE NOTIFICATION OUTPUT: This signal is high when the backplane
scan port is TRI-STATEd. This pin is used for backplane physical layer changes (i.e.; TTL to
LVDS). This output has 12mA of drive current.
A
B
1
I
BACKPLANE PASS-THROUGH INPUT: A general purpose input which is driven to the Y
n
of
a single selected LSP. (Not available when multiple LSPs are selected). This input has an
internal pull-up resistor.
Y
B
1
O
BACKPLANE PASS-THROUGH OUTPUT: A general purpose output which is driven from the
A
n
of a single selected LSP. (Not available when multiple LSPs are selected). This output
has 24mA of drive current.
S
(0-6)
7
I
SLOT IDENTIFICATION: The configuration of these pins is used to identify (assign a unique
address to) each 'STA111 on the system backplane (Note 1).
OE
1
I
OUTPUT ENABLE for the Local Scan Ports, active low. When high, this active-low control
signal TRI-STATEs all local scan ports on the 'STA111, to enable an alternate resource to
access one or more of the three local scan chains.
TDO
(0-2)
3
O
TEST DATA OUTPUTS: Individual output for each of the local scan ports (Note 2). These
outputs have 24mA of drive current.
TDI
(0-2)
3
I
TEST DATA INPUTS: Individual scan data input for each of the local scan ports (Note 2).
TMS
(0-2)
3
O
TEST MODE SELECT OUTPUTS: Individual output for each of the local scan ports. TMS
n
does not provide a pull-up resistor (which is assumed to be present on a connected TMS
input, per the IEEE 1149.1 requirement) (Note 2). These outputs have 24mA of drive current.
TCK
(0-2)
3
O
LOCAL TEST CLOCK OUTPUTS: Individual output for each of the local scan ports. These
are buffered versions of TCK
B
(Note 2). These outputs have 24mA of drive current.
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TABLE 2. Pin Descriptions (Continued)
Pin Name
Description
No.
Pins
I/O
TRST
(0-2)
3
O
LOCAL TEST RESETS: A gated version of TRST
B
(Note 2). These outputs have 24mA of
drive current.
A
(0-1)
2
I
LOCAL PASS-THROUGH INPUTS: General purpose inputs which can be driven to the
backplane pin Y
B
. (Only on LSP
0
and LSP
1
. Only available when a single LSP is selected)
(Note 2). These inputs have an internal pull-up resistor.
Y
(0-1)
2
O
LOCAL PASS-THROUGH OUTPUT: General purpose outputs which can be driven from the
backplane pin A
B
. (Only on LSP
0
and LSP
1
. Only available when a single LSP is selected)
(Note 2). These outputs have 24mA of drive current.
LSP_ACTIVE
(0-2)
3
O
LOCAL ANALOG TEST BUS ENABLE: These analog pins serve as enable signals for analog
busses supporting the IEEE 1149.4 Mixed-Signal Test Bus standard (Note 2), or for
backplane physical layer changes (i.e.; TTL to LVDS). These outputs have 12mA of drive
current.
TRIST
(0-2)
3
O
LOCAL TRI-STATE NOTIFICATION OUTPUTS: This signal is high when the local scan ports
are TRI-STATEd (Note 2). These pins are used for backplane physical layer changes (i.e.;
TTL to LVDS). These outputs have 12mA of drive current.
GPI
n
N/A
I
DEDICATED GENERAL PURPOSE INPUTS: These dedicated inputs (available in HDL) are
controlled by registers that can be read or written using the dot1 backplane pins (TDI
B
,
TDO
B
, TMS
B
and TCK
B
) (Note 3).
GPO
n
N/A
O
DEDICATED GENERAL PURPOSE OUTPUTS: These dedicated outputs (available in HDL)
are controlled by registers that can be read or written using the dot1 backplane pins (TDI
B
,
TDO
B
, TMS
B
and TCK
B
) (Note 3).
TEST ENABLE
1
I
TEST ENABLE INPUT: This pin is used for factory test and should be tied to V
CC
for normal
operation.
Note 1: The Silicon device will has seven (7) slot address pins. The HDL version is paramaterized to optionally allow 6, 7 or 8.
Note 2: The Silicon device will has three (3) LSP's. The HDL version is paramaterized to optionally allow up to 8 total LSPs.
Note 3: Up to four (4) GPI/O's per LSP. This feature is only available in the HDL version.
Note 4: Refer to the IBIS model on our website for I/O characteristics.
Application Overview
ADDRESSING SCHEME - The SCANSTA111 architecture
extends the functionality of the IEEE 1149.1 Standard by
supplementing that protocol with an addressing scheme
which allows a test controller to communicate with specific
'STA111s within a network of 'STA111s. That network can
include both multi-drop and hierarchical connectivity. In ef-
fect, the 'STA111 architecture allows a test controller to
dynamically select specific portions of such a network for
participation in scan operations. This allows a complex sys-
tem to be partitioned into smaller blocks for testing purposes.
The 'STA111 provides two levels of test-network partitioning
capability. First, a test controller can select individual
'STA111s, specific sets of 'STA111s (multi-cast groups), or all
'STA111s (broadcast). This 'STA111-selection process is
supported by a Level-1 communication protocol. Second,
within each selected 'STA111, a test controller can select
one or more of the chip's three local scan-ports. That is,
individual local ports can be selected for inclusion in the
(single) scan-chain which a 'STA111 presents to the test
controller. This mechanism allows a controller to select spe-
cific terminal scan-chains within the overall scan network.
The port-selection process is supported by a Level-2 proto-
col.
HIERARCHICAL SUPPORT - Multiple SCANSTA111's can
be used to assemble a hierarchical boundary-scan tree. In
such a configuration, the system tester can configure the
local ports of a set of 'STA111s so as to connect a specific
set of local scan-chains to the active scan chain. Using this
capability, the tester can selectively communicate with spe-
cific portions of a target system. The tester's scan port is
connected to the backplane scan port of a root layer of
'STA111s, each of which can be selected using multi-drop
addressing. A second tier of 'STA111s can be connected to
this root layer, by connecting a local port (LSP) of a root-
layer 'STA111 to the backplane port of a second-tier
'STA111. This process can be continued to construct a multi-
level scan hierarchy. 'STA111 local ports which are not cas-
caded into higher-level 'STA111s can be thought of as the
terminal leaves of a scan tree. The test master can select
one or more target leaves by selecting and configuring the
local ports of an appropriate set of 'STA111s in the test tree.
Check with your ATPG tool vendor to ensure support of this
feature.
State Machines
The 'STA111 is IEEE 1149.1-compatible, in that it supports
all required 1149.1 operations. In addition, it supports a
higher level of protocol, (Level 1), that extends the IEEE
1149.1 Std. to a multi-drop environment.
In multi-drop scan systems, a scan tester can select indi-
vidual 'STA111s for participation in upcoming scan opera-
tions. STA111 selection is accomplished by simultaneously
scanning a device address out to multiple STA111s. Through
an on-chip address matching process, only those 'STA111s
whose statically-assigned address matches the scanned-out
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