Document Outline
- SCANSTA101
- General Description
- Features
- SCANSTA101 Architecture
- TABLE 1. Interface Descriptions
- Connection Diagrams
- TABLE 2. Pin Descriptions
- Absolute Maximum Ratings
- Recommended Operating Conditions
- DC Electrical Characteristics
- AC Electrical Characteristics/Operating Requirements
- Applications/Programmers Reference
- TABLE 4. Memory/Register Address Map
- TABLE 5. Vector Structure
- TABLE 6. Header/Trailer Structure
- TABLE 7. Macro Structure
- TABLE 8. Header / Trailer Usage
- TABLE 9. Macro Type bits 10 and 11
- TABLE 10. Sequencer Structure
- TABLE 11. Scan Bridge Support Structure
- Module Descriptions
- Dual Port Memory
- Parallel Processor Interface
- Serial Scan Interface
- Hardware Interface Details
- Software Interface Details
- REGISTER DEFINITIONS
- TABLE 19. Start Register (START) ($00)
- TABLE 20. Status Register (STATUS) ($01)
- TABLE 21. Interrupt Control Register (INTCTRL) ($02)
- TABLE 22. Interrupt Status Register (INTSTAT) ($03)
- TABLE 23. Setup Register (SETUPR) ($04)
- TABLE 24. Clock Divider Register (CLKDIV) ($05)
- TABLE 25. TDI_SM LFSR Exponent Register (EXPR) ($07)
- TABLE 26. TDI_SM LFSR LSB Seed Register (LSSEDR) ($08) (Notes , )
- TABLE 27. TDI_SM LFSR MSB Seed Register (MSSEDR) ($09) (Notes , )
- TABLE 28. TDI_SM LFSR LSB Result Register (LSRESR) ($0A) (Notes , )
- TABLE 29. TDI_SM LFSR MSB Result Register (MSRESR) ($0B) (Notes , )
- TABLE 30. Index Register (INDEXR) ($0C) (Notes , , )
- TABLE 31. Vector Index Register (VINDEXR) ($11) (Notes , )
- TABLE 32. Header/Trailer Index Register (HTINDEXR) ($13) (Notes , )
- TABLE 33. Macro Index Register (MINDEXR) ($15) (Notes , )
- TABLE 34. Sequencer Index Register (SINDEXR) ($17) (Notes , )
- TABLE 35. ScanBridge Support Index Register (BSINDEXR) ($19) (Notes , )
- Testability Details - IEEE 1149.1 Support
- Physical Dimensions
SCANSTA101
Low Voltage IEEE 1149.1 STA Master
General Description
The SCANSTA101 is designed to function as a test master
for a IEEE 1149.1 test system. The minimal requirements to
create a tester are a microcomputer (uP, RAM/ROM, clock,
etc.), SCANEASE r2.0 software, and a STA101.
The SCANSTA101 is an enhanced version of, and replace-
ment for, the SCANPSC100. The additional features of the
STA101 further allow it to offload some of the processor
overhead while remaining flexible. The device architecture
supports IEEE 1149.1, BIST, and IEEE 1532. The flexibility
will allow it to adapt to any changes that may occur in 1532
and support yet unknown variants.
The SCANSTA101 is useful in improving vector throughput
when applying serial vectors to system test circuitry and
reduces the software overhead that is associated with ap-
plying serial patterns with a parallel processor. The SCAN-
STA101 features a generic Parallel Processor Interface
(PPI) which operates by serializing data from the parallel bus
for shifting through the chain of 1149.1 compliant compo-
nents (i.e., scan chain). Writes can be controlled either by
wait states or the DTACK line. Handshaking is accomplished
with either polling or interrupts.
Features
n
Compatible with IEEE Std. 1149.1 (JTAG) Test Access
Port and Boundary Scan Architecture
n
Supported by National's SCAN Ease (Embedded
Application Software Enabler) Software Rev 2.0
n
Available as a Silicon Device and Intellectual Property
(IP) model for embedding into VLSI devices
n
Uses generic, asynchronous processor interface;
compatible with a wide range of processors and PCLK
frequencies
n
16-bit Data Interface (IP scalable to 32-bit)
n
2Kx32 bit dual-port memory addressing for access by
the PPI or the 1149.1 master
n
Load-on-the-fly (LotF) and Preload operating modes
supported
n
On-Board Sequencer allows multi-vector operations
such as those required to load data into an FPGA
n
On-Board Compares support TDI validation against
preloaded expected data
n
32-bit Linear Feedback Shift Register (LFSR) at the Test
Data In (TDI) port
n
State, Shift, and BIST macros allow predetermined TMS
sequences to be utilized
n
Operates at 3.3v supply voltages w/ 5V tolerant I/O
n
Outputs support Power-Down TRI-STATE mode.
SCANSTA101 Architecture
10121502
FIGURE 1.
October 2002
SCANST
A101
Low
V
oltage
IEEE
1
149.1
ST
A
Master
2002 National Semiconductor Corporation
DS101215
www.national.com
SCANSTA101 Architecture
(Continued)
Figure 1 shows a high level view of the SCANSTA101 Scan
Master and its interface groups. Table 1 provides a brief
description of each of these interface groups. Table 2 pro-
vides a brief description of the external interfaces. The de-
vice is composed of three interfaces around a dual-port
memory. These interfaces consist of the Parallel Processor
Interface (PPI), Serial Scan Interface (SSI), and Test and
Debug Interface. The System Input block is included only to
designate inputs that have global use across the device. The
Test and Debug interface supports BIST, boundary scan,
and internal scan for this device.
TABLE 1. Interface Descriptions
Interface
Description
Parallel Processor Interface
Used for configuration, ScanMaster scan chain loads and reads, programmable device
file loads and reads, and status monitoring.
Serial Scan Interface
Performs parallel to serial conversion, sequences and formats the outgoing serial
stream to conform to 1149.1 protocol.
Test and Debug Interface
Interfaces used for manufacturing tests, this includes a JTAG interface and a scan
interface. The three scan interface pins are shared with three of the data pins.
System Inputs
Interface inputs for system control, i.e. clock, reset and output tristate control.
Connection Diagrams
10121503
SSOP Package Pinout
(Top View)
10121540
BGA Package Pinout
(Top View)
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TABLE 2. Pin Descriptions
Pin
Description
Name
No.
Pins
I/O
VCC
4
N/A
Power
GND
4
N/A
Ground
D(15:0)
16
I/O
Bidirectional Data Bus. Signals are bonded out for the packaged device.
D15 and D14 are shared pins with SCAN_IN, and SCAN_OUT
respectively.
D(31:16)
(Note 1)
16
I/O
Bidirectional Data Bus. These signals are not available in the packaged
device.
A(4:0)
5
I
Address Bus
SCK
1
I
The system clock that drives all internal timing. TCK_SM is a gated,
divided and buffered version of SCK.
INT
1
O
Interrupt Output
OE
1
I
Output enable that tristates all 1149.1 "_SM" outputs when high.
DTACK
1
O
DTACK is used to synchronize asynchronous transfers between the host
and the STA101. When CE is high, DTACK is tristated. When CE is low,
DTACK is enabled. DTACK goes low when data has been registered and
then goes tri-state when the cycle has completed.
R/W
1
I
R/W defines a PPI cycle. Read when high, write when low.
STB
1
I
Strobe is used for timing all PPI transfers. D(15:0), or D(31:0) in 32-bit
mode, are tristated when STB is high. Data valid setup is with respect to
the falling edge of STB and data valid hold is with respect to rising edge of
STB.
CE
1
I
Chip Enable, when low, enables the PPI for data transfers. CE can remain
low during back-to-back accesses. D(15:0), or D(31:0) in 32-bit mode, and
DTACK are tristated when CE is high.
RST
1
I
Asynchronous reset, when low, initializes the STA101.
TDO
1
O
Test Data Out is the serial scan output from the STA101. TDO is enabled
when OE is low.
TDI
1
I
Test Data In is the serial scan input to the STA101.
TMS
1
I
Test Mode Select. The Test Mode Select pin is a serial input used to
accept control logic to the Test & debug interface.
TCK
1
I
Test Clock Input for 1149.1
TRST
1
I
Test Reset
TDI_SM
1
I
Scan Master Test Data Input in the Serial Scan Interface
TDO_SM
1
O
Scan Master Test Data Output in the Serial Scan Interface
TMS_SM
1
O
Scan Master Test Mode Select in the Serial Scan Interface
TCK_SM
1
O
Scan Master Test Clock in the Serial Scan Interface
TRST0_SM
1
O
Scan Master Test Reset output in the Serial Scan Interface
TRST1_SM
(Note 1)
1
O
Redundent ScanMaster TRST. This signal is not available for the
packaged device.
TRIST_SM
1
O
The TRI-STATE notification pin exerts a high signal when TDO_SM is
TRI-STATED
Note 1: D(31:16) in the Parallel Processor Interface and TRST1_SM in the Serial Scan Interface are not bonded out for the packaged part. These are used in the
32-bit Macro Mode only.
SCANST
A101
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3
Absolute Maximum Ratings
(Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
-0.5V to +4.0V
DC Input Diode Current (I
IK
)
V
I
= -0.5V
-20 mA
DC Input Voltage (V
I
)
-0.5V to +4.0V
DC Output Diode Current (I
OK
)
V
O
= -0.5V
-20 mA
DC Output Voltage (V
O
)
-0.5V to +4.0V
DC Output Source/Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
50 mA
per Output Pin
DC Latchup Source or Sink Current
300 mA
Junction Temperature
Plastic
+150C
Storage Temperature
-65C to +150C
Lead Temperature (Solder, 4sec)
49L BGA
220C
Max Pkg Power Capacity
@
25C
49L BGA
1.47W
Thermal Resistance (
JA
)
49L BGA
85C/W
Package Derating
11.8mW/C above
+25C
ESD Last Passing Voltage (Min)
2000V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
3.0V to 3.6V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
-40C to +85C
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of SCAN STA products outside of recommended operation
conditions.
DC Electrical Characteristics
Over recommended operating supply voltage and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Max
Units
V
IH
Minimum High Input Voltage
V
OUT
= 0.1V or V
CC
- 0.1V
2.1
V
V
IL
Maximum Low Input Voltage
V
OUT
= 0.1V or V
CC
- 0.1V
0.8
V
V
OH
Minimum High Output Voltage
I
OUT
= -100 A, V
IN
= V
IL
or V
IH
V
CC
-0.2V
V
Minimum High Output Voltage,
TDO_SM, TMS_SM, TCK_SM, TRST0_SM
outputs only
I
OH
= -24 mA, V
IN
= V
IL
or V
IH
2.2
V
Minimum High Output Voltage,
All other outputs including 1149.1
I
OH
= -12 mA, V
IN
= V
IL
or V
IH
2.4
V
V
OL
Maximum Low Output Voltage
I
OUT
= +100 A, V
IN
= V
IL
or V
IH
0.2
V
Maximum Low Output Voltage,
TDO_SM, TMS_SM, TCK_SM, TRST0_SM
outputs only
I
OL
= 24 mA, V
IN
= V
IL
or V
IH
0.5
V
Maximum Low Output Voltage,
all other outputs including 1149.1
I
OL
= 12mA, V
IN
= V
IL
or V
IH
0.4
V
I
IN
Maximum Input Leakage Current, All pins
except TDI, TMS, TRST, TDI_SM
V
IN
= V
CC
for TDI, OE, V
IN
= V
CC
,
GND for All Others
5.0
A
I
ILR
Maximum Input Leakage Current, TDI, TMS,
TRST, TDI_SM
V
IN
= GND
-45
-200
A
I
IH
Maximum Input Leakage Current, TDI, TMS,
TRST, TDI_SM
V
IN
= V
CC
5.0
A
I
OZ
Maximum TRI-STATE Leakage Current
V
IN
= V
CC
, GND, V
IN
(OE, R/W,
CE, STB) = VIL, VIH
5.0
A
I
OFF
Power Off Leakage Current
V
CC
= 0.0V
5.0
A
All pins except TDI, TMS, TRST, and
TDI_SM
I
CC
Maximum Quiescent Supply Current
250
A
I
CCmax
Maximum Supply Current
All inputs low
1.2
mA
I
CCT
Maximum I
CC
/Input
V
IN
= V
CC
- 0.6V
250
A
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A101
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AC Electrical Characteristics/Operating Requirements
Over recommended operating
supply voltage and temperature ranges unless otherwise specified. C
L
= 50 pF, R
L
= 500
unless otherwise specified.
Symbol
Parameter
Conditions
# of SCK
(Notes 3, 4)
Min
Max
Units
PARALLEL PROCESSOR INTERFACE (PPI)
t
S1
Set Up Time
Figures 11, 12
0
ns
CE, R/W, Addr, Data to STB
t
H1
Hold Time
Figures 11, 12
0
ns
CE, R/W, Addr, Data to STB
t
D1
Propagation Delay
Figure 11
2 or 3
11.5
ns
STB low to DTACK low, Register Write
t
D1
Propagation Delay
Figure 12
4 or 5
11.5
ns
STB low to DTACK low, Register Read
t
D1
Propagation Delay
Figure 11
3 or 4
11.5
ns
STB low to DTACK low, Memory Write: 16-bit first
access
t
D1
Propagation Delay
Figure 11
7 or 8
11.5
ns
STB low to DTACK low, Memory Write: 16-bit second
access
t
D1
Propagation Delay
Figure 12
9 or 10
11.5
ns
STB low to DTACK low, Memory Read: 16-bit first
access
t
D1
Propagation Delay
Figure 12
3 or 4
11.5
ns
STB low to DTACK low, Memory Read: 16-bit
second access
t
D2
Propagation Delay
Figure 11
1 or 2
10.0
ns
STB high to DTACK TRISTATE, Register Write
t
D2
Propagation Delay
Figure 12
1 or 2
10.0
ns
STB high to DTACK TRISTATE, Register Read
t
D2
Propagation Delay
Figure 11
1 or 2
10.0
ns
STB high to DTACK TRISTATE, Memory Write:
16-bit first access
t
D2
Propagation Delay
Figure 11
1 or 2
10.0
ns
STB high to DTACK TRISTATE, Memory Write:
16-bit second access
t
D2
Propagation Delay
Figure 12
1 or 2
10.0
ns
STB high to DTACK TRISTATE, Memory Read:
16-bit first access
t
D2
Propagation Delay
Figure 12
1 or 2
10.0
ns
STB high to DTACK TRISTATE, Memory Read:
16-bit second access
t
D3
Propagation Delay
Figure 12
1
ns
Output data valid to DTACK low, all read cycles
t
pHL1
Propagation Delay
Figure 11
5 or 6
10.5
ns
STB low to INT low, register write (clears Interrupt)
t
W
Clock Pulse Width, SCK, H or L
3.0
ns
f
MAX
Clock Frequency, SCK
66
MHz
t
RELEASE
Release Time, RST to STB
2
ns
Note 3: Due to uncertainty in the relationship of the STB placement to the system clock, SCK, the STB may be detected during the current or the next SCK cycle.
Note 4: An absolute maximum delay can be calculated as: (Max # SCK) x (SCK Period) + t
D
.
For example, for t
D1
(STB low to DTACK low, register write), the # SCK cycles is 2 or 3 and the delay, t
D
, is 11.5ns. For a SCK with a 100ns period, the absolute
maximum delay is (3 x 100ns) + 11.5, or 311.5ns.
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A101
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