TL H 5688
DAC1006DAC1007DAC1008
m
P
Compatible
Double-Buffered
D
t
o
A
Converters
January 1995
DAC1006 DAC1007 DAC1008 mP Compatible
Double-Buffered D to A Converters
General Description
The DAC1006 7 8 are advanced CMOS Si-Cr 10- 9- and
8-bit accurate multiplying DACs which are designed to inter-
face directly with the 8080 8048 8085 Z-80 and other pop-
ular microprocessors These DACs appear as a memory lo-
cation or an I O port to the mP and no interfacing logic is
needed
These devices combined with an external amplifier and
voltage reference can be used as standard D A converters
and they are very attractive for multiplying applications
(such as digitally controlled gain blocks) since their linearity
error is essentially independent of the voltage reference
They become equally attractive in audio signal processing
equipment as audio gain controls or as programmable at-
tenuators which marry high quality audio signal processing
to digitally based systems under microprocessor control
All of these DACs are double buffered They can load all 10
bits or two 8-bit bytes and the data format is left justified
The analog section of these DACs is essentially the same
as that of the DAC1020
The DAC1006 series are the 10-bit members of a family of
microprocessor-compatible DAC's (MICRO-DAC
TM
's) For
applications requiring other resolutions the DAC0830 series
(8 bits) and the DAC1208 and DAC1230 (12 bits) are avail-
able alternatives
Part
Accuracy
Pin
Description
(bits)
DAC1006
10
For left-
DAC1007
9
20
justified
DAC1008
8
data
MICRO-DAC
TM
and BI-FET
TM
are trademarks of National Semiconductor Corp
Features
Y
Uses easy to adjust END POINT specs NOT BEST
STRAIGHT LINE FIT
Y
Low power consumption
Y
Direct interface to all popular microprocessors
Y
Integrated thin film on CMOS structure
Y
Double-buffered single-buffered or flow through digital
data inputs
Y
Loads two 8-bit bytes or a single 10-bit word
Y
Logic inputs which meet TTL voltage level specs (1 4V
logic threshold)
Y
Works with
g
10V reference
full 4-quadrant multiplica-
tion
Y
Operates STAND ALONE (without mP) if desired
Y
Available in 0 3
standard 20-pin package
Y
Differential non-linearity selection available as special
order
Key Specifications
Y
Output Current Settling Time
500 ns
Y
Resolution
10 bits
Y
Linearity
10 9 and 8 bits
(guaranteed over temp )
Y
Gain Tempco
b
0 0003% of FS C
Y
Low Power Dissipation
20 mW
(including ladder)
Y
Single Power Supply
5 to 15 V
DC
Typical Application
DAC1006 1007 1008
NOTE FOR DETAILS OF BUS
CONNECTION SEE SECTION 6 0
TL H 5688 1
C1995 National Semiconductor Corporation
RRD-B30M115 Printed in U S A
Absolute Maximum Ratings
(Notes 1
2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (V
CC
)
17 V
DC
Voltage at Any Digital Input
V
CC
to GND
Voltage at V
REF
Input
g
25V
Storage Temperature Range
b
65 C to
a
150 C
Package Dissipation at T
A
e
25 C (Note 3)
500 mW
DC Voltage Applied to I
OUT1
or I
OUT2
(Note 4)
b
100 mV to V
CC
ESD Susceptibility (Note 11)
800V
Lead Temp (Soldering 10 seconds)
Dual-In-Line Package (plastic)
260 C
Dual-In-Line Package (ceramic)
300 C
Operating Ratings
(Note 1)
Temperature Range
T
MIN
s
T
A
s
T
MAX
Part numbers with
``LCN'' and ``LCWN'' suffix
0 C to 70 C
Voltage at Any Digital Input
V
CC
to GND
Electrical Characteristics
Tested at V
CC
e
4 75 V
DC
and 15 75 V
DC
T
A
e
25 C V
REF
e
10 000 V
DC
unless otherwise noted
See
V
CC
e
12V
DC
g
5%
V
CC
e
5V
DC
g
5%
Parameter
Conditions
Note
to 15V
DC
g
5%
Units
Min
Typ
Max
Min
Typ
Max
Resolution
10
10
bits
Linearity Error
Endpoint adjust only
4 7
T
MIN
k
T
A
k
T
MAX
6
b
10V
s
V
REF
s
a
10V
5
DAC1006
0 05
0 05
% of FSR
DAC1007
0 1
0 1
% of FSR
DAC1008
0 2
0 2
% of FSR
Differential
Endpoint adjust only
4 7
Nonlinearity
T
MIN
k
T
A
k
T
MAX
6
b
10V
s
V
REF
s
a
10V
5
DAC1006
0 1
0 1
% of FSR
DAC1007
0 2
0 2
% of FSR
DAC1008
0 4
0 4
% of FSR
Monotonicity
T
MIN
k
T
A
k
T
MAX
4 6
b
10V
s
V
REF
s
a
10V
5
DAC1006
10
10
bits
DAC1007
9
9
bits
DAC1008
8
8
bits
Gain Error
Using internal R
fb
b
10V
s
V
REF
s
a
10V
5
b
1 0
g
0 3
1 0
b
1 0
g
0 3
1 0
% of FS
Gain Error Tempco
T
MIN
k
T
A
k
T
MAX
6
Using internal R
fb
9
b
0 0003
b
0 001
b
0 0006
b
0 002 % of FS C
Power Supply
All digital inputs
Rejection
latched high
V
CC
e
14 5V to 15 5V
0 003
0 008
% FSR V
11 5V to 12 5V
0 004
0 010
% FSR V
4 75V to 5 25V
0 033
0 10
% FSR V
Reference Input
Resistance
10
15
20
10
15
20
kX
Output Feedthrough
V
REF
e
20V
p-p
f
e
100 kHz
Error
All data inputs
90
90
mV
p-p
latched low
Output
I
OUT1
All data inputs
60
60
pF
Capacitance
I
OUT2
latched low
250
250
pF
I
OUT1
All data inputs
250
250
pF
I
OUT2
latched high
60
60
pF
Supply Current Drain
T
MIN
s
T
A
s
T
MAX
6
0 5
3 5
0 5
3 5
mA
2
Electrical Characteristics
Tested at V
CC
e
4 75 V
DC
and 15 75 V
DC
T
A
e
25 C V
REF
e
10 000 V
DC
unless otherwise noted (Continued)
See
V
CC
e
12V
DC
g
5%
V
CC
e
5V
DC
g
5%
Parameter
Conditions
Note
to 15V
DC
g
5%
Units
Min
Typ
Max
Min
Typ
Max
Output Leakage
T
MIN
s
T
A
s
T
MAX
6
Current
I
OUT1
All data inputs
latched low
10
200
200
nA
I
OUT2
All data inputs
latched high
200
200
nA
Digital Input
T
MIN
s
T
A
s
T
MAX
6
Voltages
Low level
LCN and LCWM suffix
0 8 0 8
0 7 0 8
V
DC
High level (all parts)
2 0
2 0
V
DC
Digital Input
T
MIN
s
T
A
s
T
MAX
6
Currents
Digital inputs
k
0 8V
b
40
b
150
b
40
b
150
m
A
DC
Digital inputs
l
2 0V
1 0
a
10
1 0
a
10
m
A
DC
Current Settling
t
S
V
IL
e
0V V
IH
e
5V
500
500
ns
Time
Write and XFER
t
W
V
IL
e
0V V
IH
e
5V
Pulse Width
T
A
e
25 C
8
150
60
320
200
ns
T
MIN
s
T
A
s
T
MAX
9
320
100
500
250
ns
Data Set Up Time
t
DS
V
IL
e
0V V
IH
e
5V
T
A
e
25 C
9
150
80
320
170
ns
T
MIN
s
T
A
s
T
MAX
320
120
500
250
ns
Data Hold Time
t
DH
V
IL
e
OV V
IH
e
5V
T
A
e
25 C
9
200
100
320
220
ns
T
MIN
s
T
A
s
T
MAX
250
120
500
320
ns
Control Set Up
t
CS
V
IL
e
0V V
IL
e
5V
Time
T
A
e
25 C
9
150
60
320
180
ns
T
MIN
s
T
A
s
T
MAX
320
100
500
260
ns
Control Hold Time
t
CH
V
IL
e
0V V
IH
e
5V
T
A
e
25 C
9
10
0
10
0
ns
T
MIN
s
T
A
s
T
MAX
10
0
10
0
ns
Note 1
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions
Note 2
All voltages are measured with respect to GND unless otherwise specified
Note 3
This 500 mW specification applies for all packages The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify
the power dissipation) removes concern for heat sinking
Note 4
For current switching applications both I
OUT1
and I
OUT2
must go to ground or the ``Virtual Ground'' of an operational amplifier The linearity error is
degraded by approximately V
OS
d
V
REF
For example if V
REF
e
10V then a 1 mV offset V
OS
on I
OUT1
or I
OUT2
will introduce an additional 0 01% linearity error
Note 5
Guaranteed at V
REF
e g
10 V
DC
and V
REF
e g
1 V
DC
Note 6
T
MIN
e
0 C and T
MAX
e
70 C for ``LCN'' and ``LCWM'' suffix parts
Note 7
The unit ``FSR'' stands for ``Full Scale Range '' ``Linearity Error'' and ``Power Supply Rejection'' specs are based on this unit to eliminate dependence on a
particular V
REF
value and to indicate the true performance of the part The ``Linearity Error'' specification of the DAC1006 is ``0 05% of FSR (MAX) '' This
guarantees that after performing a zero and full scale adjustment (See Sections 2 5 and 2 6) the plot of the 1024 analog voltage outputs will each be within
0 05%
c
V
REF
of a straight line which passes through zero and full scale
Note 8
This specification implies that all parts are guaranteed to operate with a write pulse or transfer pulse width (t
W
) of 320 ns A typical part will operate with t
W
of only 100 ns The entire write pulse must occur within the valid data interval for the specified t
W
t
DS
t
DH
and t
S
to apply
Note 9
Guaranteed by design but not tested
Note 10
A 200 nA leakage current with R
fb
e
20K and V
REF
e
10V corresponds to a zero error of (200
c
10
b
9c
20
c
10
3
)
c
100
d
10 which is 0 04% of FS
Note 11
Human body model 100 pF discharged through a 1 5 kX resistor
3
Switching Waveforms
TL H 5688 2
Typical Performance Characteristics
Errors vs Supply Voltage
Errors vs Temperature
Write Width t
W
Control Setup Time t
CS
Data Setup Time t
DS
Data Hold Time t
DH
Digital Threshold
vs Supply Voltage
Digital Input Threshold
vs Temperature
TL H 5688 3
4
Block and Connection Diagrams
DAC1006 1007 1008 (20-Pin Parts)
USE DAC1006 1007 1008
FOR LEFT JUSTIFIED DATA
TL H 5688 5
DAC1006 1007 1008
(20-Pin Parts)
Dual-In-Line Package
TL H 5688 28
Top View
See Ordering Information
DAC1006 1007 1008
Simple Hookup for a ``Quick Look''
A TOTAL OF 10
INPUT SWITCHES
1K RESISTORS
TL H 5688 7
Notes
1 For V
REF
e b
10 240 V
DC
the output voltage steps are approximately 10 mV each
2 SW1 is a normally closed switch While SW1 is closed the DAC register is latched and new data
can be loaded into the input latch via the 10 SW2 switches
When SW1 is momentarily opened the new data is transferred from the input latch to the DAC register and is latched when SW1 again closes
5
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