TL F 10201
93L34
8-Bit
Addressable
Latch
June 1989
93L34
8-Bit Addressable Latch
General Description
The 93L34 is an 8-bit addressable latch designed for gener-
al purpose storage applications in digital systems It is a
multifunctional device capable of storing single line data in
eight addressable latches and being a one-of-eight decoder
and demultiplexer with active level HIGH outputs The de-
vice also incorporates an active LOW common clear for re-
setting all latches as well as an active LOW enable
Features
Y
Serial to parallel capability
Y
Eight bits of storage with output of each bit available
Y
Random (addressable) data entry
Y
Active high demultiplexing or decoding capability
Y
Easily expandable
Y
Common conditional clear
Connection Diagram
Dual-In-Line Package
TL F 10201 1
Order Number 93L34DMQB or 93L34FMQB
See NS Package Number J16A or W16A
Logic Symbol
TL F 10201 2
V
CC
e
Pin 16
GND
e
Pin 8
Pin Names
Description
A0 A3
Address Inputs
D
Data Input
E
Enable Input (Active LOW)
CL
Clear Input (Active LOW)
Q0 Q7
Parallel Latch Outputs
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
5 5V
Operating Free Air Temperature Range
Military
b
55 C to
a
125 C
Storage Temperature Range
b
65 C to
a
150 C
Note
The ``Absolute Maximum Ratings'' are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ``Electrical Characteristics''
table are not guaranteed at the absolute maximum ratings
The ``Recommended Operating Conditions'' table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
Parameter
93L34 (Mil)
Units
Min
Nom
Max
V
CC
Supply Voltage
4 5
5
5 5
V
V
IH
High Level Input Voltage
2
V
V
IL
Low Level Input Voltage
0 7
V
I
OH
High Level Output Voltage
b
400
m
A
I
OL
Low Level Output Current
4 8
mA
T
A
Free Air Operating Temperature
b
55
125
C
t
s
(H)
Setup Time HIGH D to E
45
ns
t
h
(H)
Hold Time HIGH D to E
b
5
ns
t
s
(L)
Setup Time LOW D to E
45
ns
t
h
(L)
Hold Time LOW D to E
b
7
ns
t
s
(H)
Setup Time HIGH or LOW
10
ns
t
s
(L)
A
n
to E
10
t
w
(L)
E Pulse Width LOW
26
ns
t
w
(L)
CL Pulse Width LOW
35
ns
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 1)
V
I
Input Clamp Voltage
V
CC
e
Min I
I
e b
10 mA
b
1 5
V
V
OH
High Level Output Voltage
V
CC
e
Min I
OH
e
Max
2 4
V
V
IL
e
Max V
IH
e
Min
V
OL
Low Level Output Voltage
V
CC
e
Min I
OL
e
Max
0 3
V
V
IH
e
Min V
IL
e
Max
I
I
Input Current
Max
V
CC
e
Max V
I
e
5 5V
1
mA
Input Voltage
I
IH
High Level Input Current
V
CC
e
Max V
I
e
2 4V
Inputs
20
m
A
E
30
I
IL
Low Level Input Current
V
CC
e
Max V
I
e
0 3V
Inputs
b
0 4
mA
E
b
0 6
I
OS
Short Circuit
V
CC
e
Max (Note 2)
b
2 5
b
25
mA
Output Current
I
CC
Supply Current
V
CC
e
Max (Note 3)
21
mA
Note 1
All typicals are at V
CC
e
5V T
A
e
25 C
Note 2
Not more than one output should be shorted at a time and the duration should not exceed one second
Note 3
I
CC
is measured with all outputs open and all inputs grounded
2
Switching Characteristics
V
CC
e a
5 0V T
A
e a
25 C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
C
L
e
15 pF
Units
Min
Max
t
PLH
Propagation Delay
45
ns
t
PHL
E to Q
n
42
t
PLH
Propagation Delay
65
ns
t
PHL
D to Q
n
45
t
PLH
Propagation Delay
66
ns
t
PHL
A
n
to Q
n
66
t
PHL
Propagation Delay
55
ns
CL to Q
n
Functional Description
The 93L34 has four modes of operation which are shown in
the Mode Select Table In the addressable latch mode data
on the data line (D) is written into the addressed latch The
addressed latch will follow the Data input with all non-ad-
dressed latches remaining in their previous states In the
memory mode all latches remain in their previous state and
are unaffected by the data or address inputs To eliminate
the possibility of entering erroneous data into the latches
the Enable should be held HIGH while the Address lines are
changing In the 1-of-8 decoding or demultiplexing mode
the addressed output will follow the state of the D input with
all other outputs in the LOW state In the clear mode all
outputs are LOW and unaffected by the address and data
inputs When operating the 93L34 as an addressable latch
changing more than one bit of the address could impose a
transient wrong address Therefore this should only be
done while in the memory mode
Mode Select Table
E
CL
Mode
L
H
Addressable Latch
H
H
Memory
L
L
Active HIGH 8-Channel Demultiplexer
H
L
Clear
3
PDF 
ZIP
