DS1776
PI-Bus Transceiver
General Description
The DS1776 is an octal PI-bus Transceiver. The A to B path
is latched. B outputs are open collector with series Schottky
diode, ensuring minimum B output loading. B outputs also
have ramped rise and fall times (2.5 ns typical), ensuring
minimum PI-bus ringing. B inputs have glitch rejection cir-
cuitry, 4 ns typical.
Designed using National's Bi-CMOS process for both low
operating and disabled power. AC performance is optimized
for the PI-Bus inter-operability requirements.
The DS1776 is an octal latched transceiver and is intended
to provide the electrical interface to a high performance
wired-or bus. This bus has a loaded characteristic imped-
ance range of 20
to 50
and is terminated on each end
with a 30
to 40
resistor.
The DS1776 is an octal bidirectional transceiver with open
collector B and TRI-STATE
A port output drivers. A latch
function is provided for the A port signals. The B port output
driver is designed to sink 100 mA from 2V and features a
controlled linear ramp to minimize crosstalk and ringing on
the bus.
A separate high level control voltage (V
X
) is provided to pre-
vent the A side output high level from exceeding future high
density processor supply voltage levels. For 5V systems, V
X
is tied to V
CC
.
Features
n
Mil-Std-883C qualified
n
Similar to BTL
n
Low power I
CCL
= 41 mA max
n
B output controlled ramp rate
n
B input noise immunity, typically 4 ns
n
Available in 28-pin DIP, Flatpak and CLCC
n
Pin and function compatible with Signetics 54F776
Pin Configurations
Logic Symbol
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
Pin Configuration
DS010875-1
Order Number DS1776E/883 or DS1776J/883
See NS Package E28A or J28B
Pin Configuration
DS010875-2
DS010875-3
January 1996
DS1776
PI-Bus
T
ransceiver
1999 National Semiconductor Corporation
DS010875
www.national.com
MIL-STD-883C
DEVICE SPECIFICATIONS
Absolute Maximum Ratings
(Notes 1, 2)
The 883 specifications are written to reflect the Rel Elec-
trical Test Specifications (RETS) established by National
Semiconductor for this product. For a copy of the latest
RETS please contact your local National Semiconductor
sales office or distributor.
Supply Voltage (V
CC
)
-0.5V to +7.0V
V
X
, V
OH
Output Level Control Voltage
(A Outputs)
-0.5V to +7.0V
OEB n, OEA, LE Input Voltage (V
I
)
-0.5V to +7.0V
A0A7, B0B7 Input Voltage (V
I
)
-0.5V to +5.5V
Input Current (I
I
)
-40 mA to +5 mA
Voltage Applied to Output in
High Output State (V
O
)
-0.5V to +V
CC
V
A0A7 Current Applied to Output
in Low Output State (I
O
)
40 mA
B0B7 Current Applied to Output
in Low Output State (I
O
)
200 mA
Storage Temperature Range (T
STG
)
-65C to +150C
Lead Temperature
(Soldering 10 Sec.)
260C
ESD Tolerance:
C
ZAP
= 120 pF, R
ZAP
= 1500
0.5 kV
Operating Conditions
Min
Max
Units
Supply Voltage (V
CC
)
4.5
5.5
V
Operating Temp. Range (T
A
)
-55
+125
C
Input Rise or Fall Times (t
r
, t
f
)
50
ns
PI Bus Transceiver DS1776
DC Electrical Characteristics
V
CC
= 5V
10% (Unless Otherwise Specified) DC testing temp. groups: 1 = +25C, 2 = +125C, 3 = -55C
Symbol
Parameter
Conditions
Temp.
Min
Typ
Max Units
(Notes 3, 5)
Group
(Note 4)
V
IH
High Level Input
Except Bn
1, 2, 3
2
V
Voltage
Bn
1.6
V
V
IL
Low Level Input
Except Bn
1, 2, 3
0.8
V
Voltage
Bn
1.45
V
I
OH
High Level Output
An
V
IN
= V
IH
1, 2, 3
-3
mA
Current
V
OH
= V
CC
- 2.0V
High Level Output
Bn
V
CC
= Max, OEA = LE
100
A
Current
V
IH
= 2.0V, V
OH
=
2.1V
I
OL
Low Level Output
An
V
IN
= V
IL
1, 2, 3
Current
V
OL
= 0.5V
20
mA
Bn
V
OL
= 1.15V
100
mA
I
IK
Input Clamp
Current
Except An
1, 2, 3
-18
mA
An
-40
mA
I
OZ
TRI-STATE
Output
An
1, 2, 3
70
A
Leakage Current
Bn
V
OH
High Level Output
An
V
CC
= Min, V
IH
= 1.9V
I
OH
= - 3 mA
1, 2, 3
2.5
V
CC
V
Voltage
V
X
= V
CC
I
OH
= -0.4
mA
2.5
V
X
V
V
X
= 3.13V to
3.47V
V
OL
Low Output
An
V
CC
=Min, V
IL
=1.2V
I
OL
=20 mA,
0.5
V
Level Voltage
V
X
=V
CC
Bn
V
CC
=Min, V
IL
=0.8V
I
OL
=100 mA
1, 2, 3
1.15
V
I
OL
=4 mA
0.4
V
IK
Input Clamp
An
V
CC
=Min, I
I
=-40 mA
1, 2, 3
-0.5
V
www.national.com
2
DC Electrical Characteristics
(Continued)
V
CC
= 5V
10% (Unless Otherwise Specified) DC testing temp. groups: 1 = +25C, 2 = +125C, 3 = -55C
Symbol
Parameter
Conditions
Temp.
Min
Typ
Max Units
(Notes 3, 5)
Group
(Note 4)
Voltage
Except An
V
CC
=Min, I
I
=-18 mA
-1.2
V
I
IH2
Input Current
OEBn, OEA,
LE
V
CC
=Min, V
I
=7.0V
1, 2, 3
1
100
A
at Max
An
V
CC
=Min, V
I
=5.5V
0.01
1
mA
Input Voltage
Bn
V
CC
=Min, V
I
=5.5V
0.01
1
mA
I
IH1
Input Current
OEB, OEA, LE
V
CC
=Max, V
I
=2.7V
20
A
at Max
B0B7
V
CC
=Max, V
I
=2.1V
100
A
Input Voltage
I
IL
Low Level
OEB, OEA, LE
V
CC
=Max, V
I
=0.5V
2, 3
-40
A
Input Current
1
-20
A
Bn
V
CC
=Max, V
I
=0.3V
1, 2, 3
-100
A
I
OZH
TRI-STATE
An
V
CC
=Max, V
O
=2.7V
1, 2, 3
+I
IH
Output Current,
70
A
High Level
Voltage Applied
I
OZH
TRI-STATE
An
V
CC
=Max, V
O
=0.5V
1, 2, 3
+I
IL
Output Current,
-70
A
Low Level
Voltage Applied
I
X
High Level
V
CC
=Max, V
X
=V
CC
,
1, 2, 3
Control Current
LE=OEA=OEBn=2.7V
-100
100
A
An=2.7V, Bn=2.0V
V
CC
=Max, V
X
=3.14V &
3.47V,
1, 2, 3
LE=OEA=OEBn=2.7V,
-10
10
mA
An=2.7V, Bn=2.0V
I
OS
Short-Circuit
An
V
CC
=Max, Bn=1.9V,
1, 2, 3
Output Current
OEA=2.0V,
OEBn=2.7V
-60
-75
-150
mA
(Note 6)
I
CC
Supply Current
I
CCH
V
CC
=Max, V
IH
(A)=5.0V
1, 2
37
mA
I
CCH
3
41
mA
I
CCL
V
CC
=Max, V
IL
(A)=0.3V
1, 2, 3
38
mA
I
CCZ
V
CC
=Max, V
IL
(A)=0.3V
1, 2, 3
35
mA
I
OFF
Power Off
Bn=2.1V, V
CC
=0.0V,
1, 2, 3
100
A
Output Current
V
IL
=Max or V
IH
=Min
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. Unless otherwise specified, V
X
= V
CC
for all test conditions.
Note 4: All typical values are at V
CC
= 5V, T
A
= 25C.
Note 5: Due to test equipment limitations, actual test conditions are for V
IH
= 1.9V and for V
IL
= 1.2V, however the specified test limits and conditions are guaranteed.
Note 6: Not more than one output should be shorted at a time. For testing [<i]nfOS the use of high speed test apparatus and/or sample-and-hold techniques are
preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip tem-
perature above normal and thereby cause invalid readings in other parameter tests. In any squence of parameter test [<i]nfOStest should be performed last.
Note 7: Not more than one output should be shorted at a time. For testing I
OS
, the use of high speed test apparatus and/or sample-and-hold techniques are pref-
erable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip tem-
perature above normal and thereby cause invalid readings in other parameter tests. In any squence of parameter test, I
OS
tests should be performed last.
www.national.com
3
AC Electrical Characteristics
V
CC
= 5V
10% (Unless otherwise specified)
AC testing temp. groups: 1 = +25C, 2 = +125C, 3 = -55C
Path
Parameter
Conditions
Temp.
Min
Max
Units
Group
B-TO-A PATH
t
PLH
Propagation Delay B to A
Waveform 1, 2
1, 2, 3
4.5
17
ns
t
PHL
6
17
ns
t
PZH
Output Enable OEA to A
Waveform 3, 4
1, 2, 3
4
17
ns
t
PZL
4
17
ns
t
PHZ
Output Disable OEA to A
Waveform 3, 4
1, 2, 3
2
12
ns
t
PLZ
2
13
ns
A-TO-B PATH
t
PLH
Propagation Delay A to B
Waveform 1, 2
1, 3
2
13
ns
2
2
17
ns
t
PHL
1, 2, 3
2.5
13
ns
t
PLH
Propagation Delay LE to B
Waveform 1, 2
1, 3
2
16
ns
2
2
22
ns
t
PHL
1, 2, 3
2
16
ns
t
PLH
Enable/Disable OEBn to B
Waveform 1, 2
1, 3
2
13
ns
2
2
16
ns
t
PHL
1
3.5
14
ns
2
3.5
13
ns
3
3.5
16
ns
t
TLH
Transition Time, B Side
1.3V to 1.7V
1, 3
0.5
5.5
ns
2
0.5
10
ns
t
THL
1.7V to 1.3V
1
0.5
5.5
ns
2
0.5
7
ns
3
0.5
10
ns
SETUP/HOLD/PULSE WIDTH SPECS
t
S
A to LE Setup
Waveform 5
1, 2, 3
7
ns
t
H
A to LE Hold
Waveform 5
1, 2, 3
0
ns
t
W
LE Pulse Width Low
Waveform 5
1, 2, 3
12
ns
Description
PIN DESCRIPTION
TABLE 1. Pin Description
Symbol
Pins
Type
Name and Function
A0
3
I/O
A1
5
I/O
A2
6
I/O
A3
7
I/O
TTL Level, latched input/TRI-STATE output (with V
X
control option)
A4
9
I/O
A5
10
I/O
A6
12
I/O
A7
13
I/O
www.national.com
4
Description
(Continued)
TABLE 1. Pin Description (Continued)
Symbol
Pins
Type
Name and Function
B0
27
I/O
Data input with special threshold circuitry to reject noise/Open Collector output,
High current drive
B1
26
I/O
B2
24
I/O
B3
23
I/O
B4
21
I/O
B5
20
I/O
B6
19
I/O
B7
17
I/O
OEB 0
15
I
Enables the B outputs when both pins are low
OEB 1
16
I
OEA
2
I
Enables the A outputs when High
LE
28
I
Latched when High (a special delay feature is built in for proper enabling
times)
V
X
14
I
Clamping voltage keeping V
OH
from rising above V
X
(V
X
= V
CC
for normal
use)
www.national.com
5
PDF 
ZIP