TL F 9581
54F74F651
54F74F652
TransceiversRegisters
December 1994
54F 74F651
54F 74F652
Transceivers Registers
General Description
These devices consist of bus transceiver circuits with
D-type flip-flops and control circuitry arranged for multi-
plexed transmission of data directly from the input bus or
from internal registers Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to HIGH logic level Output Enable pins (OEAB OEBA) are
provided to control the transceiver function
Features
Y
Independent registers for A and B buses
Y
Multiplexed real-time and stored data
Y
Choice of non-inverting and inverting data paths
'F651 inverting
'F652 non-inverting
Y
Guaranteed 4000V minimum ESD protection
Commercial
Military
Package
Package Description
Number
74F651SPC
N24C
24-Lead (0 300 Wide) Molded Dual-In-Line
54F651SDM (Note 2)
J24F
24-Lead (0 300 Wide) Ceramic Dual-In-Line
74F651SC (Note 1)
M24B
24-Lead (0 300 Wide) Molded Small Outline JEDEC
54F651FM (Note 2)
W24C
24-Lead Cerpack
54F651LM (Note 2)
E28A
24-Lead Ceramic Leadless Chip Carrier Type C
74F652SPC
N24C
24-Lead (0 300 Wide) Molded Dual-In-Line
54F652SDM (Note 2)
J24F
24-Lead (0 300 Wide) Ceramic Dual-In-Line
74F652SC (Note 1)
M24B
24-Lead (0 300 Wide) Molded Small Outline JEDEC
54F652FM (Note 2)
W24C
24-Lead Cerpack
54F652LM (Note 2)
E28A
24-Lead Ceramic Leadless Chip Carrier Type C
Note 1
Devices also available in 13
reel Use suffix
e
SCX
Note 2
Military grade device with environmental and burn-in processing Use suffix
e
DMQB FMQB and LMQB
Connection Diagrams
Pin Assignment
DIP SOIC and Flatpak
TL F 9581 3
Pin Assignment
for LCC
TL F 9581 4
TRI-STATE
is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M75 Printed in U S A
Logic Symbols
IEEE IEC
'F651
TL F 9581 1
'F651
TL F 9581 2
IEEE IEC
'F652
TL F 9581 10
'F652
TL F 9581 11
Unit Loading Fan Out
54F 74F
Pin Names
Description
U L
Input I
IH
I
IL
HIGH LOW
Output I
OH
I
OL
A
0
A
7
B
0
B
7
A and B Inputs
1 0 1 0
20 mA
b
0 6 mA
TRI-STATE Outputs 600 106 6 (80)
b
12 mA 64 mA (48 mA)
CPAB CPBA
Clock Inputs
1 0 1 0
20 mA
b
0 6 mA
SAB SBA
Select Inputs
1 0 1 0
20 mA
b
0 6 mA
OEAB OEBA
Output Enable Inputs
1 0 1 0
20 mA
b
0 6 mA
2
Logic Diagrams
'F652
TL F 9581 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
'F651
TL F 9581 12
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
3
Functional Description
In the transceiver mode data present at the HIGH imped-
ance port may be stored in either the A or B register or both
The select (SAB SBA) controls can multiplex stored and
real-time
The examples in
Figure 1 demonstrate the four fundamental
bus-management functions that can be performed with the
Octal bus transceivers and receivers
Data on the A or B data bus or both can be stored in the
internal D flip-flop by LOW to HIGH transitions at the appro-
priate Clock Inputs (CPAB CPBA) regardless of the Select
or Output Enable Inputs When SAB and SBA are in the real
time transfer mode it is also possible to store data without
using the internal D flip-flops by simultaneously enabling
OEAB and OEBA In this configuration each Output reinforc-
es its Input Thus when all other data sources to the two
sets of bus lines are in a HIGH impedance state each set of
bus lines will remain at its last state
Note A Real-Time
Transfer Bus B to Bus A
TL F 9581 6
OEAB
OEBA
CPAB
CPBA
SAB
SBA
L
L
X
X
X
L
Note B Real-Time
Transfer Bus A to Bus B
TL F 9581 7
OEAB
OEBA
CPAB
CPBA
SAB
SBA
H
H
X
X
L
X
Note C Storage
TL F 9581 8
OEAB
OEBA
CPAB
CPBA
SAB
SBA
X
H
L
X
X
X
L
X
X
L
X
X
L
H
L
L
X
X
Note D Transfer Storage
Data to A or B
TL F 9581 9
OEAB
OEBA
CPAB
CPBA
SAB
SBA
H
L
H or L
H or L
H
X
FIGURE 1
Inputs
Inputs Outputs (Note 1)
Operating Mode
OEAB
OEBA
CPAB
CPBA
SAB
SBA
A
0
thru A
7
B
0
thru B
7
L
H
H or L
H or L
X
X
Input
Input
Isolation
L
H
L
L
X
X
Store A and B Data
X
H
L
H or L
X
X
Input
Not Specified
Store A Hold B
H
H
L
L
X
X
Input
Output
Store A in Both Registers
L
X
H or L
L
X
X
Not Specified
Input
Hold A Store B
L
L
L
L
X
X
Output
Input
Store B in Both Registers
L
L
X
X
X
L
Output
Input
Real-Time B Data to A Bus
L
L
X
H or L
X
H
Store B Data to A Bus
H
H
X
X
L
X
Input
Output
Real-Time A Data to B Bus
H
H
H or L
X
H
X
Stored A Data to B Bus
H
L
H or L
H or L
H
H
Output
Output
Stored A Data to B Bus and
Stored B Data to A Bus
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
L
e
LOW to HIGH Clock Transition
Note 1
The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs Data input functions are always enabled i e data at the
bus pins will be stored on every LOW to HIGH transition on the clock inputs
4
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Storage Temperature
b
65 C to
a
150 C
Ambient Temperature under Bias
b
55 C to
a
125 C
Junction Temperature under Bias
b
55 C to
a
175 C
Plastic
b
55 C to
a
150 C
V
CC
Pin Potential to
Ground Pin
b
0 5V to
a
7 0V
Input Voltage (Note 2)
b
0 5V to
a
7 0V
Input Current (Note 2)
b
30 mA to
a
5 0 mA
Note 1
Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired Functional operation under
these conditions is not implied
Note 2
Either voltage limit or current limit is sufficient to protect inputs
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
Standard Output
b
0 5V to V
CC
TRI-STATE Output
b
0 5V to
a
5 5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min)
4000V
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
b
55 C to
a
125 C
Commercial
0 C to
a
70 C
Supply Voltage
Military
a
4 5V to
a
5 5V
Commercial
a
4 5V to
a
5 5V
DC Electrical Characteristics
Symbol
Parameter
54F 74F
Units
V
CC
Conditions
Min
Typ
Max
V
IH
Input HIGH Voltage
2 0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0 8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
b
1 2
V
Min
I
IN
e b
18 mA (Non I O Pins)
V
OH
Output HIGH
54F 10% V
CC
2 0
V
Min
I
OH
e b
12 mA (A
n
B
n
)
Voltage
74F 10% V
CC
2 0
I
OH
e b
15 mA (A
n
B
n
)
V
OL
Output LOW
54F 10% V
CC
0 55
V
Min
I
OL
e
48 mA (A
n
B
n
)
Voltage
74F 10% V
CC
0 55
I
OL
e
64 mA (A
n
B
n
)
I
IH
Input HIGH
54F
20 0
m
A
Max
V
IN
e
2 7V
Current
74F
5 0
(Non I O Pins)
I
BVI
Input HIGH Current
54F
100
m
A
Max
V
IN
e
7 0V
Breakdown Test
74F
7 0
I
BVIT
Input HIGH Current
54F
1 0
mA
Max
V
IN
e
5 5V
Breakdown (I O)
74F
0 5
(A
n
B
n
)
I
CEX
Output HIGH
54F
250
m
A
Max
V
OUT
e
V
CC
Leakage Current
74F
50
V
ID
Input Leakage
74F
4 75
V
0 0
I
ID
e
1 9 mA
Test
All Other Pins Grounded
I
OD
Output Leakage
74F
3 75
m
A
0 0
VI
IOD
e
150 mV
Circuit Current
All Other Pins Grounded
I
IL
Input LOW Current
b
0 6
mA
Max
V
IN
e
0 5V (Non I O Pins)
I
IH
a
I
OZH
Output Leakage Current
70
m
A
Max
V
OUT
e
2 7V (A
n
B
n
)
I
IL
a
I
OZL
Output Leakage Current
b
650
m
A
Max
V
OUT
e
0 5V (A
n
B
n
)
I
OS
Output Short-Circuit Current
b
100
b
225
mA
Max
V
OUT
e
0V
I
ZZ
Bus Drainage Test
500
m
A
0 0V
V
OUT
e
5 25V
I
CCH
Power Supply Current
105
135
mA
Max
V
O
e
HIGH
I
CCL
Power Supply Current
118
150
mA
Max
V
O
e
LOW
I
CCZ
Power Supply Current
115
150
mA
Max
V
O
e
HIGH Z
5
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