NT7702
240 Output LCD Segment/Common Driver
1
V1.0
Features
(Segment mode)
!
Shift Clock frequency:
20 MHz (Max.) (V
DD
= 5 V
10%)
!
Adopts a data bus system
!
4-bit/8-bit parallel input modes are selectable with a
mode (MD) pin
!
Automatic transfer function with an enable signal
!
Automatic counting function when in the chip select
mode, causes the internal clock to be stopped by
automatically counting 240 bits of input data
(Common mode)
!
Shift clock frequency :
4.0 MHz (Max.)
!
Built-in 240-bits bidirectional shift register (divisible into
120-bits x 2)
!
Available in a single mode (240-bits shift register) or in a
dual mode(120-bits shift register x 2)
1. Y1
Y240
Single mode
2. Y240
Y1
Single mode
3. Y1
Y120, Y121
Y240
Dual mode
4. Y240
Y121, Y120
Y1
Dual mode
The above 4 shift directions are pin-selectable
(Both for segment mode and common mode)
!
Supply voltage for LCD driver: 15.0 to 30.0 V
!
Number of LCD driver outputs: 240
!
Low output impedance
!
Low power consumption
!
Supply voltage for the logic system: +2.5 to +5.5 V
!
COMS process
!
Package: 272pin TCP (Tape Carrier Package)
!
Not designed or rated as radiation hardened
General Description
The NT7702 is a 240-bit output segment/common driver LSI
suitable for driving large scale dot matrix LCD panels using
as PDA/personal computers/work stations. Through the use
of SST (Super Slim TCP) technology, it is ideal for
substantially decreasing the size of the frame section of the
LCD module. The NT7702 is good as both a segment driver
and as a common driver, and a low power consuming, high-
precision LCD panel display can be assembled using the
NT7702. In the segment mode, the data input is selected as
4bit parallel input mode or as 8bit parallel input mode by a
mode (MD) pin. In the common mode, the data input/output
pins are bi-directional and the four data shift directions are
pin-selectable.
Pin Configuration
NT7702
151
Y
1
2
3
Y
1
2
2
Y
1
2
1
Y
1
2
0
Y
1
1
9
Y
1
1
8
152
153
154
155
150
33
Y
5
Y
4
Y
3
Y
2
Y
1
D
U
M
M
Y
34
35
36
37
272
Y
2
3
6
Y
2
3
7
Y
2
3
8
Y
2
3
9
Y
2
4
0
D
U
M
M
Y
271 270 269 268
1
D
U
M
M
Y
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
V
0
L
V
0
L
V
1
2
L
V
4
3
L
V
5
L
V
S
S
V
D
D
S
/
C
E
I
O
2
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
X
C
K
D
I
S
P
O
F
F
L
P
E
I
O
1
F
R
L
/
R
M
D
N
C
V
S
S
N
C
V
5
R
V
4
3
R
V
1
2
R
V
0
R
V
0
R
D
U
M
M
Y
NT7702
2
Pad Configuration
NT7702
x
x
x
x
x
x
x
x
x
x
x
ALK_R
ALK_L
1
44
45
58
59
282
283
296
x
Dummy Pad
x
Dummy Pad
Block Diagram
240 Bits 4 Level Driver
240 Bits Level Shifter
240 Bits Line Latch/Shift Register
Y1
Y2
Y239 Y240
V
43R
V
12R
V
0R
Level
Shifter
FR
DISPOFF
Active
Control
EIO
1
EIO
2
Control
Logic
SP Conversion & Data Control
(4 to 8 or 8 to 8)
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
L/R
MD
S/C
8Bits
2
Data
Latch
Data Latch Control
/8
/240
/240
V
DD
V
SS
V
SS
/16
/16
/16
/16
/16
LP
XCK
V
5R
V
5L
V
12L
V
0L
V
43L
NT7702
3
Pin Description
Pin No.
Designation
I/O
Description
1, 2
V
0L
P
Power supply for LCD driver
3
V
12L
P
Power supply for LCD driver
4
V
43L
P
Power supply for LCD driver
5
V
5L
P
Power supply for LCD driver
6
V
SS
P
Ground (0V), these two pads must be connected to each other
7
V
DD
P
Power supply for the logic system (+2.5 to +5.5V)
8
S/C
I
Segment mode/common mode selection
9
EIO
2
I/O
Input/output for chip select or data of the shift register
10 - 16
D0 - D6
I
Display data input for segment mode
17
D7
I
Display data input for Segment mode/ Dual mode data input
18
XCK
I
Display data shift clock input for segment mode
19
DISPOFF
I
Control input for deselect output level
20
LP
I
Latch pulse input/shift clock input for the shift register
21
EIO
1
I/O
Input/output for chip select or data of the shift register
22
FR
I
AC-converting signal input for LCD driver waveform
23
L/R
I
Display data shift direction selection
24
MD
I
Mode selection input
25, 27
NC
-
No connected
26
V
SS
P
Ground (0V), these two pads must be connected to each other
28
V
5R
P
Power supply for LCD driver
29
V
43R
P
Power supply for LCD driver
30
V
12R
P
Power supply for LCD driver
31, 32
V
0R
P
Power supply for LCD driver
33 - 272
Y1 - Y240
O
LCD driver output
NT7702
4
Pad Description
Pad No.
Designation
I/O
Description
1, 2
V
5L
P
Power supply for LCD driver
3, 4
V
SS
P
Ground (0V), these two pads must be connected to each other
5, 6
V
DD
P
Power supply for the logic system (+2.5 to +5.5V)
7, 8
S/C
I
Segment mode/common mode selection
9, 10
EIO
2
I/O
Input/output for chip select or data of the shift register
11, 12 - 23, 24
D0 - D6
I
Display data input for segment mode
25, 26
D7
I
Display data input for Segment mode/ Dual mode data input
27, 28
XCK
I
Display data shift clock input for segment mode
29, 30
DISPOFF
I
Control input for deselect output level
31, 32
LP
I
Latch pulse input/shift clock input for the shift register
33, 34
EIO
1
I/O
Input/output for chip select or data of the shift register
35, 36
FR
I
AC-converting signal input for LCD driver waveform
37, 38
L/R
I
Display data shift direction selection
39, 40
MD
I
Mode selection input
41, 42
V
SS
P
Ground (0V), these two pads must be connected to each other
43, 44
V
5R
P
Power supply for LCD driver
45, 46
V
43R
P
Power supply for LCD driver
47, 48
V
12R
P
Power supply for LCD driver
49, 50
V
0R
P
Power supply for LCD driver
51 - 290
Y1 - Y240
O
LCD driver output
291, 292
V
0L
P
Power supply for LCD driver
293, 294
V
12L
P
Power supply for LCD driver
295, 296
V
43L
P
Power supply for LCD driver
NT7702
5
Input / Output Circuits
V
DD
V
SS
I
Input Signal
Applicable Pins
L/R, S/C, D0 - D6,
, LP, FR, MD
DISPOFF
Input Circuit (1)
V
DD
I
V
SS
V
SS
Input Signal
Control Signal
Applicable Pins
D7, XCK
Input Circuit (2)
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